1 /*
2  * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
3  * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /* ZynqMP power management enums and defines */
9 
10 #ifndef ZYNQMP_PM_DEFS_H
11 #define ZYNQMP_PM_DEFS_H
12 
13 /*********************************************************************
14  * Macro definitions
15  ********************************************************************/
16 
17 /*
18  * Version number is a 32bit value, like:
19  * (PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR
20  */
21 #define PM_VERSION_MAJOR	1U
22 #define PM_VERSION_MINOR	1U
23 
24 #define PM_VERSION	((PM_VERSION_MAJOR << 16U) | PM_VERSION_MINOR)
25 
26 /*
27  * PM API versions
28  */
29 
30 /* Expected version of firmware APIs */
31 #define FW_API_BASE_VERSION		(1U)
32 /* Expected version of firmware API for feature check */
33 #define FW_API_VERSION_2		(2U)
34 /* Version of APIs implemented in TF-A */
35 #define TFA_API_BASE_VERSION		(1U)
36 /* Updating the QUERY_DATA API versioning as the bitmask functionality
37  * support is added in the v2.*/
38 #define TFA_API_QUERY_DATA_VERSION	(2U)
39 
40 /* Capabilities for RAM */
41 #define PM_CAP_ACCESS	0x1U
42 #define PM_CAP_CONTEXT	0x2U
43 
44 /* APU processor states */
45 #define PM_PROC_STATE_FORCEDOFF		0U
46 #define PM_PROC_STATE_ACTIVE		1U
47 #define PM_PROC_STATE_SLEEP		2U
48 #define PM_PROC_STATE_SUSPENDING	3U
49 
50 #define PM_SET_SUSPEND_MODE		0xa02
51 
52 /*********************************************************************
53  * Enum definitions
54  ********************************************************************/
55 
56 enum pm_node_id {
57 	NODE_UNKNOWN = 0,
58 	NODE_APU,
59 	NODE_APU_0,
60 	NODE_APU_1,
61 	NODE_APU_2,
62 	NODE_APU_3,
63 	NODE_RPU,
64 	NODE_RPU_0,
65 	NODE_RPU_1,
66 	NODE_PLD,
67 	NODE_FPD,
68 	NODE_OCM_BANK_0,
69 	NODE_OCM_BANK_1,
70 	NODE_OCM_BANK_2,
71 	NODE_OCM_BANK_3,
72 	NODE_TCM_0_A,
73 	NODE_TCM_0_B,
74 	NODE_TCM_1_A,
75 	NODE_TCM_1_B,
76 	NODE_L2,
77 	NODE_GPU_PP_0,
78 	NODE_GPU_PP_1,
79 	NODE_USB_0,
80 	NODE_USB_1,
81 	NODE_TTC_0,
82 	NODE_TTC_1,
83 	NODE_TTC_2,
84 	NODE_TTC_3,
85 	NODE_SATA,
86 	NODE_ETH_0,
87 	NODE_ETH_1,
88 	NODE_ETH_2,
89 	NODE_ETH_3,
90 	NODE_UART_0,
91 	NODE_UART_1,
92 	NODE_SPI_0,
93 	NODE_SPI_1,
94 	NODE_I2C_0,
95 	NODE_I2C_1,
96 	NODE_SD_0,
97 	NODE_SD_1,
98 	NODE_DP,
99 	NODE_GDMA,
100 	NODE_ADMA,
101 	NODE_NAND,
102 	NODE_QSPI,
103 	NODE_GPIO,
104 	NODE_CAN_0,
105 	NODE_CAN_1,
106 	NODE_EXTERN,
107 	NODE_APLL,
108 	NODE_VPLL,
109 	NODE_DPLL,
110 	NODE_RPLL,
111 	NODE_IOPLL,
112 	NODE_DDR,
113 	NODE_IPI_APU,
114 	NODE_IPI_RPU_0,
115 	NODE_GPU,
116 	NODE_PCIE,
117 	NODE_PCAP,
118 	NODE_RTC,
119 	NODE_LPD,
120 	NODE_VCU,
121 	NODE_IPI_RPU_1,
122 	NODE_IPI_PL_0,
123 	NODE_IPI_PL_1,
124 	NODE_IPI_PL_2,
125 	NODE_IPI_PL_3,
126 	NODE_PL,
127 	NODE_GEM_TSU,
128 	NODE_SWDT_0,
129 	NODE_SWDT_1,
130 	NODE_CSU,
131 	NODE_PJTAG,
132 	NODE_TRACE,
133 	NODE_TESTSCAN,
134 	NODE_PMU,
135 	NODE_MAX,
136 };
137 
138 enum pm_request_ack {
139 	REQ_ACK_NO = 1,
140 	REQ_ACK_BLOCKING,
141 	REQ_ACK_NON_BLOCKING,
142 };
143 
144 enum pm_suspend_reason {
145 	SUSPEND_REASON_PU_REQ = 201,
146 	SUSPEND_REASON_ALERT,
147 	SUSPEND_REASON_SYS_SHUTDOWN,
148 };
149 
150 enum pm_ram_state {
151 	PM_RAM_STATE_OFF = 1,
152 	PM_RAM_STATE_RETENTION,
153 	PM_RAM_STATE_ON,
154 };
155 
156 /**
157  * enum pm_boot_status - enum represents the boot status of the PM.
158  * @PM_INITIAL_BOOT: boot is a fresh system startup.
159  * @PM_RESUME: boot is a resume.
160  * @PM_BOOT_ERROR: error, boot cause cannot be identified.
161  *
162  */
163 enum pm_boot_status {
164 	PM_INITIAL_BOOT,
165 	PM_RESUME,
166 	PM_BOOT_ERROR,
167 };
168 
169 /**
170  * enum pm_shutdown_type - enum represents the shutdown type of the PM.
171  * @PMF_SHUTDOWN_TYPE_SHUTDOWN: shutdown.
172  * @PMF_SHUTDOWN_TYPE_RESET: reset/reboot.
173  * @PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY: set the shutdown/reboot scope.
174  *
175  */
176 enum pm_shutdown_type {
177 	PMF_SHUTDOWN_TYPE_SHUTDOWN,
178 	PMF_SHUTDOWN_TYPE_RESET,
179 	PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY,
180 };
181 
182 /**
183  * enum pm_shutdown_subtype - enum represents the shutdown subtype of the PM.
184  * @PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM: shutdown/reboot APU subsystem only.
185  * @PMF_SHUTDOWN_SUBTYPE_PS_ONLY: shutdown/reboot entire PS (but not PL).
186  * @PMF_SHUTDOWN_SUBTYPE_SYSTEM: shutdown/reboot entire system.
187  *
188  */
189 enum pm_shutdown_subtype {
190 	PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM,
191 	PMF_SHUTDOWN_SUBTYPE_PS_ONLY,
192 	PMF_SHUTDOWN_SUBTYPE_SYSTEM,
193 };
194 
195 /**
196  * enum pm_pll_mode - enum represents the mode of the PLL.
197  * @PM_PLL_MODE_RESET: PLL is in reset (not locked).
198  * @PM_PLL_MODE_INTEGER: PLL is locked in integer mode.
199  * @PM_PLL_MODE_FRACTIONAL: PLL is locked in fractional mode.
200  * @PM_PLL_MODE_MAX: Represents the maximum mode value for the PLL.
201  */
202 enum pm_pll_mode {
203 	PM_PLL_MODE_RESET,
204 	PM_PLL_MODE_INTEGER,
205 	PM_PLL_MODE_FRACTIONAL,
206 	PM_PLL_MODE_MAX,
207 };
208 
209 /**
210  * enum pm_clock_div_id - enum represents the clock division identifiers in the
211  *                        PM.
212  * @PM_CLOCK_DIV0_ID: Clock divider 0.
213  * @PM_CLOCK_DIV1_ID: Clock divider 1.
214  */
215 enum pm_clock_div_id {
216 	PM_CLOCK_DIV0_ID,
217 	PM_CLOCK_DIV1_ID,
218 };
219 
220 #endif /* ZYNQMP_PM_DEFS_H */
221