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Searched refs:MPIDR_AFFLVL_MASK (Results 1 – 25 of 38) sorted by relevance

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/trusted-firmware-a-3.7.0/plat/arm/common/
Darm_topology.c25 valid_mask = ~(MPIDR_AFFLVL_MASK | in arm_check_mpidr()
26 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | in arm_check_mpidr()
27 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | in arm_check_mpidr()
28 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT)); in arm_check_mpidr()
29 cluster_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; in arm_check_mpidr()
30 cpu_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in arm_check_mpidr()
31 pe_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in arm_check_mpidr()
35 MPIDR_AFFLVL_MASK); in arm_check_mpidr()
37 MPIDR_AFFLVL_MASK); in arm_check_mpidr()
/trusted-firmware-a-3.7.0/plat/mediatek/mt8186/
Dplat_topology.c42 if ((mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) != 0) { in plat_core_pos_by_mpidr()
54 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
55 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
/trusted-firmware-a-3.7.0/plat/mediatek/mt8192/
Dplat_topology.c47 if (mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) { in plat_core_pos_by_mpidr()
59 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
60 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
/trusted-firmware-a-3.7.0/plat/mediatek/mt8195/
Dplat_topology.c42 if ((mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) != 0) { in plat_core_pos_by_mpidr()
54 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
55 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
/trusted-firmware-a-3.7.0/plat/intel/soc/common/
Dsocfpga_topology.c36 cluster_id = (mpidr >> PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
37 cpu_id = (mpidr >> PLAT_CPU_ID_MPIDR_AFF_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
/trusted-firmware-a-3.7.0/plat/rpi/common/
Drpi3_topology.c46 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
47 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
/trusted-firmware-a-3.7.0/plat/amlogic/common/
Daml_topology.c43 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
44 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
/trusted-firmware-a-3.7.0/plat/arm/board/a5ds/
Da5ds_topology.c38 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
39 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
/trusted-firmware-a-3.7.0/plat/qemu/common/
Dtopology.c47 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
48 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
/trusted-firmware-a-3.7.0/plat/aspeed/ast2700/
Dplat_topology.c31 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
32 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
/trusted-firmware-a-3.7.0/plat/hisilicon/hikey960/
Dhikey960_topology.c52 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
53 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
/trusted-firmware-a-3.7.0/plat/hisilicon/hikey/
Dhikey_topology.c52 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
53 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
/trusted-firmware-a-3.7.0/plat/mediatek/mt8173/
Dplat_topology.c46 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
47 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
/trusted-firmware-a-3.7.0/plat/mediatek/mt8183/
Dplat_topology.c45 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
46 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
/trusted-firmware-a-3.7.0/plat/st/stm32mp1/
Dstm32mp1_topology.c41 cluster_id = (mpidr_copy >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
42 cpu_id = (mpidr_copy >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
/trusted-firmware-a-3.7.0/plat/socionext/uniphier/
Duniphier_topology.c31 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
35 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
/trusted-firmware-a-3.7.0/plat/socionext/synquacer/
Dsq_topology.c19 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
23 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
/trusted-firmware-a-3.7.0/plat/renesas/common/
Dplat_topology.c33 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
34 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
/trusted-firmware-a-3.7.0/plat/qemu/qemu_sbsa/
Dsbsa_topology.c49 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
50 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
/trusted-firmware-a-3.7.0/drivers/arm/css/scpi/
Dcss_scpi.c199 cpu = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in scpi_get_css_power_state()
200 cluster = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; in scpi_get_css_power_state()
202 cpu = mpidr & MPIDR_AFFLVL_MASK; in scpi_get_css_power_state()
203 cluster = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in scpi_get_css_power_state()
/trusted-firmware-a-3.7.0/plat/imx/imx93/aarch64/
Dplat_helpers.S56 mov x1, #MPIDR_AFFLVL_MASK
67 mov x1, #MPIDR_AFFLVL_MASK
/trusted-firmware-a-3.7.0/drivers/arm/css/scp/
Dcss_pm_scpi.c103 element = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in css_scp_get_power_state()
105 element = mpidr & MPIDR_AFFLVL_MASK; in css_scp_get_power_state()
/trusted-firmware-a-3.7.0/plat/rockchip/common/
Dplat_topology.c26 cpu_id = mpidr & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
/trusted-firmware-a-3.7.0/plat/marvell/armada/common/
Dmarvell_topology.c51 MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)) in marvell_check_mpidr()
/trusted-firmware-a-3.7.0/plat/mediatek/mt8192/aarch64/
Dplat_helpers.S46 mov x1, #MPIDR_AFFLVL_MASK

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