/trusted-firmware-a-3.7.0/plat/arm/common/ |
D | arm_topology.c | 25 valid_mask = ~(MPIDR_AFFLVL_MASK | in arm_check_mpidr() 26 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | in arm_check_mpidr() 27 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | in arm_check_mpidr() 28 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT)); in arm_check_mpidr() 29 cluster_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; in arm_check_mpidr() 30 cpu_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in arm_check_mpidr() 31 pe_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in arm_check_mpidr() 35 MPIDR_AFFLVL_MASK); in arm_check_mpidr() 37 MPIDR_AFFLVL_MASK); in arm_check_mpidr()
|
/trusted-firmware-a-3.7.0/plat/mediatek/mt8186/ |
D | plat_topology.c | 42 if ((mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) != 0) { in plat_core_pos_by_mpidr() 54 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr() 55 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
/trusted-firmware-a-3.7.0/plat/mediatek/mt8192/ |
D | plat_topology.c | 47 if (mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) { in plat_core_pos_by_mpidr() 59 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr() 60 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
/trusted-firmware-a-3.7.0/plat/mediatek/mt8195/ |
D | plat_topology.c | 42 if ((mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) != 0) { in plat_core_pos_by_mpidr() 54 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr() 55 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
/trusted-firmware-a-3.7.0/plat/intel/soc/common/ |
D | socfpga_topology.c | 36 cluster_id = (mpidr >> PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr() 37 cpu_id = (mpidr >> PLAT_CPU_ID_MPIDR_AFF_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
/trusted-firmware-a-3.7.0/plat/rpi/common/ |
D | rpi3_topology.c | 46 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr() 47 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
/trusted-firmware-a-3.7.0/plat/amlogic/common/ |
D | aml_topology.c | 43 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr() 44 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
/trusted-firmware-a-3.7.0/plat/arm/board/a5ds/ |
D | a5ds_topology.c | 38 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr() 39 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
/trusted-firmware-a-3.7.0/plat/qemu/common/ |
D | topology.c | 47 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr() 48 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
/trusted-firmware-a-3.7.0/plat/aspeed/ast2700/ |
D | plat_topology.c | 31 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr() 32 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
/trusted-firmware-a-3.7.0/plat/hisilicon/hikey960/ |
D | hikey960_topology.c | 52 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr() 53 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
/trusted-firmware-a-3.7.0/plat/hisilicon/hikey/ |
D | hikey_topology.c | 52 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr() 53 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
/trusted-firmware-a-3.7.0/plat/mediatek/mt8173/ |
D | plat_topology.c | 46 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr() 47 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
/trusted-firmware-a-3.7.0/plat/mediatek/mt8183/ |
D | plat_topology.c | 45 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr() 46 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
/trusted-firmware-a-3.7.0/plat/st/stm32mp1/ |
D | stm32mp1_topology.c | 41 cluster_id = (mpidr_copy >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr() 42 cpu_id = (mpidr_copy >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
/trusted-firmware-a-3.7.0/plat/socionext/uniphier/ |
D | uniphier_topology.c | 31 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr() 35 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
/trusted-firmware-a-3.7.0/plat/socionext/synquacer/ |
D | sq_topology.c | 19 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr() 23 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
/trusted-firmware-a-3.7.0/plat/renesas/common/ |
D | plat_topology.c | 33 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr() 34 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
/trusted-firmware-a-3.7.0/plat/qemu/qemu_sbsa/ |
D | sbsa_topology.c | 49 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr() 50 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
/trusted-firmware-a-3.7.0/drivers/arm/css/scpi/ |
D | css_scpi.c | 199 cpu = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in scpi_get_css_power_state() 200 cluster = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; in scpi_get_css_power_state() 202 cpu = mpidr & MPIDR_AFFLVL_MASK; in scpi_get_css_power_state() 203 cluster = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in scpi_get_css_power_state()
|
/trusted-firmware-a-3.7.0/plat/imx/imx93/aarch64/ |
D | plat_helpers.S | 56 mov x1, #MPIDR_AFFLVL_MASK 67 mov x1, #MPIDR_AFFLVL_MASK
|
/trusted-firmware-a-3.7.0/drivers/arm/css/scp/ |
D | css_pm_scpi.c | 103 element = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in css_scp_get_power_state() 105 element = mpidr & MPIDR_AFFLVL_MASK; in css_scp_get_power_state()
|
/trusted-firmware-a-3.7.0/plat/rockchip/common/ |
D | plat_topology.c | 26 cpu_id = mpidr & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
/trusted-firmware-a-3.7.0/plat/marvell/armada/common/ |
D | marvell_topology.c | 51 MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)) in marvell_check_mpidr()
|
/trusted-firmware-a-3.7.0/plat/mediatek/mt8192/aarch64/ |
D | plat_helpers.S | 46 mov x1, #MPIDR_AFFLVL_MASK
|