Searched refs:MIDR_PN_SHIFT (Results 1 – 16 of 16) sorted by relevance
| /trusted-firmware-a-3.7.0/plat/imx/imx93/aarch64/ |
| D | plat_helpers.S | 28 ubfx x0, x0, MIDR_PN_SHIFT, #12
29 cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
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| /trusted-firmware-a-3.7.0/plat/imx/common/ |
| D | imx8_helpers.S | 33 ubfx x0, x0, MIDR_PN_SHIFT, #12
34 cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
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| /trusted-firmware-a-3.7.0/services/std_svc/errata_abi/ |
| D | cpu_errata_info.h | 34 #define EXTRACT_PARTNUM(x) ((x >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
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| /trusted-firmware-a-3.7.0/plat/rockchip/common/aarch64/ |
| D | plat_helpers.S | 36 ubfx x0, x0, MIDR_PN_SHIFT, #12
37 cmp w0, #((CORTEX_A72_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
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| /trusted-firmware-a-3.7.0/include/lib/cpus/aarch32/ |
| D | cpu_macros.S | 180 ubfx r0, r0, #MIDR_PN_SHIFT, #12
181 ldr r1, =((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
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| /trusted-firmware-a-3.7.0/lib/cpus/aarch64/ |
| D | cpuamu.c | 26 (MIDR_PN_MASK << MIDR_PN_SHIFT); in midr_match()
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| /trusted-firmware-a-3.7.0/plat/nuvoton/common/ |
| D | nuvoton_helpers.S | 38 ubfx x0, x0, MIDR_PN_SHIFT, #12
39 cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
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| /trusted-firmware-a-3.7.0/include/lib/cpus/ |
| D | cpu_ops.h | 13 (MIDR_PN_MASK << MIDR_PN_SHIFT)
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| /trusted-firmware-a-3.7.0/plat/renesas/common/include/ |
| D | rcar_def.h | 276 #define MIDR_CA57 (0x0D07U << MIDR_PN_SHIFT)
277 #define MIDR_CA53 (0x0D03U << MIDR_PN_SHIFT)
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| /trusted-firmware-a-3.7.0/plat/renesas/common/aarch64/ |
| D | plat_helpers.S | 352 ubfx x1, x0, MIDR_PN_SHIFT, #12
353 cmp w1, #((CORTEX_A57_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
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| /trusted-firmware-a-3.7.0/plat/nvidia/tegra/common/aarch64/ |
| D | tegra_helpers.S | 65 mov x1, #(MIDR_PN_MASK << MIDR_PN_SHIFT)
67 lsr x0, x0, #MIDR_PN_SHIFT
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| /trusted-firmware-a-3.7.0/include/lib/cpus/aarch64/ |
| D | cpu_macros.S | 252 ubfx x0, x0, MIDR_PN_SHIFT, #12
253 cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
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| /trusted-firmware-a-3.7.0/plat/renesas/rzg/ |
| D | bl2_plat_setup.c | 711 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); in bl2_el3_early_platform_setup()
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| /trusted-firmware-a-3.7.0/include/arch/aarch32/ |
| D | arch.h | 24 #define MIDR_PN_SHIFT U(4) macro
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| /trusted-firmware-a-3.7.0/plat/renesas/rcar/ |
| D | bl2_plat_setup.c | 898 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); in bl2_el3_early_platform_setup()
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| /trusted-firmware-a-3.7.0/include/arch/aarch64/ |
| D | arch.h | 25 #define MIDR_PN_SHIFT U(0x4) macro
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