Searched refs:IMX_IOMUX_GPR_BASE (Results 1 – 9 of 9) sorted by relevance
103 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); in bl31_tzc380_setup()139 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, 0x4E1); in bl31_early_platform_setup2()140 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c); in bl31_early_platform_setup2()141 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000); in bl31_early_platform_setup2()
107 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); in bl31_tzc380_setup()150 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, 0x4c1); in bl31_early_platform_setup2()151 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c); in bl31_early_platform_setup2()152 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000); in bl31_early_platform_setup2()
82 #define IMX_IOMUX_GPR_BASE U(0x30340000) macro
107 #define IMX_IOMUX_GPR_BASE U(0x30340000) macro
90 #define IMX_IOMUX_GPR_BASE U(0x30340000) macro
132 val = mmio_read_32(IMX_IOMUX_GPR_BASE + IOMUXC_GPR10); in bl31_tz380_setup()
405 mmio_setbits_32(IMX_IOMUX_GPR_BASE + 0x4, 1 << 12); in imx_gpc_init()
116 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); in bl31_tzc380_setup()
110 #define IMX_IOMUX_GPR_BASE U(0x30340000) macro