Searched refs:IMX_HDMI_CTL_BASE (Results 1 – 2 of 2) sorted by relevance
132 mmio_write_32(IMX_HDMI_CTL_BASE + TX_CONTROL1, 0x22018); in imx_noc_qos()133 mmio_write_32(IMX_HDMI_CTL_BASE + TX_CONTROL1, 0x22010); in imx_noc_qos()136 hurry = mmio_read_32(IMX_HDMI_CTL_BASE + TX_CONTROL0); in imx_noc_qos()138 mmio_write_32(IMX_HDMI_CTL_BASE + TX_CONTROL0, hurry); in imx_noc_qos()198 mmio_write_32(IMX_HDMI_CTL_BASE + RTX_RESET_CTL0, 0x0); in imx_gpc_pm_domain_enable()200 mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL0, 0xFFFFFFFF); in imx_gpc_pm_domain_enable()201 mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL1, 0x7ffff87e); in imx_gpc_pm_domain_enable()219 mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL0, 0x0); in imx_gpc_pm_domain_enable()220 mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL1, 0x0); in imx_gpc_pm_domain_enable()222 mmio_write_32(IMX_HDMI_CTL_BASE + RTX_RESET_CTL0, 0xffffffff); in imx_gpc_pm_domain_enable()[all …]
129 #define IMX_HDMI_CTL_BASE U(0x32fc0000) macro
