1 /*
2  * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef ARCH_H
8 #define ARCH_H
9 
10 #include <lib/utils_def.h>
11 
12 /*******************************************************************************
13  * MIDR bit definitions
14  ******************************************************************************/
15 #define MIDR_IMPL_MASK		U(0xff)
16 #define MIDR_IMPL_SHIFT		U(24)
17 #define MIDR_VAR_SHIFT		U(20)
18 #define MIDR_VAR_BITS		U(4)
19 #define MIDR_VAR_MASK		U(0xf)
20 #define MIDR_REV_SHIFT		U(0)
21 #define MIDR_REV_BITS		U(4)
22 #define MIDR_REV_MASK		U(0xf)
23 #define MIDR_PN_MASK		U(0xfff)
24 #define MIDR_PN_SHIFT		U(4)
25 
26 /*******************************************************************************
27  * MPIDR macros
28  ******************************************************************************/
29 #define MPIDR_MT_MASK		(U(1) << 24)
30 #define MPIDR_CPU_MASK		MPIDR_AFFLVL_MASK
31 #define MPIDR_CLUSTER_MASK	(MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
32 #define MPIDR_AFFINITY_BITS	U(8)
33 #define MPIDR_AFFLVL_MASK	U(0xff)
34 #define MPIDR_AFFLVL_SHIFT	U(3)
35 #define MPIDR_AFF0_SHIFT	U(0)
36 #define MPIDR_AFF1_SHIFT	U(8)
37 #define MPIDR_AFF2_SHIFT	U(16)
38 #define MPIDR_AFF_SHIFT(_n)	MPIDR_AFF##_n##_SHIFT
39 #define MPIDR_AFFINITY_MASK	U(0x00ffffff)
40 #define MPIDR_AFFLVL0		U(0)
41 #define MPIDR_AFFLVL1		U(1)
42 #define MPIDR_AFFLVL2		U(2)
43 #define MPIDR_AFFLVL(_n)	MPIDR_AFFLVL##_n
44 
45 #define MPIDR_AFFLVL0_VAL(mpidr) \
46 		(((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
47 #define MPIDR_AFFLVL1_VAL(mpidr) \
48 		(((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
49 #define MPIDR_AFFLVL2_VAL(mpidr) \
50 		(((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
51 #define MPIDR_AFFLVL3_VAL(mpidr)	U(0)
52 
53 #define MPIDR_AFF_ID(mpid, n)					\
54 	(((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
55 
56 #define MPID_MASK		(MPIDR_MT_MASK				|\
57 				 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)|\
58 				 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT)|\
59 				 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
60 
61 /*
62  * An invalid MPID. This value can be used by functions that return an MPID to
63  * indicate an error.
64  */
65 #define INVALID_MPID		U(0xFFFFFFFF)
66 
67 /*
68  * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
69  * add one while using this macro to define array sizes.
70  */
71 #define MPIDR_MAX_AFFLVL	U(2)
72 
73 /* Data Cache set/way op type defines */
74 #define DC_OP_ISW			U(0x0)
75 #define DC_OP_CISW			U(0x1)
76 #if ERRATA_A53_827319
77 #define DC_OP_CSW			DC_OP_CISW
78 #else
79 #define DC_OP_CSW			U(0x2)
80 #endif
81 
82 /*******************************************************************************
83  * Generic timer memory mapped registers & offsets
84  ******************************************************************************/
85 #define CNTCR_OFF			U(0x000)
86 /* Counter Count Value Lower register */
87 #define CNTCVL_OFF			U(0x008)
88 /* Counter Count Value Upper register */
89 #define CNTCVU_OFF			U(0x00C)
90 #define CNTFID_OFF			U(0x020)
91 
92 #define CNTCR_EN			(U(1) << 0)
93 #define CNTCR_HDBG			(U(1) << 1)
94 #define CNTCR_FCREQ(x)			((x) << 8)
95 
96 /*******************************************************************************
97  * System register bit definitions
98  ******************************************************************************/
99 /* CLIDR definitions */
100 #define LOUIS_SHIFT		U(21)
101 #define LOC_SHIFT		U(24)
102 #define CLIDR_FIELD_WIDTH	U(3)
103 
104 /* CSSELR definitions */
105 #define LEVEL_SHIFT		U(1)
106 
107 /* ID_DFR0 definitions */
108 #define ID_DFR0_PERFMON_SHIFT		U(24)
109 #define ID_DFR0_PERFMON_MASK		U(0xf)
110 #define ID_DFR0_PERFMON_PMUV3		U(3)
111 #define ID_DFR0_PERFMON_PMUV3P5		U(6)
112 #define ID_DFR0_COPTRC_SHIFT		U(12)
113 #define ID_DFR0_COPTRC_MASK		U(0xf)
114 #define ID_DFR0_COPTRC_SUPPORTED	U(1)
115 #define ID_DFR0_COPTRC_LENGTH		U(4)
116 #define ID_DFR0_TRACEFILT_SHIFT		U(28)
117 #define ID_DFR0_TRACEFILT_MASK		U(0xf)
118 #define ID_DFR0_TRACEFILT_SUPPORTED	U(1)
119 #define ID_DFR0_TRACEFILT_LENGTH	U(4)
120 
121 /* ID_DFR1_EL1 definitions */
122 #define ID_DFR1_MTPMU_SHIFT	U(0)
123 #define ID_DFR1_MTPMU_MASK	U(0xf)
124 #define ID_DFR1_MTPMU_SUPPORTED	U(1)
125 #define ID_DFR1_MTPMU_DISABLED	U(15)
126 
127 /* ID_MMFR3 definitions */
128 #define ID_MMFR3_PAN_SHIFT	U(16)
129 #define ID_MMFR3_PAN_MASK	U(0xf)
130 
131 /* ID_MMFR4 definitions */
132 #define ID_MMFR4_CNP_SHIFT	U(12)
133 #define ID_MMFR4_CNP_LENGTH	U(4)
134 #define ID_MMFR4_CNP_MASK	U(0xf)
135 
136 #define ID_MMFR4_CCIDX_SHIFT	U(24)
137 #define ID_MMFR4_CCIDX_LENGTH	U(4)
138 #define ID_MMFR4_CCIDX_MASK	U(0xf)
139 
140 /* ID_PFR0 definitions */
141 #define ID_PFR0_AMU_SHIFT	U(20)
142 #define ID_PFR0_AMU_LENGTH	U(4)
143 #define ID_PFR0_AMU_MASK	U(0xf)
144 #define ID_PFR0_AMU_NOT_SUPPORTED	U(0x0)
145 #define ID_PFR0_AMU_V1		U(0x1)
146 #define ID_PFR0_AMU_V1P1	U(0x2)
147 
148 #define ID_PFR0_DIT_SHIFT	U(24)
149 #define ID_PFR0_DIT_LENGTH	U(4)
150 #define ID_PFR0_DIT_MASK	U(0xf)
151 #define ID_PFR0_DIT_SUPPORTED	(U(1) << ID_PFR0_DIT_SHIFT)
152 
153 /* ID_PFR1 definitions */
154 #define ID_PFR1_VIRTEXT_SHIFT	U(12)
155 #define ID_PFR1_VIRTEXT_MASK	U(0xf)
156 #define GET_VIRT_EXT(id)	(((id) >> ID_PFR1_VIRTEXT_SHIFT) \
157 				 & ID_PFR1_VIRTEXT_MASK)
158 #define ID_PFR1_GENTIMER_SHIFT	U(16)
159 #define ID_PFR1_GENTIMER_MASK	U(0xf)
160 #define ID_PFR1_GIC_SHIFT	U(28)
161 #define ID_PFR1_GIC_MASK	U(0xf)
162 #define ID_PFR1_SEC_SHIFT	U(4)
163 #define ID_PFR1_SEC_MASK	U(0xf)
164 #define ID_PFR1_ELx_ENABLED	U(1)
165 
166 /* SCTLR definitions */
167 #define SCTLR_RES1_DEF		((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \
168 				 (U(1) << 3))
169 #if ARM_ARCH_MAJOR == 7
170 #define SCTLR_RES1		SCTLR_RES1_DEF
171 #else
172 #define SCTLR_RES1		(SCTLR_RES1_DEF | (U(1) << 11))
173 #endif
174 #define SCTLR_M_BIT		(U(1) << 0)
175 #define SCTLR_A_BIT		(U(1) << 1)
176 #define SCTLR_C_BIT		(U(1) << 2)
177 #define SCTLR_CP15BEN_BIT	(U(1) << 5)
178 #define SCTLR_ITD_BIT		(U(1) << 7)
179 #define SCTLR_Z_BIT		(U(1) << 11)
180 #define SCTLR_I_BIT		(U(1) << 12)
181 #define SCTLR_V_BIT		(U(1) << 13)
182 #define SCTLR_RR_BIT		(U(1) << 14)
183 #define SCTLR_NTWI_BIT		(U(1) << 16)
184 #define SCTLR_NTWE_BIT		(U(1) << 18)
185 #define SCTLR_WXN_BIT		(U(1) << 19)
186 #define SCTLR_UWXN_BIT		(U(1) << 20)
187 #define SCTLR_EE_BIT		(U(1) << 25)
188 #define SCTLR_TRE_BIT		(U(1) << 28)
189 #define SCTLR_AFE_BIT		(U(1) << 29)
190 #define SCTLR_TE_BIT		(U(1) << 30)
191 #define SCTLR_DSSBS_BIT		(U(1) << 31)
192 #define SCTLR_RESET_VAL		(SCTLR_RES1 | SCTLR_NTWE_BIT |		\
193 				SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT)
194 
195 /* SDCR definitions */
196 #define SDCR_SPD(x)		((x) << 14)
197 #define SDCR_SPD_LEGACY		U(0x0)
198 #define SDCR_SPD_DISABLE	U(0x2)
199 #define SDCR_SPD_ENABLE		U(0x3)
200 #define SDCR_SPME_BIT		(U(1) << 17)
201 #define SDCR_TTRF_BIT		(U(1) << 19)
202 #define SDCR_SCCD_BIT		(U(1) << 23)
203 #define SDCR_MTPME_BIT		(U(1) << 28)
204 #define SDCR_RESET_VAL		U(0x0)
205 
206 /* HSCTLR definitions */
207 #define HSCTLR_RES1	((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
208 			 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
209 			 (U(1) << 11) | (U(1) << 4) | (U(1) << 3))
210 
211 #define HSCTLR_M_BIT		(U(1) << 0)
212 #define HSCTLR_A_BIT		(U(1) << 1)
213 #define HSCTLR_C_BIT		(U(1) << 2)
214 #define HSCTLR_CP15BEN_BIT	(U(1) << 5)
215 #define HSCTLR_ITD_BIT		(U(1) << 7)
216 #define HSCTLR_SED_BIT		(U(1) << 8)
217 #define HSCTLR_I_BIT		(U(1) << 12)
218 #define HSCTLR_WXN_BIT		(U(1) << 19)
219 #define HSCTLR_EE_BIT		(U(1) << 25)
220 #define HSCTLR_TE_BIT		(U(1) << 30)
221 
222 /* CPACR definitions */
223 #define CPACR_FPEN(x)		((x) << 20)
224 #define CPACR_FP_TRAP_PL0	UL(0x1)
225 #define CPACR_FP_TRAP_ALL	UL(0x2)
226 #define CPACR_FP_TRAP_NONE	UL(0x3)
227 
228 /* SCR definitions */
229 #define SCR_TWE_BIT		(UL(1) << 13)
230 #define SCR_TWI_BIT		(UL(1) << 12)
231 #define SCR_SIF_BIT		(UL(1) << 9)
232 #define SCR_HCE_BIT		(UL(1) << 8)
233 #define SCR_SCD_BIT		(UL(1) << 7)
234 #define SCR_NET_BIT		(UL(1) << 6)
235 #define SCR_AW_BIT		(UL(1) << 5)
236 #define SCR_FW_BIT		(UL(1) << 4)
237 #define SCR_EA_BIT		(UL(1) << 3)
238 #define SCR_FIQ_BIT		(UL(1) << 2)
239 #define SCR_IRQ_BIT		(UL(1) << 1)
240 #define SCR_NS_BIT		(UL(1) << 0)
241 #define SCR_VALID_BIT_MASK	U(0x33ff)
242 #define SCR_RESET_VAL		U(0x0)
243 
244 #define GET_NS_BIT(scr)		((scr) & SCR_NS_BIT)
245 
246 /* HCR definitions */
247 #define HCR_TGE_BIT		(U(1) << 27)
248 #define HCR_AMO_BIT		(U(1) << 5)
249 #define HCR_IMO_BIT		(U(1) << 4)
250 #define HCR_FMO_BIT		(U(1) << 3)
251 #define HCR_RESET_VAL		U(0x0)
252 
253 /* CNTHCTL definitions */
254 #define CNTHCTL_RESET_VAL	U(0x0)
255 #define PL1PCEN_BIT		(U(1) << 1)
256 #define PL1PCTEN_BIT		(U(1) << 0)
257 
258 /* CNTKCTL definitions */
259 #define PL0PTEN_BIT		(U(1) << 9)
260 #define PL0VTEN_BIT		(U(1) << 8)
261 #define PL0PCTEN_BIT		(U(1) << 0)
262 #define PL0VCTEN_BIT		(U(1) << 1)
263 #define EVNTEN_BIT		(U(1) << 2)
264 #define EVNTDIR_BIT		(U(1) << 3)
265 #define EVNTI_SHIFT		U(4)
266 #define EVNTI_MASK		U(0xf)
267 
268 /* HCPTR definitions */
269 #define HCPTR_RES1		((U(1) << 13) | (U(1) << 12) | U(0x3ff))
270 #define TCPAC_BIT		(U(1) << 31)
271 #define TAM_SHIFT		U(30)
272 #define TAM_BIT			(U(1) << TAM_SHIFT)
273 #define TTA_BIT			(U(1) << 20)
274 #define TCP11_BIT		(U(1) << 11)
275 #define TCP10_BIT		(U(1) << 10)
276 #define HCPTR_RESET_VAL		HCPTR_RES1
277 
278 /* VTTBR definitions */
279 #define VTTBR_RESET_VAL		ULL(0x0)
280 #define VTTBR_VMID_MASK		ULL(0xff)
281 #define VTTBR_VMID_SHIFT	U(48)
282 #define VTTBR_BADDR_MASK	ULL(0xffffffffffff)
283 #define VTTBR_BADDR_SHIFT	U(0)
284 
285 /* HDCR definitions */
286 #define HDCR_MTPME_BIT		(U(1) << 28)
287 #define HDCR_HLP_BIT		(U(1) << 26)
288 #define HDCR_HPME_BIT		(U(1) << 7)
289 #define HDCR_RESET_VAL		U(0x0)
290 
291 /* HSTR definitions */
292 #define HSTR_RESET_VAL		U(0x0)
293 
294 /* CNTHP_CTL definitions */
295 #define CNTHP_CTL_RESET_VAL	U(0x0)
296 
297 /* NSACR definitions */
298 #define NSASEDIS_BIT		(U(1) << 15)
299 #define NSTRCDIS_BIT		(U(1) << 20)
300 #define NSACR_CP11_BIT		(U(1) << 11)
301 #define NSACR_CP10_BIT		(U(1) << 10)
302 #define NSACR_IMP_DEF_MASK	(U(0x7) << 16)
303 #define NSACR_ENABLE_FP_ACCESS	(NSACR_CP11_BIT | NSACR_CP10_BIT)
304 #define NSACR_RESET_VAL		U(0x0)
305 
306 /* CPACR definitions */
307 #define ASEDIS_BIT		(U(1) << 31)
308 #define TRCDIS_BIT		(U(1) << 28)
309 #define CPACR_CP11_SHIFT	U(22)
310 #define CPACR_CP10_SHIFT	U(20)
311 #define CPACR_ENABLE_FP_ACCESS	((U(0x3) << CPACR_CP11_SHIFT) |\
312 				 (U(0x3) << CPACR_CP10_SHIFT))
313 #define CPACR_RESET_VAL		U(0x0)
314 
315 /* FPEXC definitions */
316 #define FPEXC_RES1		((U(1) << 10) | (U(1) << 9) | (U(1) << 8))
317 #define FPEXC_EN_BIT		(U(1) << 30)
318 #define FPEXC_RESET_VAL		FPEXC_RES1
319 
320 /* SPSR/CPSR definitions */
321 #define SPSR_FIQ_BIT		(U(1) << 0)
322 #define SPSR_IRQ_BIT		(U(1) << 1)
323 #define SPSR_ABT_BIT		(U(1) << 2)
324 #define SPSR_AIF_SHIFT		U(6)
325 #define SPSR_AIF_MASK		U(0x7)
326 
327 #define SPSR_E_SHIFT		U(9)
328 #define SPSR_E_MASK		U(0x1)
329 #define SPSR_E_LITTLE		U(0)
330 #define SPSR_E_BIG		U(1)
331 
332 #define SPSR_T_SHIFT		U(5)
333 #define SPSR_T_MASK		U(0x1)
334 #define SPSR_T_ARM		U(0)
335 #define SPSR_T_THUMB		U(1)
336 
337 #define SPSR_MODE_SHIFT		U(0)
338 #define SPSR_MODE_MASK		U(0x7)
339 
340 #define SPSR_SSBS_BIT		BIT_32(23)
341 
342 #define DISABLE_ALL_EXCEPTIONS \
343 		(SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT)
344 
345 #define CPSR_DIT_BIT		(U(1) << 21)
346 /*
347  * TTBCR definitions
348  */
349 #define TTBCR_EAE_BIT		(U(1) << 31)
350 
351 #define TTBCR_SH1_NON_SHAREABLE		(U(0x0) << 28)
352 #define TTBCR_SH1_OUTER_SHAREABLE	(U(0x2) << 28)
353 #define TTBCR_SH1_INNER_SHAREABLE	(U(0x3) << 28)
354 
355 #define TTBCR_RGN1_OUTER_NC	(U(0x0) << 26)
356 #define TTBCR_RGN1_OUTER_WBA	(U(0x1) << 26)
357 #define TTBCR_RGN1_OUTER_WT	(U(0x2) << 26)
358 #define TTBCR_RGN1_OUTER_WBNA	(U(0x3) << 26)
359 
360 #define TTBCR_RGN1_INNER_NC	(U(0x0) << 24)
361 #define TTBCR_RGN1_INNER_WBA	(U(0x1) << 24)
362 #define TTBCR_RGN1_INNER_WT	(U(0x2) << 24)
363 #define TTBCR_RGN1_INNER_WBNA	(U(0x3) << 24)
364 
365 #define TTBCR_EPD1_BIT		(U(1) << 23)
366 #define TTBCR_A1_BIT		(U(1) << 22)
367 
368 #define TTBCR_T1SZ_SHIFT	U(16)
369 #define TTBCR_T1SZ_MASK		U(0x7)
370 #define TTBCR_TxSZ_MIN		U(0)
371 #define TTBCR_TxSZ_MAX		U(7)
372 
373 #define TTBCR_SH0_NON_SHAREABLE		(U(0x0) << 12)
374 #define TTBCR_SH0_OUTER_SHAREABLE	(U(0x2) << 12)
375 #define TTBCR_SH0_INNER_SHAREABLE	(U(0x3) << 12)
376 
377 #define TTBCR_RGN0_OUTER_NC	(U(0x0) << 10)
378 #define TTBCR_RGN0_OUTER_WBA	(U(0x1) << 10)
379 #define TTBCR_RGN0_OUTER_WT	(U(0x2) << 10)
380 #define TTBCR_RGN0_OUTER_WBNA	(U(0x3) << 10)
381 
382 #define TTBCR_RGN0_INNER_NC	(U(0x0) << 8)
383 #define TTBCR_RGN0_INNER_WBA	(U(0x1) << 8)
384 #define TTBCR_RGN0_INNER_WT	(U(0x2) << 8)
385 #define TTBCR_RGN0_INNER_WBNA	(U(0x3) << 8)
386 
387 #define TTBCR_EPD0_BIT		(U(1) << 7)
388 #define TTBCR_T0SZ_SHIFT	U(0)
389 #define TTBCR_T0SZ_MASK		U(0x7)
390 
391 /*
392  * HTCR definitions
393  */
394 #define HTCR_RES1			((U(1) << 31) | (U(1) << 23))
395 
396 #define HTCR_SH0_NON_SHAREABLE		(U(0x0) << 12)
397 #define HTCR_SH0_OUTER_SHAREABLE	(U(0x2) << 12)
398 #define HTCR_SH0_INNER_SHAREABLE	(U(0x3) << 12)
399 
400 #define HTCR_RGN0_OUTER_NC	(U(0x0) << 10)
401 #define HTCR_RGN0_OUTER_WBA	(U(0x1) << 10)
402 #define HTCR_RGN0_OUTER_WT	(U(0x2) << 10)
403 #define HTCR_RGN0_OUTER_WBNA	(U(0x3) << 10)
404 
405 #define HTCR_RGN0_INNER_NC	(U(0x0) << 8)
406 #define HTCR_RGN0_INNER_WBA	(U(0x1) << 8)
407 #define HTCR_RGN0_INNER_WT	(U(0x2) << 8)
408 #define HTCR_RGN0_INNER_WBNA	(U(0x3) << 8)
409 
410 #define HTCR_T0SZ_SHIFT		U(0)
411 #define HTCR_T0SZ_MASK		U(0x7)
412 
413 #define MODE_RW_SHIFT		U(0x4)
414 #define MODE_RW_MASK		U(0x1)
415 #define MODE_RW_32		U(0x1)
416 
417 #define MODE32_SHIFT		U(0)
418 #define MODE32_MASK		U(0x1f)
419 #define MODE32_usr		U(0x10)
420 #define MODE32_fiq		U(0x11)
421 #define MODE32_irq		U(0x12)
422 #define MODE32_svc		U(0x13)
423 #define MODE32_mon		U(0x16)
424 #define MODE32_abt		U(0x17)
425 #define MODE32_hyp		U(0x1a)
426 #define MODE32_und		U(0x1b)
427 #define MODE32_sys		U(0x1f)
428 
429 #define GET_M32(mode)		(((mode) >> MODE32_SHIFT) & MODE32_MASK)
430 
431 #define SPSR_MODE32(mode, isa, endian, aif) \
432 ( \
433 	( \
434 		(MODE_RW_32 << MODE_RW_SHIFT) | \
435 		(((mode) & MODE32_MASK) << MODE32_SHIFT) | \
436 		(((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \
437 		(((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \
438 		(((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) \
439 	) & \
440 	(~(SPSR_SSBS_BIT)) \
441 )
442 
443 /*
444  * TTBR definitions
445  */
446 #define TTBR_CNP_BIT		ULL(0x1)
447 
448 /*
449  * CTR definitions
450  */
451 #define CTR_CWG_SHIFT		U(24)
452 #define CTR_CWG_MASK		U(0xf)
453 #define CTR_ERG_SHIFT		U(20)
454 #define CTR_ERG_MASK		U(0xf)
455 #define CTR_DMINLINE_SHIFT	U(16)
456 #define CTR_DMINLINE_WIDTH	U(4)
457 #define CTR_DMINLINE_MASK	((U(1) << 4) - U(1))
458 #define CTR_L1IP_SHIFT		U(14)
459 #define CTR_L1IP_MASK		U(0x3)
460 #define CTR_IMINLINE_SHIFT	U(0)
461 #define CTR_IMINLINE_MASK	U(0xf)
462 
463 #define MAX_CACHE_LINE_SIZE	U(0x800) /* 2KB */
464 
465 /* PMCR definitions */
466 #define PMCR_N_SHIFT		U(11)
467 #define PMCR_N_MASK		U(0x1f)
468 #define PMCR_N_BITS		(PMCR_N_MASK << PMCR_N_SHIFT)
469 #define PMCR_LP_BIT		(U(1) << 7)
470 #define PMCR_LC_BIT		(U(1) << 6)
471 #define PMCR_DP_BIT		(U(1) << 5)
472 #define PMCR_X_BIT		(U(1) << 4)
473 #define PMCR_C_BIT		(U(1) << 2)
474 #define PMCR_P_BIT		(U(1) << 1)
475 #define PMCR_E_BIT		(U(1) << 0)
476 #define	PMCR_RESET_VAL		U(0x0)
477 
478 /*******************************************************************************
479  * Definitions of register offsets, fields and macros for CPU system
480  * instructions.
481  ******************************************************************************/
482 
483 #define TLBI_ADDR_SHIFT		U(0)
484 #define TLBI_ADDR_MASK		U(0xFFFFF000)
485 #define TLBI_ADDR(x)		(((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
486 
487 /*******************************************************************************
488  * Definitions of register offsets and fields in the CNTCTLBase Frame of the
489  * system level implementation of the Generic Timer.
490  ******************************************************************************/
491 #define CNTCTLBASE_CNTFRQ	U(0x0)
492 #define CNTNSAR			U(0x4)
493 #define CNTNSAR_NS_SHIFT(x)	(x)
494 
495 #define CNTACR_BASE(x)		(U(0x40) + ((x) << 2))
496 #define CNTACR_RPCT_SHIFT	U(0x0)
497 #define CNTACR_RVCT_SHIFT	U(0x1)
498 #define CNTACR_RFRQ_SHIFT	U(0x2)
499 #define CNTACR_RVOFF_SHIFT	U(0x3)
500 #define CNTACR_RWVT_SHIFT	U(0x4)
501 #define CNTACR_RWPT_SHIFT	U(0x5)
502 
503 /*******************************************************************************
504  * Definitions of register offsets and fields in the CNTBaseN Frame of the
505  * system level implementation of the Generic Timer.
506  ******************************************************************************/
507 /* Physical Count register. */
508 #define CNTPCT_LO		U(0x0)
509 /* Counter Frequency register. */
510 #define CNTBASEN_CNTFRQ		U(0x10)
511 /* Physical Timer CompareValue register. */
512 #define CNTP_CVAL_LO		U(0x20)
513 /* Physical Timer Control register. */
514 #define CNTP_CTL		U(0x2c)
515 
516 /* Physical timer control register bit fields shifts and masks */
517 #define CNTP_CTL_ENABLE_SHIFT	0
518 #define CNTP_CTL_IMASK_SHIFT	1
519 #define CNTP_CTL_ISTATUS_SHIFT	2
520 
521 #define CNTP_CTL_ENABLE_MASK	U(1)
522 #define CNTP_CTL_IMASK_MASK	U(1)
523 #define CNTP_CTL_ISTATUS_MASK	U(1)
524 
525 /* MAIR macros */
526 #define MAIR0_ATTR_SET(attr, index)	((attr) << ((index) << U(3)))
527 #define MAIR1_ATTR_SET(attr, index)	((attr) << (((index) - U(3)) << U(3)))
528 
529 /* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */
530 #define SCR		p15, 0, c1, c1, 0
531 #define SCTLR		p15, 0, c1, c0, 0
532 #define ACTLR		p15, 0, c1, c0, 1
533 #define SDCR		p15, 0, c1, c3, 1
534 #define MPIDR		p15, 0, c0, c0, 5
535 #define MIDR		p15, 0, c0, c0, 0
536 #define HVBAR		p15, 4, c12, c0, 0
537 #define VBAR		p15, 0, c12, c0, 0
538 #define MVBAR		p15, 0, c12, c0, 1
539 #define NSACR		p15, 0, c1, c1, 2
540 #define CPACR		p15, 0, c1, c0, 2
541 #define DCCIMVAC	p15, 0, c7, c14, 1
542 #define DCCMVAC		p15, 0, c7, c10, 1
543 #define DCIMVAC		p15, 0, c7, c6, 1
544 #define DCCISW		p15, 0, c7, c14, 2
545 #define DCCSW		p15, 0, c7, c10, 2
546 #define DCISW		p15, 0, c7, c6, 2
547 #define CTR		p15, 0, c0, c0, 1
548 #define CNTFRQ		p15, 0, c14, c0, 0
549 #define ID_MMFR3	p15, 0, c0, c1, 7
550 #define ID_MMFR4	p15, 0, c0, c2, 6
551 #define ID_DFR0		p15, 0, c0, c1, 2
552 #define ID_DFR1		p15, 0, c0, c3, 5
553 #define ID_PFR0		p15, 0, c0, c1, 0
554 #define ID_PFR1		p15, 0, c0, c1, 1
555 #define MAIR0		p15, 0, c10, c2, 0
556 #define MAIR1		p15, 0, c10, c2, 1
557 #define TTBCR		p15, 0, c2, c0, 2
558 #define TTBR0		p15, 0, c2, c0, 0
559 #define TTBR1		p15, 0, c2, c0, 1
560 #define TLBIALL		p15, 0, c8, c7, 0
561 #define TLBIALLH	p15, 4, c8, c7, 0
562 #define TLBIALLIS	p15, 0, c8, c3, 0
563 #define TLBIMVA		p15, 0, c8, c7, 1
564 #define TLBIMVAA	p15, 0, c8, c7, 3
565 #define TLBIMVAAIS	p15, 0, c8, c3, 3
566 #define TLBIMVAHIS	p15, 4, c8, c3, 1
567 #define BPIALLIS	p15, 0, c7, c1, 6
568 #define BPIALL		p15, 0, c7, c5, 6
569 #define ICIALLU		p15, 0, c7, c5, 0
570 #define HSCTLR		p15, 4, c1, c0, 0
571 #define HCR		p15, 4, c1, c1, 0
572 #define HCPTR		p15, 4, c1, c1, 2
573 #define HSTR		p15, 4, c1, c1, 3
574 #define CNTHCTL		p15, 4, c14, c1, 0
575 #define CNTKCTL		p15, 0, c14, c1, 0
576 #define VPIDR		p15, 4, c0, c0, 0
577 #define VMPIDR		p15, 4, c0, c0, 5
578 #define ISR		p15, 0, c12, c1, 0
579 #define CLIDR		p15, 1, c0, c0, 1
580 #define CSSELR		p15, 2, c0, c0, 0
581 #define CCSIDR		p15, 1, c0, c0, 0
582 #define CCSIDR2		p15, 1, c0, c0, 2
583 #define HTCR		p15, 4, c2, c0, 2
584 #define HMAIR0		p15, 4, c10, c2, 0
585 #define ATS1CPR		p15, 0, c7, c8, 0
586 #define ATS1HR		p15, 4, c7, c8, 0
587 #define DBGOSDLR	p14, 0, c1, c3, 4
588 
589 /* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
590 #define HDCR		p15, 4, c1, c1, 1
591 #define PMCR		p15, 0, c9, c12, 0
592 #define CNTHP_TVAL	p15, 4, c14, c2, 0
593 #define CNTHP_CTL	p15, 4, c14, c2, 1
594 
595 /* AArch32 coproc registers for 32bit MMU descriptor support */
596 #define PRRR		p15, 0, c10, c2, 0
597 #define NMRR		p15, 0, c10, c2, 1
598 #define DACR		p15, 0, c3, c0, 0
599 
600 /* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
601 #define ICC_IAR1	p15, 0, c12, c12, 0
602 #define ICC_IAR0	p15, 0, c12, c8, 0
603 #define ICC_EOIR1	p15, 0, c12, c12, 1
604 #define ICC_EOIR0	p15, 0, c12, c8, 1
605 #define ICC_HPPIR1	p15, 0, c12, c12, 2
606 #define ICC_HPPIR0	p15, 0, c12, c8, 2
607 #define ICC_BPR1	p15, 0, c12, c12, 3
608 #define ICC_BPR0	p15, 0, c12, c8, 3
609 #define ICC_DIR		p15, 0, c12, c11, 1
610 #define ICC_PMR		p15, 0, c4, c6, 0
611 #define ICC_RPR		p15, 0, c12, c11, 3
612 #define ICC_CTLR	p15, 0, c12, c12, 4
613 #define ICC_MCTLR	p15, 6, c12, c12, 4
614 #define ICC_SRE		p15, 0, c12, c12, 5
615 #define ICC_HSRE	p15, 4, c12, c9, 5
616 #define ICC_MSRE	p15, 6, c12, c12, 5
617 #define ICC_IGRPEN0	p15, 0, c12, c12, 6
618 #define ICC_IGRPEN1	p15, 0, c12, c12, 7
619 #define ICC_MGRPEN1	p15, 6, c12, c12, 7
620 
621 /* 64 bit system register defines The format is: coproc, opt1, CRm */
622 #define TTBR0_64	p15, 0, c2
623 #define TTBR1_64	p15, 1, c2
624 #define CNTVOFF_64	p15, 4, c14
625 #define VTTBR_64	p15, 6, c2
626 #define CNTPCT_64	p15, 0, c14
627 #define HTTBR_64	p15, 4, c2
628 #define CNTHP_CVAL_64	p15, 6, c14
629 #define PAR_64		p15, 0, c7
630 
631 /* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */
632 #define ICC_SGI1R_EL1_64	p15, 0, c12
633 #define ICC_ASGI1R_EL1_64	p15, 1, c12
634 #define ICC_SGI0R_EL1_64	p15, 2, c12
635 
636 /* Fault registers. The format is: coproc, opt1, CRn, CRm, opt2 */
637 #define DFSR		p15, 0, c5, c0, 0
638 #define IFSR		p15, 0, c5, c0, 1
639 #define DFAR		p15, 0, c6, c0, 0
640 #define IFAR		p15, 0, c6, c0, 2
641 
642 /*******************************************************************************
643  * Definitions of MAIR encodings for device and normal memory
644  ******************************************************************************/
645 /*
646  * MAIR encodings for device memory attributes.
647  */
648 #define MAIR_DEV_nGnRnE		U(0x0)
649 #define MAIR_DEV_nGnRE		U(0x4)
650 #define MAIR_DEV_nGRE		U(0x8)
651 #define MAIR_DEV_GRE		U(0xc)
652 
653 /*
654  * MAIR encodings for normal memory attributes.
655  *
656  * Cache Policy
657  *  WT:	 Write Through
658  *  WB:	 Write Back
659  *  NC:	 Non-Cacheable
660  *
661  * Transient Hint
662  *  NTR: Non-Transient
663  *  TR:	 Transient
664  *
665  * Allocation Policy
666  *  RA:	 Read Allocate
667  *  WA:	 Write Allocate
668  *  RWA: Read and Write Allocate
669  *  NA:	 No Allocation
670  */
671 #define MAIR_NORM_WT_TR_WA	U(0x1)
672 #define MAIR_NORM_WT_TR_RA	U(0x2)
673 #define MAIR_NORM_WT_TR_RWA	U(0x3)
674 #define MAIR_NORM_NC		U(0x4)
675 #define MAIR_NORM_WB_TR_WA	U(0x5)
676 #define MAIR_NORM_WB_TR_RA	U(0x6)
677 #define MAIR_NORM_WB_TR_RWA	U(0x7)
678 #define MAIR_NORM_WT_NTR_NA	U(0x8)
679 #define MAIR_NORM_WT_NTR_WA	U(0x9)
680 #define MAIR_NORM_WT_NTR_RA	U(0xa)
681 #define MAIR_NORM_WT_NTR_RWA	U(0xb)
682 #define MAIR_NORM_WB_NTR_NA	U(0xc)
683 #define MAIR_NORM_WB_NTR_WA	U(0xd)
684 #define MAIR_NORM_WB_NTR_RA	U(0xe)
685 #define MAIR_NORM_WB_NTR_RWA	U(0xf)
686 
687 #define MAIR_NORM_OUTER_SHIFT	U(4)
688 
689 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer)	\
690 		((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
691 
692 /* PAR fields */
693 #define PAR_F_SHIFT	U(0)
694 #define PAR_F_MASK	ULL(0x1)
695 #define PAR_ADDR_SHIFT	U(12)
696 #define PAR_ADDR_MASK	(BIT_64(40) - ULL(1)) /* 40-bits-wide page address */
697 
698 /*******************************************************************************
699  * Definitions for system register interface to AMU for FEAT_AMUv1
700  ******************************************************************************/
701 #define AMCR		p15, 0, c13, c2, 0
702 #define AMCFGR		p15, 0, c13, c2, 1
703 #define AMCGCR		p15, 0, c13, c2, 2
704 #define AMUSERENR	p15, 0, c13, c2, 3
705 #define AMCNTENCLR0	p15, 0, c13, c2, 4
706 #define AMCNTENSET0	p15, 0, c13, c2, 5
707 #define AMCNTENCLR1	p15, 0, c13, c3, 0
708 #define AMCNTENSET1	p15, 0, c13, c3, 1
709 
710 /* Activity Monitor Group 0 Event Counter Registers */
711 #define AMEVCNTR00	p15, 0, c0
712 #define AMEVCNTR01	p15, 1, c0
713 #define AMEVCNTR02	p15, 2, c0
714 #define AMEVCNTR03	p15, 3, c0
715 
716 /* Activity Monitor Group 0 Event Type Registers */
717 #define AMEVTYPER00	p15, 0, c13, c6, 0
718 #define AMEVTYPER01	p15, 0, c13, c6, 1
719 #define AMEVTYPER02	p15, 0, c13, c6, 2
720 #define AMEVTYPER03	p15, 0, c13, c6, 3
721 
722 /* Activity Monitor Group 1 Event Counter Registers */
723 #define AMEVCNTR10	p15, 0, c4
724 #define AMEVCNTR11	p15, 1, c4
725 #define AMEVCNTR12	p15, 2, c4
726 #define AMEVCNTR13	p15, 3, c4
727 #define AMEVCNTR14	p15, 4, c4
728 #define AMEVCNTR15	p15, 5, c4
729 #define AMEVCNTR16	p15, 6, c4
730 #define AMEVCNTR17	p15, 7, c4
731 #define AMEVCNTR18	p15, 0, c5
732 #define AMEVCNTR19	p15, 1, c5
733 #define AMEVCNTR1A	p15, 2, c5
734 #define AMEVCNTR1B	p15, 3, c5
735 #define AMEVCNTR1C	p15, 4, c5
736 #define AMEVCNTR1D	p15, 5, c5
737 #define AMEVCNTR1E	p15, 6, c5
738 #define AMEVCNTR1F	p15, 7, c5
739 
740 /* Activity Monitor Group 1 Event Type Registers */
741 #define AMEVTYPER10	p15, 0, c13, c14, 0
742 #define AMEVTYPER11	p15, 0, c13, c14, 1
743 #define AMEVTYPER12	p15, 0, c13, c14, 2
744 #define AMEVTYPER13	p15, 0, c13, c14, 3
745 #define AMEVTYPER14	p15, 0, c13, c14, 4
746 #define AMEVTYPER15	p15, 0, c13, c14, 5
747 #define AMEVTYPER16	p15, 0, c13, c14, 6
748 #define AMEVTYPER17	p15, 0, c13, c14, 7
749 #define AMEVTYPER18	p15, 0, c13, c15, 0
750 #define AMEVTYPER19	p15, 0, c13, c15, 1
751 #define AMEVTYPER1A	p15, 0, c13, c15, 2
752 #define AMEVTYPER1B	p15, 0, c13, c15, 3
753 #define AMEVTYPER1C	p15, 0, c13, c15, 4
754 #define AMEVTYPER1D	p15, 0, c13, c15, 5
755 #define AMEVTYPER1E	p15, 0, c13, c15, 6
756 #define AMEVTYPER1F	p15, 0, c13, c15, 7
757 
758 /* AMCNTENSET0 definitions */
759 #define AMCNTENSET0_Pn_SHIFT	U(0)
760 #define AMCNTENSET0_Pn_MASK	U(0xffff)
761 
762 /* AMCNTENSET1 definitions */
763 #define AMCNTENSET1_Pn_SHIFT	U(0)
764 #define AMCNTENSET1_Pn_MASK	U(0xffff)
765 
766 /* AMCNTENCLR0 definitions */
767 #define AMCNTENCLR0_Pn_SHIFT	U(0)
768 #define AMCNTENCLR0_Pn_MASK	U(0xffff)
769 
770 /* AMCNTENCLR1 definitions */
771 #define AMCNTENCLR1_Pn_SHIFT	U(0)
772 #define AMCNTENCLR1_Pn_MASK	U(0xffff)
773 
774 /* AMCR definitions */
775 #define AMCR_CG1RZ_SHIFT	U(17)
776 #define AMCR_CG1RZ_BIT		(ULL(1) << AMCR_CG1RZ_SHIFT)
777 
778 /* AMCFGR definitions */
779 #define AMCFGR_NCG_SHIFT	U(28)
780 #define AMCFGR_NCG_MASK		U(0xf)
781 #define AMCFGR_N_SHIFT		U(0)
782 #define AMCFGR_N_MASK		U(0xff)
783 
784 /* AMCGCR definitions */
785 #define AMCGCR_CG0NC_SHIFT	U(0)
786 #define AMCGCR_CG0NC_MASK	U(0xff)
787 #define AMCGCR_CG1NC_SHIFT	U(8)
788 #define AMCGCR_CG1NC_MASK	U(0xff)
789 
790 /*******************************************************************************
791  * Definitions for DynamicIQ Shared Unit registers
792  ******************************************************************************/
793 #define CLUSTERPWRDN	p15, 0, c15, c3, 6
794 
795 /* CLUSTERPWRDN register definitions */
796 #define DSU_CLUSTER_PWR_OFF	0
797 #define DSU_CLUSTER_PWR_ON	1
798 #define DSU_CLUSTER_PWR_MASK	U(1)
799 #define DSU_CLUSTER_MEM_RET	BIT(1)
800 
801 #endif /* ARCH_H */
802