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Searched refs:GICD_CTLR_RWP_BIT (Results 1 – 3 of 3) sorted by relevance

/trusted-firmware-a-3.7.0/drivers/arm/gic/v3/
Dgic600_multichip.c72 CTLR_ENABLE_G1NS_BIT | GICD_CTLR_RWP_BIT)) != 0) { in set_gicd_dchipr_rt_owner()
108 CTLR_ENABLE_G1NS_BIT | GICD_CTLR_RWP_BIT)) != 0) { in set_gicd_chipr_n()
346 CTLR_ENABLE_G1NS_BIT | GICD_CTLR_RWP_BIT)) != 0) { in gic600_multichip_init()
Dgicv3_private.h266 while ((gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) != 0U) { in gicd_wait_for_pending_write()
/trusted-firmware-a-3.7.0/include/drivers/arm/
Dgicv3.h138 #define GICD_CTLR_RWP_BIT BIT_32(GICD_CTLR_RWP_SHIFT) macro