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Searched refs:DRVCTRL1_QSPI1_MISO_IO1 (Results 1 – 8 of 8) sorted by relevance

/trusted-firmware-a-3.7.0/drivers/renesas/rcar/pfc/M3N/
Dpfc_init_m3n.c244 #define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U) macro
925 reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3) in pfc_init_m3n()
/trusted-firmware-a-3.7.0/drivers/renesas/rzg/pfc/G2H/
Dpfc_init_g2h.c244 #define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U) macro
972 DRVCTRL1_QSPI1_MISO_IO1(3) | in pfc_init_g2h()
/trusted-firmware-a-3.7.0/drivers/renesas/rzg/pfc/G2N/
Dpfc_init_g2n.c244 #define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U) macro
968 DRVCTRL1_QSPI1_MISO_IO1(3) | in pfc_init_g2n()
/trusted-firmware-a-3.7.0/drivers/renesas/rcar/pfc/H3/
Dpfc_init_h3_v1.c240 #define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U) macro
890 reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3) in pfc_init_h3_v1()
Dpfc_init_h3_v2.c242 #define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U) macro
923 reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3) in pfc_init_h3_v2()
/trusted-firmware-a-3.7.0/drivers/renesas/rzg/pfc/G2M/
Dpfc_init_g2m.c245 #define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U) macro
1007 reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3) in pfc_init_g2m()
/trusted-firmware-a-3.7.0/drivers/renesas/rcar/pfc/M3/
Dpfc_init_m3.c245 #define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U) macro
1018 reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3) in pfc_init_m3()
/trusted-firmware-a-3.7.0/drivers/renesas/rcar/pfc/D3/
Dpfc_init_d3.c245 #define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U) macro