| /trusted-firmware-a-3.6.0-3.5.0/plat/intel/soc/stratix10/include/ |
| D | s10_memory_controller.h | 22 #define S10_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(value) \ argument
23 (((value) & 0x00000060) >> 5)
72 #define ACT_TO_ACT_DIFF_BANK(value) (((value) & 0x00fc0000) >> 18) argument
73 #define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12) argument
74 #define ACT_TO_RDWR(value) (((value) & 0x0000003f) >> 0) argument
75 #define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12) argument
78 #define RD_TO_RD_DIFF_CHIP(value) (((value) & 0x00000fc0) >> 6) argument
79 #define RD_TO_WR_DIFF_CHIP(value) (((value) & 0x3f000000) >> 24) argument
80 #define RD_TO_WR(value) (((value) & 0x00fc0000) >> 18) argument
81 #define RD_TO_PCH(value) (((value) & 0x00000fc0) >> 6) argument
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| /trusted-firmware-a-3.6.0-3.5.0/plat/intel/soc/agilex/include/ |
| D | agilex_memory_controller.h | 24 #define AGX_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(value) \ argument
25 (((value) & 0x00000060) >> 5)
73 #define ACT_TO_ACT_DIFF_BANK(value) (((value) & 0x00fc0000) >> 18) argument
74 #define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12) argument
75 #define ACT_TO_RDWR(value) (((value) & 0x0000003f) >> 0) argument
76 #define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12) argument
79 #define RD_TO_RD_DIFF_CHIP(value) (((value) & 0x00000fc0) >> 6) argument
80 #define RD_TO_WR_DIFF_CHIP(value) (((value) & 0x3f000000) >> 24) argument
81 #define RD_TO_WR(value) (((value) & 0x00fc0000) >> 18) argument
82 #define RD_TO_PCH(value) (((value) & 0x00000fc0) >> 6) argument
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| /trusted-firmware-a-3.6.0-3.5.0/plat/xilinx/zynqmp/pm_service/ |
| D | pm_api_ioctl.c | 96 uint32_t value) in pm_ioctl_config_boot_addr() argument
110 if (value == PM_RPU_BOOTMEM_LOVEC) { in pm_ioctl_config_boot_addr()
112 } else if (value == PM_RPU_BOOTMEM_HIVEC) { in pm_ioctl_config_boot_addr()
132 static enum pm_ret_status pm_ioctl_config_tcm_comb(uint32_t value) in pm_ioctl_config_tcm_comb() argument
138 if (value == PM_RPU_TCM_SPLIT) { in pm_ioctl_config_tcm_comb()
140 } else if (value == PM_RPU_TCM_COMB) { in pm_ioctl_config_tcm_comb()
161 uint32_t value) in pm_ioctl_set_tapdelay_bypass() argument
163 if ((value != PM_TAPDELAY_BYPASS_ENABLE && in pm_ioctl_set_tapdelay_bypass()
164 value != PM_TAPDELAY_BYPASS_DISABLE) || type >= PM_TAPDELAY_MAX) { in pm_ioctl_set_tapdelay_bypass()
168 return pm_mmio_write(IOU_TAPDLY_BYPASS, TAP_DELAY_MASK, value << type); in pm_ioctl_set_tapdelay_bypass()
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| D | zynqmp_pm_svc_main.c | 142 uint32_t value; in zynqmp_sgi7_irq() local
160 pm_mmio_read(PMU_GLOBAL_GEN_STORAGE4, &value); in zynqmp_sgi7_irq()
161 value = (value & RESTART_SCOPE_MASK) >> RESTART_SCOPE_SHIFT; in zynqmp_sgi7_irq()
162 pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET, value); in zynqmp_sgi7_irq()
356 uint32_t value = 0U; in pm_smc_handler() local
358 ret = pm_fpga_get_status(&value); in pm_smc_handler()
359 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); in pm_smc_handler()
378 uint32_t value = 0U; in pm_smc_handler() local
381 pm_arg[3], &value); in pm_smc_handler()
382 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); in pm_smc_handler()
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| D | zynqmp_pm_api_sys.h | 118 uint32_t value);
119 enum pm_ret_status pm_mmio_read(uintptr_t address, uint32_t *value);
124 enum pm_ret_status pm_fpga_get_status(uint32_t *value);
126 enum pm_ret_status pm_get_chipid(uint32_t *value);
137 uint32_t *value);
168 uint32_t *value);
173 uint32_t *value);
176 uint32_t *value);
180 uint32_t value,
184 uint32_t value);
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| /trusted-firmware-a-3.6.0-3.5.0/plat/mediatek/drivers/ptp3/ |
| D | ptp3_common.c | 17 unsigned int i, addr, value; in ptp3_init() local
30 value = ptp3_cfg2[i][PTP3_CFG_VALUE]; in ptp3_init()
32 mmio_write_32(addr, value); in ptp3_init()
39 value = ptp3_cfg2[i][PTP3_CFG_VALUE] + 0x5E0; in ptp3_init()
41 value = ptp3_cfg2[i][PTP3_CFG_VALUE]; in ptp3_init()
43 mmio_write_32(addr, value); in ptp3_init()
49 value = ptp3_cfg3[PTP3_CFG_VALUE]; in ptp3_init()
52 value = ptp3_cfg3_ext[PTP3_CFG_VALUE]; in ptp3_init()
54 mmio_write_32(addr, value & PTP3_CFG3_MASK1); in ptp3_init()
55 mmio_write_32(addr, value & PTP3_CFG3_MASK2); in ptp3_init()
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| /trusted-firmware-a-3.6.0-3.5.0/lib/extensions/amu/aarch64/ |
| D | amu.c | 66 static inline __unused void write_cptr_el2_tam(uint64_t value) in write_cptr_el2_tam() argument
69 ((value << CPTR_EL2_TAM_SHIFT) & CPTR_EL2_TAM_BIT)); in write_cptr_el2_tam()
74 uint64_t value = read_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3); in ctx_write_cptr_el3_tam() local
76 value &= ~TAM_BIT; in ctx_write_cptr_el3_tam()
77 value |= (tam << TAM_SHIFT) & TAM_BIT; in ctx_write_cptr_el3_tam()
79 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, value); in ctx_write_cptr_el3_tam()
84 uint64_t value = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); in ctx_write_scr_el3_amvoffen() local
86 value &= ~SCR_AMVOFFEN_BIT; in ctx_write_scr_el3_amvoffen()
87 value |= (amvoffen << SCR_AMVOFFEN_SHIFT) & SCR_AMVOFFEN_BIT; in ctx_write_scr_el3_amvoffen()
89 write_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3, value); in ctx_write_scr_el3_amvoffen()
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| /trusted-firmware-a-3.6.0-3.5.0/plat/brcm/board/stingray/include/ |
| D | scp_utils.h | 22 #define SCP_WRITE_CFG(cfg, value) mmio_write_32(CRMU_CFG_BASE + \ argument
23 offsetof(M0CFG, cfg), value)
27 #define SCP_WRITE_CFG16(cfg, value) mmio_write_16(CRMU_CFG_BASE + \ argument
28 offsetof(M0CFG, cfg), value)
32 #define SCP_WRITE_CFG8(cfg, value) mmio_write_8(CRMU_CFG_BASE + \ argument
33 offsetof(M0CFG, cfg), value)
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| /trusted-firmware-a-3.6.0-3.5.0/lib/extensions/amu/aarch32/ |
| D | amu.c | 43 static inline __unused void write_hcptr_tam(uint32_t value) in write_hcptr_tam() argument
46 ((value << TAM_SHIFT) & TAM_BIT)); in write_hcptr_tam()
49 static inline __unused void write_amcr_cg1rz(uint32_t value) in write_amcr_cg1rz() argument
52 ((value << AMCR_CG1RZ_SHIFT) & AMCR_CG1RZ_BIT)); in write_amcr_cg1rz()
87 uint32_t value = read_amcntenset0(); in write_amcntenset0_px() local
89 value &= ~AMCNTENSET0_Pn_MASK; in write_amcntenset0_px()
90 value |= (px << AMCNTENSET0_Pn_SHIFT) & in write_amcntenset0_px()
93 write_amcntenset0(value); in write_amcntenset0_px()
98 uint32_t value = read_amcntenset1(); in write_amcntenset1_px() local
100 value &= ~AMCNTENSET1_Pn_MASK; in write_amcntenset1_px()
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| /trusted-firmware-a-3.6.0-3.5.0/include/lib/ |
| D | mmio.h | 12 static inline void mmio_write_8(uintptr_t addr, uint8_t value) in mmio_write_8() argument
14 *(volatile uint8_t*)addr = value; in mmio_write_8()
22 static inline void mmio_write_16(uintptr_t addr, uint16_t value) in mmio_write_16() argument
24 *(volatile uint16_t*)addr = value; in mmio_write_16()
39 static inline void mmio_write_32(uintptr_t addr, uint32_t value) in mmio_write_32() argument
41 *(volatile uint32_t*)addr = value; in mmio_write_32()
49 static inline void mmio_write_64(uintptr_t addr, uint64_t value) in mmio_write_64() argument
51 *(volatile uint64_t*)addr = value; in mmio_write_64()
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| D | utils_def.h | 98 #define round_boundary(value, boundary) \ argument
99 ((__typeof__(value))((boundary) - 1))
101 #define round_up(value, boundary) \ argument
102 ((((value) - 1) | round_boundary(value, boundary)) + 1)
104 #define round_down(value, boundary) \ argument
105 ((value) & ~round_boundary(value, boundary))
110 #define is_aligned(value, boundary) \ argument
111 (round_up((uintptr_t) value, boundary) == \
112 round_down((uintptr_t) value, boundary))
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| /trusted-firmware-a-3.6.0-3.5.0/drivers/arm/sp805/ |
| D | sp805.c | 14 static inline void sp805_write_wdog_load(uintptr_t base, uint32_t value) in sp805_write_wdog_load() argument
16 mmio_write_32(base + SP805_WDOG_LOAD_OFF, value); in sp805_write_wdog_load()
19 static inline void sp805_write_wdog_ctrl(uintptr_t base, uint32_t value) in sp805_write_wdog_ctrl() argument
21 mmio_write_32(base + SP805_WDOG_CTR_OFF, value); in sp805_write_wdog_ctrl()
24 static inline void sp805_write_wdog_lock(uintptr_t base, uint32_t value) in sp805_write_wdog_lock() argument
26 mmio_write_32(base + SP805_WDOG_LOCK_OFF, value); in sp805_write_wdog_lock()
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| /trusted-firmware-a-3.6.0-3.5.0/plat/hisilicon/hikey/ |
| D | hikey_ddr.c | 1224 uint32_t value; in lpddrx_save_ddl_para_bypass() local
1229 value = mmio_read_32(0xf712c000 + 0x22c + i * 0x80); in lpddrx_save_ddl_para_bypass()
1230 ddr_ddl_para[cnt++] = value; in lpddrx_save_ddl_para_bypass()
1231 value = mmio_read_32(0xf712c000 + 0x23c + i * 0x80); in lpddrx_save_ddl_para_bypass()
1232 ddr_ddl_para[cnt++] = value; in lpddrx_save_ddl_para_bypass()
1233 value = mmio_read_32(0xf712c000 + 0x240 + i * 0x80); in lpddrx_save_ddl_para_bypass()
1234 ddr_ddl_para[cnt++] = value; in lpddrx_save_ddl_para_bypass()
1235 value = mmio_read_32(0xf712c000 + 0x640 + i * 0x80); in lpddrx_save_ddl_para_bypass()
1236 ddr_ddl_para[cnt++] = value; in lpddrx_save_ddl_para_bypass()
1242 uint32_t value; in lpddrx_save_ddl_para_mission() local
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/lib/compiler-rt/builtins/ |
| D | int_lib.h | 122 int __inline __builtin_ctz(uint32_t value) { in __builtin_ctz() argument
124 if (_BitScanForward(&trailing_zero, value)) in __builtin_ctz()
129 int __inline __builtin_clz(uint32_t value) { in __builtin_clz() argument
131 if (_BitScanReverse(&leading_zero, value)) in __builtin_clz()
137 int __inline __builtin_clzll(uint64_t value) { in __builtin_clzll() argument
139 if (_BitScanReverse64(&leading_zero, value)) in __builtin_clzll()
144 int __inline __builtin_clzll(uint64_t value) { in __builtin_clzll() argument
145 if (value == 0) in __builtin_clzll()
147 uint32_t msh = (uint32_t)(value >> 32); in __builtin_clzll()
148 uint32_t lsh = (uint32_t)(value & 0xFFFFFFFF); in __builtin_clzll()
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| /trusted-firmware-a-3.6.0-3.5.0/docs/components/ |
| D | ffa-manifest-binding.rst | 11 - value type: <string>
21 - value type: <u32>
31 - value type: <prop-encoded-array>
36 - value type: <u32>
40 - value type: <u32>
44 - value type: <string>
48 - value type: <u32>
53 - If value of this field = 1 and number of PEs > 1 then the partition is
55 - If the value of this field > 1 then the partition is treated as a MP
59 - value type: <u32>
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| /trusted-firmware-a-3.6.0-3.5.0/drivers/arm/sbsa/ |
| D | sbsa.c | 13 void sbsa_watchdog_offset_reg_write(uintptr_t base, uint64_t value) in sbsa_watchdog_offset_reg_write() argument
15 assert((value >> SBSA_WDOG_WOR_WIDTH) == 0); in sbsa_watchdog_offset_reg_write()
17 ((uint32_t)value & UINT32_MAX)); in sbsa_watchdog_offset_reg_write()
18 mmio_write_32(base + SBSA_WDOG_WOR_HIGH_OFFSET, (uint32_t)(value >> 32)); in sbsa_watchdog_offset_reg_write()
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| /trusted-firmware-a-3.6.0-3.5.0/lib/mpmm/ |
| D | mpmm.c | 27 uint64_t value = read_cpumpmmcr_el3(); in write_cpumpmmcr_el3_mpmm_en() local
29 value &= ~(CPUMPMMCR_EL3_MPMM_EN_MASK << CPUMPMMCR_EL3_MPMM_EN_SHIFT); in write_cpumpmmcr_el3_mpmm_en()
30 value |= (mpmm_en & CPUMPMMCR_EL3_MPMM_EN_MASK) << in write_cpumpmmcr_el3_mpmm_en()
33 write_cpumpmmcr_el3(value); in write_cpumpmmcr_el3_mpmm_en()
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| /trusted-firmware-a-3.6.0-3.5.0/drivers/st/bsec/ |
| D | bsec2.c | 246 uint32_t value; in bsec_set_config() local
253 value = ((((uint32_t)cfg->freq << BSEC_CONF_FRQ_SHIFT) & in bsec_set_config()
262 mmio_write_32(bsec_base + BSEC_OTP_CONF_OFF, value); in bsec_set_config()
272 value = ((((uint32_t)cfg->upper_otp_lock << UPPER_OTP_LOCK_SHIFT) & in bsec_set_config()
281 mmio_write_32(bsec_base + BSEC_OTP_LOCK_OFF, value); in bsec_set_config()
295 uint32_t value; in bsec_get_config() local
301 value = mmio_read_32(bsec_base + BSEC_OTP_CONF_OFF); in bsec_get_config()
302 cfg->power = (uint8_t)((value & BSEC_CONF_POWER_UP_MASK) >> in bsec_get_config()
304 cfg->freq = (uint8_t)((value & BSEC_CONF_FRQ_MASK) >> in bsec_get_config()
306 cfg->pulse_width = (uint8_t)((value & BSEC_CONF_PRG_WIDTH_MASK) >> in bsec_get_config()
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| /trusted-firmware-a-3.6.0-3.5.0/common/ |
| D | fdt_wrappers.c | 27 unsigned int cells, uint32_t *value) in fdt_read_uint32_array() argument
34 assert(value != NULL); in fdt_read_uint32_array()
51 value[i] = fdt32_to_cpu(prop[i]); in fdt_read_uint32_array()
58 uint32_t *value) in fdt_read_uint32() argument
60 return fdt_read_uint32_array(dtb, node, prop_name, 1, value); in fdt_read_uint32()
77 uint64_t *value) in fdt_read_uint64() argument
87 *value = ((uint64_t)array[0] << 32) | array[1]; in fdt_read_uint64()
97 unsigned int length, void *value) in fdtw_read_bytes() argument
104 assert(value != NULL); in fdtw_read_bytes()
121 (void)memcpy(value, ptr, length); in fdtw_read_bytes()
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| /trusted-firmware-a-3.6.0-3.5.0/include/common/ |
| D | fdt_wrappers.h | 19 uint32_t *value);
23 uint64_t *value);
25 unsigned int cells, uint32_t *value);
31 unsigned int cells, void *value);
33 unsigned int length, void *value);
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| /trusted-firmware-a-3.6.0-3.5.0/plat/xilinx/common/pm_service/ |
| D | pm_ipi.c | 162 uint32_t *value, size_t count) in pm_ipi_buff_read() argument
167 uint32_t *payload_ptr = value; in pm_ipi_buff_read()
183 *value = mmio_read_32(buffer_base + (i * PAYLOAD_ARG_SIZE)); in pm_ipi_buff_read()
184 value++; in pm_ipi_buff_read()
219 enum pm_ret_status pm_ipi_buff_read_callb(uint32_t *value, size_t count) in pm_ipi_buff_read_callb() argument
223 uint32_t *payload_ptr = value; in pm_ipi_buff_read_callb()
237 *value = mmio_read_32(buffer_base + (i * PAYLOAD_ARG_SIZE)); in pm_ipi_buff_read_callb()
238 value++; in pm_ipi_buff_read_callb()
274 uint32_t *value, size_t count) in pm_ipi_send_sync() argument
285 ret = ERROR_CODE_MASK & (pm_ipi_buff_read(proc, value, count)); in pm_ipi_send_sync()
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| /trusted-firmware-a-3.6.0-3.5.0/drivers/renesas/common/emmc/ |
| D | emmc_utility.c | 81 uint32_t value; in emmc_bit_field() local
87 value = data[index_top]; in emmc_bit_field()
89 value = in emmc_bit_field()
92 value = in emmc_bit_field()
97 value = in emmc_bit_field()
104 value = ((value >> (bottom & 0x07)) & ((1 << (top - bottom + 1)) - 1)); in emmc_bit_field()
106 return value; in emmc_bit_field()
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| /trusted-firmware-a-3.6.0-3.5.0/drivers/renesas/rcar/qos/ |
| D | qos_common.h | 111 static inline void io_write_32(uintptr_t addr, uint32_t value) in io_write_32() argument
113 *(volatile uint32_t *)addr = value; in io_write_32()
121 static inline void io_write_64(uintptr_t addr, uint64_t value) in io_write_64() argument
123 *(volatile uint64_t *)addr = value; in io_write_64()
128 uint64_t value; member
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| /trusted-firmware-a-3.6.0-3.5.0/plat/hisilicon/hikey960/ |
| D | hikey960_boardid.c | 63 static int get_adc(unsigned int channel, unsigned int *value) in get_adc() argument
93 *value = data; in get_adc()
97 static int get_value(unsigned int channel, unsigned int *value) in get_value() argument
101 ret = get_adc(channel, value); in get_value()
106 ret = ((*value & HKADC_VALID_VALUE) * HKADC_VREF_1V8) / HKADC_ACCURACY; in get_value()
107 *value = ret; in get_value()
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| /trusted-firmware-a-3.6.0-3.5.0/drivers/renesas/common/ |
| D | common.c | 18 uint32_t value = regval; in cpg_write() local
20 mmio_write_32(CPG_CPGWPR, ~value); in cpg_write()
21 mmio_write_32(regadr, value); in cpg_write()
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