| /trusted-firmware-a-3.6.0-3.5.0/drivers/mmc/ |
| D | mmc.c | 58 int ret; in mmc_send_cmd() local
66 ret = ops->send_cmd(&cmd); in mmc_send_cmd()
68 if ((ret == 0) && (r_data != NULL)) { in mmc_send_cmd()
76 if (ret != 0) { in mmc_send_cmd()
77 VERBOSE("Send command %u error: %d\n", idx, ret); in mmc_send_cmd()
80 return ret; in mmc_send_cmd()
89 int ret; in mmc_device_state() local
97 ret = mmc_send_cmd(MMC_CMD(13), rca << RCA_SHIFT_OFFSET, in mmc_device_state()
99 if (ret != 0) { in mmc_device_state()
116 int ret; in mmc_send_part_switch_cmd() local
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/plat/ti/k3/common/drivers/ti_sci/ |
| D | ti_sci.c | 103 int ret; in ti_sci_get_response() local
107 ret = k3_sec_proxy_recv(chan, msg); in ti_sci_get_response()
108 if (ret) { in ti_sci_get_response()
109 ERROR("Message receive failed (%d)\n", ret); in ti_sci_get_response()
110 return ret; in ti_sci_get_response()
150 int ret; in ti_sci_do_xfer() local
155 ret = k3_sec_proxy_clear_rx_thread(SP_RESPONSE); in ti_sci_do_xfer()
156 if (ret) { in ti_sci_do_xfer()
157 ERROR("Could not clear response queue (%d)\n", ret); in ti_sci_do_xfer()
158 return ret; in ti_sci_do_xfer()
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/drivers/mtd/nor/ |
| D | spi_nor.c | 87 int ret; in spi_nor_ready() local
89 ret = spi_nor_read_sr(&sr); in spi_nor_ready()
90 if (ret != 0) { in spi_nor_ready()
91 return ret; in spi_nor_ready()
97 ret = spi_nor_read_fsr(&fsr); in spi_nor_ready()
98 if (ret != 0) { in spi_nor_ready()
99 return ret; in spi_nor_ready()
111 int ret; in spi_nor_wait_ready() local
115 ret = spi_nor_ready(); in spi_nor_wait_ready()
116 if (ret <= 0) { in spi_nor_wait_ready()
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/plat/st/common/ |
| D | stm32cubeprogrammer_uart.c | 103 int ret; in uart_read_8() local
107 ret = stm32_uart_getc(&handle.uart); in uart_read_8()
108 if (ret == -EAGAIN) { in uart_read_8()
112 } else if (ret < 0) { in uart_read_8()
113 return ret; in uart_read_8()
115 } while (ret == -EAGAIN); in uart_read_8()
117 *byte = (uint8_t)ret; in uart_read_8()
124 int ret; in uart_send_result() local
128 ret = stm32_uart_getc(&handle.uart); in uart_send_result()
129 } while (ret >= 0); in uart_send_result()
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/plat/allwinner/sun50i_h616/ |
| D | sunxi_power.c | 43 int ret; in rsb_init() local
45 ret = rsb_init_controller(); in rsb_init()
46 if (ret) in rsb_init()
47 return ret; in rsb_init()
50 ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000); in rsb_init()
51 if (ret) in rsb_init()
52 return ret; in rsb_init()
55 ret = rsb_set_device_mode(AXP20X_MODE_RSB << 16 | AXP20X_MODE_REG << 8); in rsb_init()
56 if (ret) in rsb_init()
57 return ret; in rsb_init()
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/plat/allwinner/sun50i_h6/ |
| D | sunxi_power.c | 42 int ret; in rsb_init() local
44 ret = rsb_init_controller(); in rsb_init()
45 if (ret) in rsb_init()
46 return ret; in rsb_init()
49 ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000); in rsb_init()
50 if (ret) in rsb_init()
51 return ret; in rsb_init()
54 ret = rsb_set_device_mode(AXP20X_MODE_RSB << 16 | AXP20X_MODE_REG << 8); in rsb_init()
55 if (ret) in rsb_init()
56 return ret; in rsb_init()
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/plat/ti/k3/common/ |
| D | k3_psci.c | 44 int core, proc_id, device_id, ret; in k3_pwr_domain_on() local
55 ret = ti_sci_proc_request(proc_id); in k3_pwr_domain_on()
56 if (ret) { in k3_pwr_domain_on()
57 ERROR("Request for processor failed: %d\n", ret); in k3_pwr_domain_on()
61 ret = ti_sci_proc_set_boot_cfg(proc_id, k3_sec_entrypoint, 0, 0); in k3_pwr_domain_on()
62 if (ret) { in k3_pwr_domain_on()
63 ERROR("Request to set core boot address failed: %d\n", ret); in k3_pwr_domain_on()
68 ret = ti_sci_proc_set_boot_ctrl(proc_id, in k3_pwr_domain_on()
72 if (ret) { in k3_pwr_domain_on()
73 ERROR("Request to clear boot configuration failed: %d\n", ret); in k3_pwr_domain_on()
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/drivers/nxp/sfp/ |
| D | fuse_prov.c | 77 int ret = 0; in prog_srkh() local
79 ret = write_fuses(sfp_ccsr_regs->srk_hash, fuse_hdr->srkh, 8); in prog_srkh()
81 if (ret != 0) { in prog_srkh()
82 ret = (ret == ERROR_ALREADY_BLOWN) ? in prog_srkh()
86 return ret; in prog_srkh()
93 int i, ret = 0; in prog_oemuid() local
99 ret = write_fuses(&sfp_ccsr_regs->oem_uid[i], in prog_oemuid()
102 if (ret != 0) { in prog_oemuid()
103 ret = (ret == ERROR_ALREADY_BLOWN) ? in prog_oemuid()
109 return ret; in prog_oemuid()
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/drivers/nxp/i2c/ |
| D | i2c.c | 62 int ret; in tx_byte() local
66 ret = wait_for_state(ccsr_i2c, I2C_SR_IF, I2C_SR_IF); in tx_byte()
67 if (ret < 0) { in tx_byte()
69 return ret; in tx_byte()
71 if (ret & I2C_SR_RX_NAK) { in tx_byte()
82 int ret; in gen_stop() local
87 ret = wait_for_state(ccsr_i2c, I2C_SR_IDLE, I2C_SR_BB); in gen_stop()
88 if (ret < 0) { in gen_stop()
91 return ret; in gen_stop()
97 int ret; in i2c_write_addr() local
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/plat/mediatek/drivers/rtc/ |
| D | rtc_mt6359p.c | 39 int16_t ret; in rtc_enable_k_eosc() local
48 ret = RTC_Write_Trigger(); in rtc_enable_k_eosc()
49 if (ret == 0) { in rtc_enable_k_eosc()
54 ret = RTC_Write_Trigger(); in rtc_enable_k_eosc()
55 if (ret == 0) { in rtc_enable_k_eosc()
60 ret = RTC_Write_Trigger(); in rtc_enable_k_eosc()
61 if (ret == 0) { in rtc_enable_k_eosc()
66 ret = RTC_Write_Trigger(); in rtc_enable_k_eosc()
67 if (ret == 0) { in rtc_enable_k_eosc()
73 ret = RTC_Write_Trigger(); in rtc_enable_k_eosc()
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/plat/mediatek/drivers/dcm/ |
| D | mtk_dcm.c | 41 bool ret = true; in check_dcm_state() local
43 ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(); in check_dcm_state()
44 ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(); in check_dcm_state()
45 ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(); in check_dcm_state()
47 ret &= dcm_mp_cpusys_top_adb_dcm_is_on(); in check_dcm_state()
48 ret &= dcm_mp_cpusys_top_apb_dcm_is_on(); in check_dcm_state()
49 ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on(); in check_dcm_state()
50 ret &= dcm_mp_cpusys_top_misc_dcm_is_on(); in check_dcm_state()
51 ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on(); in check_dcm_state()
52 ret &= dcm_cpccfg_reg_emi_wfifo_is_on(); in check_dcm_state()
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/plat/brcm/board/stingray/driver/ |
| D | swreg.c | 161 int ret; in write_swreg_config() local
166 ret = swreg_poll(); in write_swreg_config()
167 if (ret) { in write_swreg_config()
170 return ret; in write_swreg_config()
172 return ret; in write_swreg_config()
178 int ret; in read_swreg_config() local
183 ret = swreg_poll(); in read_swreg_config()
184 if (ret) { in read_swreg_config()
187 return ret; in read_swreg_config()
192 return ret; in read_swreg_config()
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/plat/xilinx/zynqmp/pm_service/ |
| D | zynqmp_pm_svc_main.c | 178 int ret; in pm_wdt_restart_setup() local
181 ret = request_intr_type_el3(ARM_IRQ_SEC_SGI_7, zynqmp_sgi7_irq); in pm_wdt_restart_setup()
182 if (ret) { in pm_wdt_restart_setup()
187 ret = request_intr_type_el3(IRQ_TTC3_1, ttc_fiq_handler); in pm_wdt_restart_setup()
188 if (ret) in pm_wdt_restart_setup()
192 return ret; in pm_wdt_restart_setup()
229 int32_t status = 0, ret = 0; in pm_setup() local
239 ret = 0; in pm_setup()
242 ret = status; in pm_setup()
247 return ret; in pm_setup()
[all …]
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| D | pm_api_ioctl.c | 186 enum pm_ret_status ret; in pm_ioctl_set_sgmii_mode() local
211 ret = pm_mmio_write(IOU_GEM_CLK_CTRL, mask, 0U); in pm_ioctl_set_sgmii_mode()
216 ret = pm_mmio_write(IOU_GEM_CTRL, mask, val); in pm_ioctl_set_sgmii_mode()
217 if (ret != PM_RET_SUCCESS) { in pm_ioctl_set_sgmii_mode()
218 return ret; in pm_ioctl_set_sgmii_mode()
225 ret = pm_mmio_write(IOU_GEM_CLK_CTRL, mask, val); in pm_ioctl_set_sgmii_mode()
228 return ret; in pm_ioctl_set_sgmii_mode()
244 enum pm_ret_status ret; in pm_ioctl_sd_dll_reset() local
259 ret = pm_mmio_write(ZYNQMP_SD_DLL_CTRL, mask, val); in pm_ioctl_sd_dll_reset()
260 if (ret != PM_RET_SUCCESS) { in pm_ioctl_sd_dll_reset()
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/drivers/mtd/nand/ |
| D | raw_nand.c | 90 int ret; in nand_change_read_column_cmd() local
94 ret = nand_send_cmd(NAND_CMD_CHANGE_1ST, 0U); in nand_change_read_column_cmd()
95 if (ret != 0) { in nand_change_read_column_cmd()
96 return ret; in nand_change_read_column_cmd()
107 ret = nand_send_addr(addr[i], 0U); in nand_change_read_column_cmd()
108 if (ret != 0) { in nand_change_read_column_cmd()
109 return ret; in nand_change_read_column_cmd()
113 ret = nand_send_cmd(NAND_CMD_CHANGE_2ND, NAND_TCCS_MIN); in nand_change_read_column_cmd()
114 if (ret != 0) { in nand_change_read_column_cmd()
115 return ret; in nand_change_read_column_cmd()
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/drivers/brcm/ |
| D | spi_flash.c | 58 int ret; in spi_flash_read_id() local
60 ret = spi_flash_cmd(CMD_READ_ID, id, SPI_FLASH_MAX_ID_LEN); in spi_flash_read_id()
61 if (ret < 0) { in spi_flash_read_id()
62 ERROR("SF: Error %d reading JEDEC ID\n", ret); in spi_flash_read_id()
89 int ret; in spi_flash_cmd_wait() local
94 ret = spi_flash_cmd_read(&cmd, 1, &status, 1); in spi_flash_cmd_wait()
95 if (ret < 0) { in spi_flash_cmd_wait()
105 ret = -1; in spi_flash_cmd_wait()
111 return ret; in spi_flash_cmd_wait()
118 int ret; in spi_flash_write_common() local
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/plat/nvidia/tegra/soc/t194/drivers/mce/ |
| D | mce.c | 46 int32_t ret = 0; in mce_command_handler() local
50 ret = nvg_enter_cstate((uint32_t)arg0, (uint32_t)arg1); in mce_command_handler()
51 if (ret < 0) { in mce_command_handler()
52 ERROR("%s: enter_cstate failed(%d)\n", __func__, ret); in mce_command_handler()
58 ret = nvg_is_sc7_allowed(); in mce_command_handler()
59 if (ret < 0) { in mce_command_handler()
60 ERROR("%s: is_sc7_allowed failed(%d)\n", __func__, ret); in mce_command_handler()
66 ret = nvg_online_core((uint32_t)arg0); in mce_command_handler()
67 if (ret < 0) { in mce_command_handler()
68 ERROR("%s: online_core failed(%d)\n", __func__, ret); in mce_command_handler()
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/plat/mediatek/mt8186/drivers/dcm/ |
| D | mtk_dcm.c | 38 bool ret = true; in check_dcm_state() local
40 ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(); in check_dcm_state()
41 ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(); in check_dcm_state()
42 ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(); in check_dcm_state()
44 ret &= dcm_mp_cpusys_top_adb_dcm_is_on(); in check_dcm_state()
45 ret &= dcm_mp_cpusys_top_apb_dcm_is_on(); in check_dcm_state()
46 ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on(); in check_dcm_state()
47 ret &= dcm_mp_cpusys_top_cpubiu_dbg_cg_is_on(); in check_dcm_state()
48 ret &= dcm_mp_cpusys_top_misc_dcm_is_on(); in check_dcm_state()
49 ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on(); in check_dcm_state()
[all …]
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| D | mtk_dcm_utils.c | 35 bool ret = true; in dcm_mp_cpusys_top_adb_dcm_is_on() local
37 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4) & in dcm_mp_cpusys_top_adb_dcm_is_on()
40 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) & in dcm_mp_cpusys_top_adb_dcm_is_on()
44 return ret; in dcm_mp_cpusys_top_adb_dcm_is_on()
80 bool ret = true; in dcm_mp_cpusys_top_apb_dcm_is_on() local
82 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
85 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
88 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
92 return ret; in dcm_mp_cpusys_top_apb_dcm_is_on()
134 bool ret = true; in dcm_mp_cpusys_top_bus_pll_div_dcm_is_on() local
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/plat/xilinx/common/pm_service/ |
| D | pm_svc_main.c | 51 enum pm_ret_status ret; in ipi_fiq_handler() local
57 ret = pm_get_callbackdata(payload, ARRAY_SIZE(payload), 0, 0); in ipi_fiq_handler()
58 if (ret != PM_RET_SUCCESS) { in ipi_fiq_handler()
59 payload[0] = ret; in ipi_fiq_handler()
132 int32_t ret = 0; in pm_setup() local
145 ret = request_intr_type_el3(PLAT_VERSAL_IPI_IRQ, ipi_fiq_handler); in pm_setup()
146 if (ret != 0) { in pm_setup()
151 return ret; in pm_setup()
167 enum pm_ret_status ret; in eemi_for_compatibility() local
175 ret = pm_api_ioctl(pm_arg[0], pm_arg[1], pm_arg[2], in eemi_for_compatibility()
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/lib/libfdt/ |
| D | fdt_overlay.c | 48 int path_len = 0, ret; in fdt_overlay_target_offset() local
60 ret = fdt_path_offset(fdt, path); in fdt_overlay_target_offset()
62 ret = path_len; in fdt_overlay_target_offset()
64 ret = fdt_node_offset_by_phandle(fdt, phandle); in fdt_overlay_target_offset()
73 if (ret < 0 && path_len == -FDT_ERR_NOTFOUND) in fdt_overlay_target_offset()
74 ret = -FDT_ERR_BADOVERLAY; in fdt_overlay_target_offset()
77 if (ret < 0) in fdt_overlay_target_offset()
78 return ret; in fdt_overlay_target_offset()
84 return ret; in fdt_overlay_target_offset()
145 int ret; in overlay_adjust_node_phandles() local
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/plat/mediatek/mt8192/drivers/dcm/ |
| D | mtk_dcm.c | 36 bool ret = true; in check_dcm_state() local
38 ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(); in check_dcm_state()
39 ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(); in check_dcm_state()
40 ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(); in check_dcm_state()
42 ret &= dcm_mp_cpusys_top_adb_dcm_is_on(); in check_dcm_state()
43 ret &= dcm_mp_cpusys_top_apb_dcm_is_on(); in check_dcm_state()
44 ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on(); in check_dcm_state()
45 ret &= dcm_mp_cpusys_top_misc_dcm_is_on(); in check_dcm_state()
46 ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on(); in check_dcm_state()
47 ret &= dcm_cpccfg_reg_emi_wfifo_is_on(); in check_dcm_state()
[all …]
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| D | mtk_dcm_utils.c | 44 bool ret = true; in dcm_mp_cpusys_top_adb_dcm_is_on() local
46 ret &= ((mmio_read_32(MP_ADB_DCM_CFG0) & in dcm_mp_cpusys_top_adb_dcm_is_on()
49 ret &= ((mmio_read_32(MP_ADB_DCM_CFG4) & in dcm_mp_cpusys_top_adb_dcm_is_on()
52 ret &= ((mmio_read_32(MCUSYS_DCM_CFG0) & in dcm_mp_cpusys_top_adb_dcm_is_on()
56 return ret; in dcm_mp_cpusys_top_adb_dcm_is_on()
98 bool ret = true; in dcm_mp_cpusys_top_apb_dcm_is_on() local
100 ret &= ((mmio_read_32(MP_MISC_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
103 ret &= ((mmio_read_32(MCUSYS_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
106 ret &= ((mmio_read_32(MP0_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
110 return ret; in dcm_mp_cpusys_top_apb_dcm_is_on()
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/plat/mediatek/mt8195/drivers/dcm/ |
| D | mtk_dcm.c | 36 bool ret = true; in check_dcm_state() local
38 ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(); in check_dcm_state()
39 ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(); in check_dcm_state()
40 ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(); in check_dcm_state()
42 ret &= dcm_mp_cpusys_top_adb_dcm_is_on(); in check_dcm_state()
43 ret &= dcm_mp_cpusys_top_apb_dcm_is_on(); in check_dcm_state()
44 ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on(); in check_dcm_state()
45 ret &= dcm_mp_cpusys_top_misc_dcm_is_on(); in check_dcm_state()
46 ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on(); in check_dcm_state()
47 ret &= dcm_cpccfg_reg_emi_wfifo_is_on(); in check_dcm_state()
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/plat/mediatek/mt8173/ |
| D | plat_sip_calls.c | 45 uint32_t ret; in mt_sip_pwr_on_mtcmos() local
47 ret = mtcmos_non_cpu_ctrl(1, val); in mt_sip_pwr_on_mtcmos()
48 if (ret) in mt_sip_pwr_on_mtcmos()
56 uint32_t ret; in mt_sip_pwr_off_mtcmos() local
58 ret = mtcmos_non_cpu_ctrl(0, val); in mt_sip_pwr_off_mtcmos()
59 if (ret) in mt_sip_pwr_off_mtcmos()
79 uint64_t ret; in mediatek_plat_sip_handler() local
83 ret = mt_sip_pwr_on_mtcmos((uint32_t)x1); in mediatek_plat_sip_handler()
84 SMC_RET1(handle, ret); in mediatek_plat_sip_handler()
87 ret = mt_sip_pwr_off_mtcmos((uint32_t)x1); in mediatek_plat_sip_handler()
[all …]
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