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Searched refs:reg_val (Results 1 – 14 of 14) sorted by relevance

/trusted-firmware-a-3.6.0-3.5.0/plat/marvell/armada/a8k/common/
Dplat_pm.c121 uint32_t reg_val; in plat_marvell_cpu_powerdown() local
127 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); in plat_marvell_cpu_powerdown()
128 reg_val |= 0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET; in plat_marvell_cpu_powerdown()
129 mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); in plat_marvell_cpu_powerdown()
133 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); in plat_marvell_cpu_powerdown()
135 } while (!(reg_val & (0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET)) && in plat_marvell_cpu_powerdown()
139 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); in plat_marvell_cpu_powerdown()
140 reg_val &= ~PWRC_CPUN_CR_PWR_DN_RQ_MASK; in plat_marvell_cpu_powerdown()
141 mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); in plat_marvell_cpu_powerdown()
146 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); in plat_marvell_cpu_powerdown()
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Dplat_ble_setup.c360 uint32_t reg_val, avs_workpoint, freq_pidi_mode; in ble_plat_svc_config() local
373 reg_val = mmio_read_32(MVEBU_AP_EFUSE_SRV_CTRL_REG); in ble_plat_svc_config()
374 reg_val &= ~EFUSE_SRV_CTRL_LD_SELECT_MASK; in ble_plat_svc_config()
375 mmio_write_32(MVEBU_AP_EFUSE_SRV_CTRL_REG, reg_val); in ble_plat_svc_config()
531 reg_val = mmio_read_32(AVS_EN_CTRL_REG); in ble_plat_svc_config()
532 avs_workpoint = (reg_val & in ble_plat_svc_config()
612 reg_val = mmio_read_32(AVS_EN_CTRL_REG); in ble_plat_svc_config()
614 (reg_val & AVS_VDD_LOW_LIMIT_MASK) >> AVS_LOW_VDD_LIMIT_OFFSET, in ble_plat_svc_config()
616 reg_val &= ~(AVS_VDD_LOW_LIMIT_MASK | AVS_VDD_HIGH_LIMIT_MASK); in ble_plat_svc_config()
617 reg_val |= 0x1 << AVS_ENABLE_OFFSET; in ble_plat_svc_config()
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/trusted-firmware-a-3.6.0-3.5.0/drivers/arm/gic/v3/
Dgic600ae_fmu_helpers.c100 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRFR_LO + n * 64U); in gic_fmu_read_errfr() local
102 reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRFR_HI + n * 64U) << 32); in gic_fmu_read_errfr()
103 return reg_val; in gic_fmu_read_errfr()
116 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRCTLR_LO + n * 64U); in gic_fmu_read_errctlr() local
118 reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRCTLR_HI + n * 64U) << 32); in gic_fmu_read_errctlr()
119 return reg_val; in gic_fmu_read_errctlr()
132 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRSTATUS_LO + n * 64U); in gic_fmu_read_errstatus() local
134 reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRSTATUS_HI + n * 64U) << 32); in gic_fmu_read_errstatus()
135 return reg_val; in gic_fmu_read_errstatus()
147 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRGSR_LO); in gic_fmu_read_errgsr() local
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/trusted-firmware-a-3.6.0-3.5.0/drivers/nxp/timer/
Dnxp_timer.c122 unsigned int reg_val; in ls_configure_sys_timer() local
125 reg_val = (1U << CNTACR_RPCT_SHIFT) | (1U << CNTACR_RVCT_SHIFT); in ls_configure_sys_timer()
126 reg_val |= (1U << CNTACR_RFRQ_SHIFT) | (1U << CNTACR_RVOFF_SHIFT); in ls_configure_sys_timer()
127 reg_val |= (1U << CNTACR_RWVT_SHIFT) | (1U << CNTACR_RWPT_SHIFT); in ls_configure_sys_timer()
129 CNTACR_BASE(plat_ls_ns_timer_frame_id), reg_val); in ls_configure_sys_timer()
133 reg_val = (1U << CNTNSAR_NS_SHIFT(plat_ls_ns_timer_frame_id)); in ls_configure_sys_timer()
134 mmio_write_32(ls_sys_timctl_base + CNTNSAR, reg_val); in ls_configure_sys_timer()
/trusted-firmware-a-3.6.0-3.5.0/plat/arm/common/
Darm_common.c132 unsigned int reg_val; in arm_configure_sys_timer() local
138 reg_val = (1U << CNTACR_RPCT_SHIFT) | (1U << CNTACR_RVCT_SHIFT); in arm_configure_sys_timer()
139 reg_val |= (1U << CNTACR_RFRQ_SHIFT) | (1U << CNTACR_RVOFF_SHIFT); in arm_configure_sys_timer()
140 reg_val |= (1U << CNTACR_RWVT_SHIFT) | (1U << CNTACR_RWPT_SHIFT); in arm_configure_sys_timer()
141 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); in arm_configure_sys_timer()
144 reg_val = (1U << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); in arm_configure_sys_timer()
145 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); in arm_configure_sys_timer()
/trusted-firmware-a-3.6.0-3.5.0/drivers/nxp/crypto/caam/src/
Dsec_hw_specific.c328 uint32_t reg_val = 0U; in hw_job_ring_set_coalescing_param() local
333 reg_val |= (irq_coalescing_count << JR_REG_JRCFG_LO_ICDCT_SHIFT); in hw_job_ring_set_coalescing_param()
336 reg_val |= (irq_coalescing_timer << JR_REG_JRCFG_LO_ICTT_SHIFT); in hw_job_ring_set_coalescing_param()
339 sec_out32(&regs->jrcfg1, reg_val); in hw_job_ring_set_coalescing_param()
348 uint32_t reg_val = 0U; in hw_job_ring_enable_coalescing() local
353 reg_val = sec_in32(&regs->jrcfg1); in hw_job_ring_enable_coalescing()
356 reg_val |= JR_REG_JRCFG_LO_ICEN_EN; in hw_job_ring_enable_coalescing()
359 sec_out32(&regs->jrcfg1, reg_val); in hw_job_ring_enable_coalescing()
368 uint32_t reg_val = 0U; in hw_job_ring_disable_coalescing() local
373 reg_val = sec_in32(&regs->jrcfg1); in hw_job_ring_disable_coalescing()
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/trusted-firmware-a-3.6.0-3.5.0/drivers/arm/gic/common/
Dgic_common.c251 unsigned int reg_val = gicd_read_igroupr(base, id); in gicd_get_igroupr() local
253 return (reg_val >> bit_num) & 0x1U; in gicd_get_igroupr()
259 unsigned int reg_val = gicd_read_igroupr(base, id); in gicd_set_igroupr() local
261 gicd_write_igroupr(base, id, reg_val | (1U << bit_num)); in gicd_set_igroupr()
267 unsigned int reg_val = gicd_read_igroupr(base, id); in gicd_clr_igroupr() local
269 gicd_write_igroupr(base, id, reg_val & ~(1U << bit_num)); in gicd_clr_igroupr()
303 unsigned int reg_val = gicd_read_isactiver(base, id); in gicd_get_isactiver() local
305 return (reg_val >> bit_num) & 0x1U; in gicd_get_isactiver()
335 uint32_t reg_val = gicd_read_icfgr(base, id); in gicd_set_icfgr() local
338 reg_val &= ~(GIC_CFG_MASK << bit_shift); in gicd_set_icfgr()
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/trusted-firmware-a-3.6.0-3.5.0/drivers/arm/gic/v2/
Dgicdv2_helpers.c249 unsigned int reg_val = gicd_read_igroupr(base, id); in gicd_get_igroupr() local
251 return (reg_val >> bit_num) & 0x1U; in gicd_get_igroupr()
257 unsigned int reg_val = gicd_read_igroupr(base, id); in gicd_set_igroupr() local
259 gicd_write_igroupr(base, id, reg_val | (1U << bit_num)); in gicd_set_igroupr()
265 unsigned int reg_val = gicd_read_igroupr(base, id); in gicd_clr_igroupr() local
267 gicd_write_igroupr(base, id, reg_val & ~(1U << bit_num)); in gicd_clr_igroupr()
301 unsigned int reg_val = gicd_read_isactiver(base, id); in gicd_get_isactiver() local
303 return (reg_val >> bit_num) & 0x1U; in gicd_get_isactiver()
333 uint32_t reg_val = gicd_read_icfgr(base, id); in gicd_set_icfgr() local
336 reg_val &= ~(GIC_CFG_MASK << bit_shift); in gicd_set_icfgr()
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/trusted-firmware-a-3.6.0-3.5.0/drivers/arm/smmu/
Dsmmu_v3.c20 uint32_t reg_val; in smmuv3_poll() local
26 reg_val = mmio_read_32(smmu_reg); in smmuv3_poll()
27 if ((reg_val & mask) == value) in smmuv3_poll()
32 ERROR("Read value 0x%x, expected 0x%x\n", reg_val, in smmuv3_poll()
33 value == 0U ? reg_val & ~mask : reg_val | mask); in smmuv3_poll()
/trusted-firmware-a-3.6.0-3.5.0/drivers/brcm/emmc/
Demmc_chal_sd.c194 uint32_t reg_val; in chal_sd_init() local
207 reg_val = 0; in chal_sd_init()
208 reg_val |= (1 << ICFG_SDIO0_CAP0__SLOT_TYPE_R); in chal_sd_init()
209 reg_val |= (0 << ICFG_SDIO0_CAP0__INT_MODE_R); in chal_sd_init()
210 reg_val |= (0 << ICFG_SDIO0_CAP0__SYS_BUS_64BIT_R); in chal_sd_init()
211 reg_val |= (1 << ICFG_SDIO0_CAP0__VOLTAGE_1P8V_R); in chal_sd_init()
212 reg_val |= (1 << ICFG_SDIO0_CAP0__VOLTAGE_3P0V_R); in chal_sd_init()
213 reg_val |= (1 << ICFG_SDIO0_CAP0__VOLTAGE_3P3V_R); in chal_sd_init()
214 reg_val |= (1 << ICFG_SDIO0_CAP0__SUSPEND_RESUME_R); in chal_sd_init()
215 reg_val |= (1 << ICFG_SDIO0_CAP0__SDMA_R); in chal_sd_init()
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/trusted-firmware-a-3.6.0-3.5.0/plat/socionext/synquacer/
Dsq_bl31_setup.c165 unsigned int reg_val; in sq_configure_sys_timer() local
168 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); in sq_configure_sys_timer()
169 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); in sq_configure_sys_timer()
170 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); in sq_configure_sys_timer()
172 CNTACR_BASE(PLAT_SQ_NSTIMER_FRAME_ID), reg_val); in sq_configure_sys_timer()
174 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_SQ_NSTIMER_FRAME_ID)); in sq_configure_sys_timer()
175 mmio_write_32(SQ_SYS_TIMCTL_BASE + CNTNSAR, reg_val); in sq_configure_sys_timer()
/trusted-firmware-a-3.6.0-3.5.0/drivers/marvell/mochi/
Dap807_setup.c319 uint32_t reg_val; in ap807_dram_phy_access_config() local
321 reg_val = mmio_read_32(DSS_SCR_REG); in ap807_dram_phy_access_config()
322 reg_val &= ~(DSS_PPROT_MASK << DSS_PPROT_OFFS); in ap807_dram_phy_access_config()
323 reg_val |= ((DSS_PPROT_PRIV_SECURE_DATA & DSS_PPROT_MASK) << in ap807_dram_phy_access_config()
325 mmio_write_32(DSS_SCR_REG, reg_val); in ap807_dram_phy_access_config()
Dcp110_setup.c395 uint32_t reg_val, efuse; in cp110_trng_init() local
398 reg_val = mmio_read_32(MVEBU_AP_EFUSE_SRV_CTRL_REG); in cp110_trng_init()
399 reg_val &= ~EFUSE_SRV_CTRL_LD_SELECT_MASK; in cp110_trng_init()
400 mmio_write_32(MVEBU_AP_EFUSE_SRV_CTRL_REG, reg_val); in cp110_trng_init()
/trusted-firmware-a-3.6.0-3.5.0/plat/mediatek/drivers/apusys/mt8188/
Dapusys_power.c27 uint32_t reg_val, count; in apu_poll() local
35 reg_val = mmio_read_32(reg); in apu_poll()
36 if ((reg_val & mask) == value) { in apu_poll()
44 ERROR(MODULE_TAG "Read value 0x%x, expected 0x%x\n", reg_val, in apu_poll()
45 (value == 0U) ? (reg_val & ~mask) : (reg_val | mask)); in apu_poll()