Searched refs:plat_params (Results 1 – 6 of 6) sorted by relevance
165 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in plat_early_platform_setup() local174 tegra_memctrl_tzdram_setup(plat_params->tzdram_base, in plat_early_platform_setup()175 (uint32_t)plat_params->tzdram_size); in plat_early_platform_setup()178 if (plat_params->l2_ecc_parity_prot_dis != 1) { in plat_early_platform_setup()204 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in plat_late_platform_setup() local210 if (plat_params->sc7entry_fw_base && plat_params->sc7entry_fw_size) { in plat_late_platform_setup()212 assert(plat_params->sc7entry_fw_size <= TEGRA_IRAM_A_SIZE); in plat_late_platform_setup()221 assert(plat_params->tzdram_base > plat_params->sc7entry_fw_base); in plat_late_platform_setup()223 sc7entry_end = plat_params->sc7entry_fw_base + in plat_late_platform_setup()224 plat_params->sc7entry_fw_size; in plat_late_platform_setup()[all …]
47 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in tegra_soc_validate_power_state() local75 if (!tegra_bpmp_init() && !plat_params->sc7entry_fw_base) in tegra_soc_validate_power_state()347 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in tegra_soc_pwr_domain_power_down_wfi() local409 (const void *)(plat_params->sc7entry_fw_base + SC7ENTRY_FW_HEADER_SIZE_BYTES), in tegra_soc_pwr_domain_power_down_wfi()410 plat_params->sc7entry_fw_size - SC7ENTRY_FW_HEADER_SIZE_BYTES); in tegra_soc_pwr_domain_power_down_wfi()435 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in tegra_soc_pwr_domain_on_finish() local441 if (plat_params->l2_ecc_parity_prot_dis != 1) { in tegra_soc_pwr_domain_on_finish()489 if (plat_params->sc7entry_fw_base != 0U) { in tegra_soc_pwr_domain_on_finish()491 offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base; in tegra_soc_pwr_domain_on_finish()492 tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base, in tegra_soc_pwr_domain_on_finish()[all …]
96 plat_params_from_bl2_t *plat_params = plat_get_bl31_plat_params(); in bl31_early_platform_setup2() local125 assert(plat_params != NULL); in bl31_early_platform_setup2()126 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; in bl31_early_platform_setup2()127 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; in bl31_early_platform_setup2()128 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; in bl31_early_platform_setup2()129 plat_bl31_params_from_bl2.l2_ecc_parity_prot_dis = plat_params->l2_ecc_parity_prot_dis; in bl31_early_platform_setup2()130 plat_bl31_params_from_bl2.sc7entry_fw_size = plat_params->sc7entry_fw_size; in bl31_early_platform_setup2()131 plat_bl31_params_from_bl2.sc7entry_fw_base = plat_params->sc7entry_fw_base; in bl31_early_platform_setup2()145 plat_enable_console(plat_params->uart_id); in bl31_early_platform_setup2()152 ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base, in bl31_early_platform_setup2()[all …]
166 const plat_params_from_bl2_t *plat_params; in tegra_pwr_domain_on_finish() local193 plat_params = bl31_get_plat_params(); in tegra_pwr_domain_on_finish()194 tegra_memctrl_tzdram_setup(plat_params->tzdram_base, in tegra_pwr_domain_on_finish()195 (uint32_t)plat_params->tzdram_size); in tegra_pwr_domain_on_finish()
189 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in plat_early_platform_setup() local201 tegra_memctrl_tzdram_setup(plat_params->tzdram_base, in plat_early_platform_setup()202 (uint32_t)plat_params->tzdram_size); in plat_early_platform_setup()210 if ((plat_params->l2_ecc_parity_prot_dis != 1) && in plat_early_platform_setup()
376 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in tegra_soc_pwr_domain_on_finish() local384 if ((plat_params->l2_ecc_parity_prot_dis != 1) && (impl != DENVER_IMPL)) { in tegra_soc_pwr_domain_on_finish()
