| /trusted-firmware-a-3.6.0-3.5.0/plat/nvidia/tegra/soc/t186/drivers/include/ |
| D | mce_private.h | 89 int32_t (*enter_cstate)(uint32_t ari_base, uint32_t state,
95 int32_t (*update_cstate_info)(uint32_t ari_base,
107 int32_t (*update_crossover_time)(uint32_t ari_base,
120 int32_t (*write_cstate_stats)(uint32_t ari_base,
136 int32_t (*is_ccx_allowed)(uint32_t ari_base, uint32_t state,
146 int32_t (*is_sc7_allowed)(uint32_t ari_base, uint32_t state,
153 int32_t (*online_core)(uint32_t ari_base, uint32_t cpuid);
158 int32_t (*cc3_ctrl)(uint32_t ari_base,
166 int32_t (*update_reset_vector)(uint32_t ari_base);
171 int32_t (*roc_flush_cache)(uint32_t ari_base);
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| /trusted-firmware-a-3.6.0-3.5.0/plat/nvidia/tegra/include/ |
| D | tegra_private.h | 41 int32_t uart_id;
43 int32_t l2_ecc_parity_prot_dis;
77 int32_t tegra_soc_validate_power_state(uint32_t power_state,
82 void plat_enable_console(int32_t id);
94 int32_t plat_lock_cpu_vectors(void);
98 int32_t tegra_fiq_get_intr_context(void);
111 int32_t tegra_system_suspended(void);
112 int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state);
113 int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state);
114 int32_t tegra_soc_pwr_domain_on(u_register_t mpidr);
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/plat/mediatek/mt8195/drivers/apusys/ |
| D | apupwr_clkctl.h | 13 int32_t apupwr_smc_acc_init_all(void);
15 int32_t apupwr_smc_acc_set_parent(uint32_t freq, uint32_t domain);
16 int32_t apupwr_smc_pll_set_rate(uint32_t pll, bool div2, uint32_t domain);
17 int32_t apupwr_smc_bulk_pll(bool enable);
20 int32_t apu_pll_enable(int32_t pll_idx, bool enable, bool fhctl_en);
21 int32_t anpu_pll_set_rate(enum dvfs_voltage_domain domain,
22 enum pll_set_rate_mode mode, int32_t freq);
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| /trusted-firmware-a-3.6.0-3.5.0/include/drivers/brcm/emmc/ |
| D | emmc_chal_sd.h | 169 int32_t chal_sd_start(CHAL_HANDLE *sdHandle, uint32_t mode,
171 int32_t chal_sd_config(CHAL_HANDLE *sdHandle, uint32_t speed,
174 int32_t chal_sd_stop(void);
175 int32_t chal_sd_set_dma(CHAL_HANDLE *sdHandle, uint32_t mode);
177 int32_t chal_sd_config_bus_width(CHAL_HANDLE *sdHandle, int32_t width);
178 int32_t chal_sd_send_cmd(CHAL_HANDLE *sdHandle, uint32_t cmdIndex,
180 int32_t chal_sd_set_dma_addr(CHAL_HANDLE *sdHandle, uintptr_t address);
181 int32_t chal_sd_set_clock(CHAL_HANDLE *sdHandle,
184 int32_t chal_sd_setup_xfer(CHAL_HANDLE *sdHandle, uint8_t *data,
185 uint32_t length, int32_t dir);
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/include/drivers/ |
| D | scmi-msg.h | 118 int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id,
129 int32_t plat_scmi_clock_rates_by_step(unsigned int agent_id,
149 int32_t plat_scmi_clock_set_rate(unsigned int agent_id, unsigned int scmi_id,
158 int32_t plat_scmi_clock_get_state(unsigned int agent_id, unsigned int scmi_id);
167 int32_t plat_scmi_clock_set_state(unsigned int agent_id, unsigned int scmi_id,
194 int32_t plat_scmi_rstd_autonomous(unsigned int agent_id, unsigned int scmi_id,
204 int32_t plat_scmi_rstd_set_state(unsigned int agent_id, unsigned int scmi_id,
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| /trusted-firmware-a-3.6.0-3.5.0/drivers/renesas/common/io/ |
| D | io_memdrv.c | 20 static int32_t memdrv_dev_open(const uintptr_t dev __attribute__ ((unused)),
22 static int32_t memdrv_dev_close(io_dev_info_t *dev_info);
42 static int32_t memdrv_block_open(io_dev_info_t *dev_info, const uintptr_t spec, in memdrv_block_open()
66 static int32_t memdrv_block_seek(io_entity_t *entity, int32_t mode, in memdrv_block_seek()
78 static int32_t memdrv_block_read(io_entity_t *entity, uintptr_t buffer, in memdrv_block_read()
101 static int32_t memdrv_block_close(io_entity_t *entity) in memdrv_block_close()
131 static int32_t memdrv_dev_open(const uintptr_t dev __attribute__ ((unused)), in memdrv_dev_open()
139 static int32_t memdrv_dev_close(io_dev_info_t *dev_info) in memdrv_dev_close()
144 int32_t rcar_register_io_dev_memdrv(const io_dev_connector_t **dev_con) in rcar_register_io_dev_memdrv()
146 int32_t result; in rcar_register_io_dev_memdrv()
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| D | io_emmcdrv.c | 21 static int32_t emmcdrv_dev_open(const uintptr_t spec __attribute__ ((unused)),
23 static int32_t emmcdrv_dev_close(io_dev_info_t *dev_info);
41 static int32_t emmcdrv_block_seek(io_entity_t *entity, int32_t mode, in emmcdrv_block_seek()
53 static int32_t emmcdrv_block_read(io_entity_t *entity, uintptr_t buffer, in emmcdrv_block_read()
58 int32_t result = IO_SUCCESS; in emmcdrv_block_read()
83 static int32_t emmcdrv_block_open(io_dev_info_t *dev_info, in emmcdrv_block_open()
127 static int32_t emmcdrv_block_close(io_entity_t *entity) in emmcdrv_block_close()
156 static int32_t emmcdrv_dev_open(const uintptr_t spec __attribute__ ((unused)), in emmcdrv_dev_open()
164 static int32_t emmcdrv_dev_close(io_dev_info_t *dev_info) in emmcdrv_dev_close()
169 int32_t rcar_register_io_dev_emmcdrv(const io_dev_connector_t **dev_con) in rcar_register_io_dev_emmcdrv()
[all …]
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| D | io_rcar.h | 10 int32_t rcar_register_io_dev(const io_dev_connector_t **dev_con);
11 int32_t rcar_get_certificate(const int32_t name, uint32_t *cert);
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| /trusted-firmware-a-3.6.0-3.5.0/plat/nvidia/tegra/soc/t194/drivers/include/ |
| D | mce_private.h | 51 int32_t nvg_set_cstate_stat_query_value(uint64_t data);
53 int32_t nvg_is_sc7_allowed(void);
54 int32_t nvg_online_core(uint32_t core);
55 int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx);
56 int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time);
57 int32_t nvg_roc_clean_cache_trbits(void);
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| /trusted-firmware-a-3.6.0-3.5.0/plat/nvidia/tegra/drivers/bpmp_ipc/ |
| D | ivc.h | 33 int32_t tegra_ivc_init(struct ivc *ivc, uintptr_t rx_base, uintptr_t tx_base,
38 int32_t tegra_ivc_channel_notified(struct ivc *ivc);
40 int32_t tegra_ivc_write_advance(struct ivc *ivc);
42 int32_t tegra_ivc_write(struct ivc *ivc, const void *buf, size_t size);
43 int32_t tegra_ivc_read_advance(struct ivc *ivc);
45 int32_t tegra_ivc_read(struct ivc *ivc, void *buf, size_t max_read);
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| /trusted-firmware-a-3.6.0-3.5.0/plat/nvidia/tegra/soc/t186/drivers/mce/ |
| D | ari.c | 80 static int32_t ari_request_wait(uint32_t ari_base, uint32_t evt_mask, uint32_t req, in ari_request_wait()
85 int32_t ret = 0; in ari_request_wait()
137 int32_t ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time) in ari_enter_cstate()
139 int32_t ret = 0; in ari_enter_cstate()
160 int32_t ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, in ari_update_cstate_info()
198 int32_t ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time) in ari_update_crossover_time()
200 int32_t ret = 0; in ari_update_crossover_time()
220 int32_t ret; in ari_read_cstate_stats()
241 int32_t ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats) in ari_write_cstate_stats()
254 int32_t ret; in ari_enumeration_misc()
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| D | nvg.c | 19 int32_t nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time) in nvg_enter_cstate()
21 int32_t ret = 0; in nvg_enter_cstate()
47 int32_t nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, in nvg_update_cstate_info()
89 int32_t nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time) in nvg_update_crossover_time()
91 int32_t ret = 0; in nvg_update_crossover_time()
137 int32_t nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats) in nvg_write_cstate_stats()
163 int32_t nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) in nvg_is_ccx_allowed()
173 int32_t nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) in nvg_is_sc7_allowed()
176 int32_t ret; in nvg_is_sc7_allowed()
204 int32_t nvg_online_core(uint32_t ari_base, uint32_t core) in nvg_online_core()
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/plat/nvidia/tegra/soc/t194/drivers/mce/ |
| D | nvg.c | 101 int32_t nvg_is_sc7_allowed(void) in nvg_is_sc7_allowed()
107 return (int32_t)nvg_get_result(); in nvg_is_sc7_allowed()
116 int32_t nvg_online_core(uint32_t core) in nvg_online_core()
118 int32_t ret = 0; in nvg_online_core()
139 int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx) in nvg_update_ccplex_gsc()
141 int32_t ret = 0; in nvg_update_ccplex_gsc()
158 int32_t nvg_roc_clean_cache_trbits(void) in nvg_roc_clean_cache_trbits()
160 int32_t ret = 0; in nvg_roc_clean_cache_trbits()
179 int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time) in nvg_enter_cstate()
181 int32_t ret = 0; in nvg_enter_cstate()
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| D | mce.c | 43 int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, in mce_command_handler()
46 int32_t ret = 0; in mce_command_handler()
85 int32_t mce_update_gsc_videomem(void) in mce_update_gsc_videomem()
87 int32_t ret; in mce_update_gsc_videomem()
104 int32_t mce_update_gsc_tzdram(void) in mce_update_gsc_tzdram()
106 int32_t ret; in mce_update_gsc_tzdram()
179 int32_t ret = 0; in mce_enable_strict_checking()
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| /trusted-firmware-a-3.6.0-3.5.0/drivers/renesas/common/console/ |
| D | rcar_printf.h | 12 int32_t rcar_set_log_data(int32_t c);
13 int32_t rcar_log_init(void);
|
| /trusted-firmware-a-3.6.0-3.5.0/drivers/scmi-msg/ |
| D | reset_domain.h | 43 int32_t status;
63 int32_t status;
85 int32_t status;
101 int32_t status;
109 int32_t status;
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| D | power_domain.h | 30 int32_t status;
40 int32_t status;
54 int32_t status;
69 int32_t status;
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| D | entry.c | 39 void scmi_status_response(struct scmi_msg *msg, int32_t status) in scmi_status_response()
41 assert(msg->out && msg->out_size >= sizeof(int32_t)); in scmi_status_response()
43 memcpy(msg->out, &status, sizeof(int32_t)); in scmi_status_response()
44 msg->out_size_out = sizeof(int32_t); in scmi_status_response()
54 assert(payload && size >= sizeof(int32_t) && size <= msg->out_size && in scmi_write_response()
55 msg->out && msg->out_size >= sizeof(int32_t)); in scmi_write_response()
|
| /trusted-firmware-a-3.6.0-3.5.0/plat/arm/board/morello/ |
| D | morello_bl31_setup.c | 74 int32_t plat_is_smccc_feature_available(u_register_t fid) in plat_is_smccc_feature_available()
85 int32_t plat_get_soc_version(void) in plat_get_soc_version()
91 return (int32_t) in plat_get_soc_version()
98 int32_t plat_get_soc_revision(void) in plat_get_soc_revision()
100 return (int32_t)plat_info.silicon_revision; in plat_get_soc_revision()
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| /trusted-firmware-a-3.6.0-3.5.0/plat/mediatek/common/ |
| D | mtk_plat_common.c | 45 int32_t plat_is_smccc_feature_available(u_register_t fid) in plat_is_smccc_feature_available()
55 int32_t plat_get_soc_version(void) in plat_get_soc_version()
59 return (int32_t)(manfid | (SOC_CHIP_ID & SOC_ID_IMPL_DEF_MASK)); in plat_get_soc_version()
62 int32_t plat_get_soc_revision(void) in plat_get_soc_revision()
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| /trusted-firmware-a-3.6.0-3.5.0/include/drivers/rambus/ |
| D | trng_ip_76.h | 14 int32_t eip76_rng_read_rand_buf(void *data, bool wait);
15 int32_t eip76_rng_probe(uintptr_t base_addr);
16 int32_t eip76_rng_get_random(uint8_t *data, uint32_t len);
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| /trusted-firmware-a-3.6.0-3.5.0/plat/xilinx/zynqmp/pm_service/ |
| D | pm_api_clock.c | 234 int32_t (*parents)[];
799 static int32_t can_mio_parents[] = {
828 .parents = &((int32_t []) {CLK_APLL_PRE_SRC, CLK_NA_PARENT}),
836 .parents = &((int32_t []) {
854 .parents = &((int32_t []) {CLK_APLL_INT, CLK_NA_PARENT}),
862 .parents = &((int32_t []) {
874 .parents = &((int32_t []) {
892 .parents = &((int32_t []) {
904 .parents = &((int32_t []) {CLK_DPLL_PRE_SRC, CLK_NA_PARENT}),
912 .parents = &((int32_t []) {
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/plat/arm/board/juno/ |
| D | juno_common.c | 113 int32_t plat_is_smccc_feature_available(u_register_t fid) in plat_is_smccc_feature_available()
124 int32_t plat_get_soc_version(void) in plat_get_soc_version()
126 return (int32_t) in plat_get_soc_version()
133 int32_t plat_get_soc_revision(void) in plat_get_soc_revision()
138 return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) & in plat_get_soc_revision()
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| /trusted-firmware-a-3.6.0-3.5.0/drivers/arm/dcc/ |
| D | dcc_console.c | 74 static int32_t dcc_status_timeout(uint32_t mask) in dcc_status_timeout()
92 static int32_t dcc_console_putc(int32_t ch, struct console *console) in dcc_console_putc()
105 static int32_t dcc_console_getc(struct console *console) in dcc_console_getc()
117 int32_t dcc_console_init(unsigned long base_addr, uint32_t uart_clk, in dcc_console_init()
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| /trusted-firmware-a-3.6.0-3.5.0/plat/nvidia/tegra/soc/t194/drivers/se/ |
| D | se.c | 56 int32_t ret = 0; in tegra_se_is_operation_complete()
100 int32_t ret = 0; in tegra_se_is_ready()
141 static int32_t tegra_se_save_context(void) in tegra_se_save_context()
143 int32_t ret = -ECANCELED; in tegra_se_save_context()
193 static int32_t tegra_se_sha256_hash_operation_complete(void) in tegra_se_sha256_hash_operation_complete()
229 static int32_t tegra_se_start_normal_operation(uint64_t src_addr, in tegra_se_start_normal_operation()
236 int32_t ret = 0; in tegra_se_start_normal_operation()
272 static int32_t tegra_se_calculate_sha256_hash(uint64_t src_addr, in tegra_se_calculate_sha256_hash()
276 int32_t ret = 0; in tegra_se_calculate_sha256_hash()
385 static int32_t tegra_se_save_sha256_pmc_scratch(void) in tegra_se_save_sha256_pmc_scratch()
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