Home
last modified time | relevance | path

Searched refs:cfg (Results 1 – 25 of 54) sorted by relevance

123

/trusted-firmware-a-3.6.0-3.5.0/plat/brcm/board/stingray/include/
Dscp_utils.h20 #define SCP_READ_CFG(cfg) mmio_read_32(CRMU_CFG_BASE + \ argument
21 offsetof(M0CFG, cfg))
22 #define SCP_WRITE_CFG(cfg, value) mmio_write_32(CRMU_CFG_BASE + \ argument
23 offsetof(M0CFG, cfg), value)
25 #define SCP_READ_CFG16(cfg) mmio_read_16(CRMU_CFG_BASE + \ argument
26 offsetof(M0CFG, cfg))
27 #define SCP_WRITE_CFG16(cfg, value) mmio_write_16(CRMU_CFG_BASE + \ argument
28 offsetof(M0CFG, cfg), value)
30 #define SCP_READ_CFG8(cfg) mmio_read_8(CRMU_CFG_BASE + \ argument
31 offsetof(M0CFG, cfg))
[all …]
/trusted-firmware-a-3.6.0-3.5.0/drivers/amlogic/crypto/
Dsha_dma.c20 uint32_t cfg; member
31 (ASD_DESC_GET((d)->cfg, ASD_DESC_LEN_MASK, ASD_DESC_LEN_OFF))
33 (ASD_DESC_SET((d)->cfg, v, ASD_DESC_LEN_MASK, ASD_DESC_LEN_OFF))
38 (ASD_DESC_GET((d)->cfg, ASD_DESC_IRQ_MASK, ASD_DESC_IRQ_OFF))
40 (ASD_DESC_SET((d)->cfg, v, ASD_DESC_IRQ_MASK, ASD_DESC_IRQ_OFF))
45 (ASD_DESC_GET((d)->cfg, ASD_DESC_EOD_MASK, ASD_DESC_EOD_OFF))
47 (ASD_DESC_SET((d)->cfg, v, ASD_DESC_EOD_MASK, ASD_DESC_EOD_OFF))
52 (ASD_DESC_GET((d)->cfg, ASD_DESC_LOOP_MASK, ASD_DESC_LOOP_OFF))
54 (ASD_DESC_SET((d)->cfg, v, ASD_DESC_LOOP_MASK, ASD_DESC_LOOP_OFF))
59 (ASD_DESC_GET((d)->cfg, ASD_DESC_MODE_MASK, ASD_DESC_MODE_OFF))
[all …]
/trusted-firmware-a-3.6.0-3.5.0/drivers/brcm/emmc/
Demmc_pboot_hal_memory_drv.c134 p_sdhandle->device->cfg.blockSize)) { in bcm_emmc_init()
330 const size_t blockSize = p_sdhandle->device->cfg.blockSize; in sdio_read()
481 (uint32_t)(mem_addr / p_sdhandle->device->cfg.blockSize); in sdio_write()
484 blockAddr * p_sdhandle->device->cfg.blockSize); in sdio_write()
487 ((uint32_t)mem_addr / p_sdhandle->device->cfg.blockSize) * in sdio_write()
488 p_sdhandle->device->cfg.blockSize; in sdio_write()
499 blockAddr, p_sdhandle->device->cfg.blockSize)) { in sdio_write()
502 (p_sdhandle->device->cfg.blockSize - offset)) { in sdio_write()
506 p_sdhandle->device->cfg.blockSize - offset; in sdio_write()
519 p_sdhandle->device->cfg.blockSize)) { in sdio_write()
[all …]
Demmc_chal_sd.c275 handle->cfg.voltage = 0; in chal_sd_init()
279 handle->cfg.voltage |= SD_VDD_WINDOW_3_3_TO_3_4; in chal_sd_init()
282 handle->cfg.voltage |= SD_VDD_WINDOW_3_0_TO_3_1; in chal_sd_init()
285 handle->cfg.voltage |= SD_VDD_WINDOW_1_8_TO_1_9; in chal_sd_init()
368 handle->cfg.mode = SD_PIO_MODE; /* set to PIO mode first for init */ in chal_sd_start()
369 handle->cfg.dma = SD_DMA_OFF; in chal_sd_start()
381 handle->cfg.mode = mode; in chal_sd_start()
481 handle->cfg.dma = mode; in chal_sd_set_dma()
485 val |= handle->cfg.dma - 1; in chal_sd_set_dma()
491 handle->cfg.dma = 0; in chal_sd_set_dma()
[all …]
Demmc_csl_sdcmd.c239 handle->device->cfg.blockSize = handle->card->maxRdBlkLen; in sd_cmd9()
293 if (ntry > handle->device->cfg.retryLimit) { in sd_cmd16()
295 handle->device->cfg.retryLimit); in sd_cmd16()
334 if (ntry > handle->device->cfg.retryLimit) { in sd_cmd17()
336 handle->device->cfg.retryLimit); in sd_cmd17()
388 if (ntry > handle->device->cfg.retryLimit) { in sd_cmd18()
390 handle->device->cfg.retryLimit); in sd_cmd18()
442 if (ntry > handle->device->cfg.retryLimit) { in card_sts_resp()
444 handle->device->cfg.retryLimit); in card_sts_resp()
559 if (ntry > handle->device->cfg.retryLimit) { in sd_cmd24()
[all …]
Demmc_csl_sdcard.c211 handle->device->cfg.wfe_retry); in abort_err()
258 if (handle->device->cfg.dma == SD_DMA_OFF) { in process_data_xfer()
268 handle->device->cfg.wfe_retry); in process_data_xfer()
281 if (handle->device->cfg.dma == SD_DMA_OFF) { in process_data_xfer()
297 handle->device->cfg.wfe_retry); in process_data_xfer()
479 handle->device->cfg.blockSize = 512; in init_mmc_card()
530 if ((length / handle->device->cfg.blockSize) > 1) { in xfer_data()
546 handle->device->cfg.blockSize, base); in xfer_data()
551 handle->device->cfg.blockSize, base); in xfer_data()
659 blockSize = handle->device->cfg.blockSize; in write_buffer()
[all …]
/trusted-firmware-a-3.6.0-3.5.0/plat/marvell/armada/a8k/a80x0/board/
Dmarvell_plat_config.c168 .cfg.gpio.pin_count = 1,
169 .cfg.gpio.info = {{0, 35} },
170 .cfg.gpio.step_count = 7,
171 .cfg.gpio.seq = {1, 0, 1, 0, 1, 0, 1},
172 .cfg.gpio.delay_ms = 10,
/trusted-firmware-a-3.6.0-3.5.0/plat/imx/imx8m/ddr/
Ddram.c158 struct dram_cfg_param *cfg = timing->ddrphy_cfg; in dram_phy_init() local
162 cfg = timing->ddrphy_cfg; in dram_phy_init()
164 dwc_ddrphy_apb_wr(cfg->reg, cfg->val); in dram_phy_init()
165 cfg++; in dram_phy_init()
169 cfg = timing->ddrphy_trained_csr; in dram_phy_init()
171 dwc_ddrphy_apb_wr(cfg->reg, cfg->val); in dram_phy_init()
172 cfg++; in dram_phy_init()
176 cfg = timing->ddrphy_pie; in dram_phy_init()
178 dwc_ddrphy_apb_wr(cfg->reg, cfg->val); in dram_phy_init()
179 cfg++; in dram_phy_init()
/trusted-firmware-a-3.6.0-3.5.0/plat/brcm/board/stingray/src/
Diommu.c284 struct arm_smmu_cfg cfg[NUM_OF_SMRS]; member
308 uint32_t idx = smmu->cfg[index].cbndx; in arm_smmu_smr_cfg()
321 uint32_t idx = smmu->cfg[index].cbndx; in arm_smmu_s2cr_cfg()
446 smmu->cfg[idx].cbndx = context_bank_index; in arm_smmu_create_identity_map()
447 smmu->cfg[idx].cbar = STG1_WITH_STG2_BYPASS << CBAR_TYPE_SHIFT; in arm_smmu_create_identity_map()
458 ARM_SMMU_GR1_CBA2R(smmu->cfg[idx].cbndx)), in arm_smmu_create_identity_map()
461 reg = smmu->cfg[idx].cbar; in arm_smmu_create_identity_map()
466 ARM_SMMU_GR1_CBAR(smmu->cfg[idx].cbndx)), in arm_smmu_create_identity_map()
485 ARM_SMMU_CB(smmu, smmu->cfg[idx].cbndx) + in arm_smmu_create_identity_map()
489 ARM_SMMU_CB(smmu, smmu->cfg[idx].cbndx) + in arm_smmu_create_identity_map()
[all …]
/trusted-firmware-a-3.6.0-3.5.0/include/common/
Dinterrupt_props.h13 #define INTR_PROP_DESC(num, pri, grp, cfg) \ argument
18 .intr_cfg = (cfg), \
/trusted-firmware-a-3.6.0-3.5.0/include/drivers/marvell/
Dthermal.h22 int (*ptr_tsen_probe)(struct tsen_config *cfg);
23 int (*ptr_tsen_read)(struct tsen_config *cfg, int *temp);
/trusted-firmware-a-3.6.0-3.5.0/drivers/st/bsec/
Dbsec2.c244 uint32_t bsec_set_config(struct bsec_config *cfg) in bsec_set_config() argument
253 value = ((((uint32_t)cfg->freq << BSEC_CONF_FRQ_SHIFT) & in bsec_set_config()
255 (((uint32_t)cfg->pulse_width << BSEC_CONF_PRG_WIDTH_SHIFT) & in bsec_set_config()
257 (((uint32_t)cfg->tread << BSEC_CONF_TREAD_SHIFT) & in bsec_set_config()
266 result = bsec_power_safmem((bool)cfg->power & in bsec_set_config()
272 value = ((((uint32_t)cfg->upper_otp_lock << UPPER_OTP_LOCK_SHIFT) & in bsec_set_config()
274 (((uint32_t)cfg->den_lock << DENREG_LOCK_SHIFT) & in bsec_set_config()
276 (((uint32_t)cfg->prog_lock << GPLOCK_LOCK_SHIFT) & in bsec_set_config()
293 uint32_t bsec_get_config(struct bsec_config *cfg) in bsec_get_config() argument
297 if (cfg == NULL) { in bsec_get_config()
[all …]
/trusted-firmware-a-3.6.0-3.5.0/plat/marvell/armada/a8k/common/
Dplat_pm.c510 assert((pm_cfg->cfg.gpio.pin_count < PMIC_GPIO_MAX_NUMBER) && in plat_marvell_power_off_gpio()
511 (pm_cfg->cfg.gpio.step_count < PMIC_GPIO_MAX_TOGGLE_STEP)); in plat_marvell_power_off_gpio()
514 for (gpio = 0; gpio < pm_cfg->cfg.gpio.pin_count; gpio++) { in plat_marvell_power_off_gpio()
515 info = &pm_cfg->cfg.gpio.info[gpio]; in plat_marvell_power_off_gpio()
532 mdelay(pm_cfg->cfg.gpio.delay_ms); in plat_marvell_power_off_gpio()
537 for (idx = 0; idx < pm_cfg->cfg.gpio.step_count; idx++) { in plat_marvell_power_off_gpio()
538 tog_bits = pm_cfg->cfg.gpio.seq[idx]; in plat_marvell_power_off_gpio()
543 info = &pm_cfg->cfg.gpio.info[0]; in plat_marvell_power_off_gpio()
548 for (gpio = 0; gpio < pm_cfg->cfg.gpio.pin_count; gpio++) { in plat_marvell_power_off_gpio()
549 shift = pm_cfg->cfg.gpio.info[gpio].gpio_index % 32; in plat_marvell_power_off_gpio()
[all …]
/trusted-firmware-a-3.6.0-3.5.0/drivers/st/clk/
Dclk-stm32-core.c162 struct clk_gate_cfg *cfg = clk->clock_cfg; in clk_gate_enable() local
164 mmio_setbits_32(priv->base + cfg->offset, BIT(cfg->bit_idx)); in clk_gate_enable()
172 struct clk_gate_cfg *cfg = clk->clock_cfg; in clk_gate_disable() local
174 mmio_clrbits_32(priv->base + cfg->offset, BIT(cfg->bit_idx)); in clk_gate_disable()
180 struct clk_gate_cfg *cfg = clk->clock_cfg; in clk_gate_is_enabled() local
182 return ((mmio_read_32(priv->base + cfg->offset) & BIT(cfg->bit_idx)) != 0U); in clk_gate_is_enabled()
825 struct clk_stm32_gate_cfg *cfg = clk->clock_cfg; in clk_stm32_gate_enable() local
826 const struct gate_cfg *gate = &priv->gates[cfg->id]; in clk_stm32_gate_enable()
842 struct clk_stm32_gate_cfg *cfg = clk->clock_cfg; in clk_stm32_gate_disable() local
843 const struct gate_cfg *gate = &priv->gates[cfg->id]; in clk_stm32_gate_disable()
[all …]
/trusted-firmware-a-3.6.0-3.5.0/plat/mediatek/drivers/cpu_pm/cpcv3_2/
Dmt_cpu_pm_cpc.c148 static void mtk_cpc_config(unsigned int cfg, unsigned int data) in mtk_cpc_config() argument
150 switch (cfg) { in mtk_cpc_config()
182 static unsigned int mtk_cpc_read_config(unsigned int cfg) in mtk_cpc_read_config() argument
186 switch (cfg) { in mtk_cpc_read_config()
/trusted-firmware-a-3.6.0-3.5.0/plat/mediatek/mt8186/drivers/mcdi/
Dmt_cpu_pm_cpc.c162 static void mtk_cpc_config(uint32_t cfg, uint32_t data) in mtk_cpc_config() argument
167 switch (cfg) { in mtk_cpc_config()
205 static uint32_t mtk_cpc_read_config(uint32_t cfg) in mtk_cpc_read_config() argument
209 switch (cfg) { in mtk_cpc_read_config()
/trusted-firmware-a-3.6.0-3.5.0/plat/mediatek/mt8192/drivers/mcdi/
Dmt_cpu_pm_cpc.c162 static void mtk_cpc_config(uint32_t cfg, uint32_t data) in mtk_cpc_config() argument
167 switch (cfg) { in mtk_cpc_config()
205 static uint32_t mtk_cpc_read_config(uint32_t cfg) in mtk_cpc_read_config() argument
209 switch (cfg) { in mtk_cpc_read_config()
/trusted-firmware-a-3.6.0-3.5.0/plat/mediatek/mt8195/drivers/mcdi/
Dmt_cpu_pm_cpc.c162 static void mtk_cpc_config(uint32_t cfg, uint32_t data) in mtk_cpc_config() argument
167 switch (cfg) { in mtk_cpc_config()
205 static uint32_t mtk_cpc_read_config(uint32_t cfg) in mtk_cpc_read_config() argument
209 switch (cfg) { in mtk_cpc_read_config()
/trusted-firmware-a-3.6.0-3.5.0/drivers/mtd/nand/
Dspi_nand.c67 uint8_t cfg = spinand_dev.cfg_cache; in spi_nand_update_cfg() local
69 cfg &= ~mask; in spi_nand_update_cfg()
70 cfg |= val; in spi_nand_update_cfg()
72 if (cfg == spinand_dev.cfg_cache) { in spi_nand_update_cfg()
76 ret = spi_nand_write_reg(SPI_NAND_REG_CFG, cfg); in spi_nand_update_cfg()
78 spinand_dev.cfg_cache = cfg; in spi_nand_update_cfg()
/trusted-firmware-a-3.6.0-3.5.0/drivers/arm/gic/v3/
Dgicrv3_helpers.c130 void gicr_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg) in gicr_set_icfgr() argument
138 (cfg & GIC_CFG_MASK) << bit_shift); in gicr_set_icfgr()
/trusted-firmware-a-3.6.0-3.5.0/include/drivers/st/
Dbsec.h96 uint32_t bsec_set_config(struct bsec_config *cfg);
97 uint32_t bsec_get_config(struct bsec_config *cfg);
/trusted-firmware-a-3.6.0-3.5.0/plat/nvidia/tegra/soc/t210/
Dplat_psci_handlers.c202 uint32_t cfg; in tegra_soc_pwr_domain_suspend() local
234 cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG); in tegra_soc_pwr_domain_suspend()
235 if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) { in tegra_soc_pwr_domain_suspend()
436 uint32_t cfg; in tegra_soc_pwr_domain_on_finish() local
513 cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG); in tegra_soc_pwr_domain_on_finish()
514 if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) { in tegra_soc_pwr_domain_on_finish()
/trusted-firmware-a-3.6.0-3.5.0/plat/marvell/octeontx/otx2/t91/t9130/
Dplatform.mk13 DOIMAGE_SEC := tools/doimage/secure/sec_img_7K.cfg
/trusted-firmware-a-3.6.0-3.5.0/plat/marvell/armada/a8k/a70x0/
Dplatform.mk13 DOIMAGE_SEC := tools/doimage/secure/sec_img_7K.cfg
/trusted-firmware-a-3.6.0-3.5.0/plat/marvell/armada/a8k/a70x0_amc/
Dplatform.mk13 DOIMAGE_SEC := tools/doimage/secure/sec_img_7K.cfg

123