| /trusted-firmware-a-3.6.0-3.5.0/drivers/st/gpio/ |
| D | stm32_gpio.c | 28 static void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t type,
36 static int ckeck_gpio_bank(void *fdt, uint32_t bank, int pinctrl_node) in ckeck_gpio_bank() argument
39 uint32_t bank_offset = stm32_get_gpio_bank_offset(bank); in ckeck_gpio_bank()
102 uint32_t bank; in dt_set_gpio_config() local
114 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; in dt_set_gpio_config()
156 bank_node = ckeck_gpio_bank(fdt, bank, pinctrl_node); in dt_set_gpio_config()
168 assert((unsigned long)clk == stm32_get_gpio_bank_clock(bank)); in dt_set_gpio_config()
170 set_gpio(bank, pin, mode, type, speed, pull, od, alternate, status); in dt_set_gpio_config()
225 static void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t type, in set_gpio() argument
229 uintptr_t base = stm32_get_gpio_bank_base(bank); in set_gpio()
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/plat/st/stm32mp1/ |
| D | stm32mp1_private.c | 115 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) in stm32_get_gpio_bank_base() argument
118 assert((GPIO_BANK_A == 0) && (bank <= GPIO_BANK_I)); in stm32_get_gpio_bank_base()
121 if (bank == GPIO_BANK_Z) { in stm32_get_gpio_bank_base()
125 assert((GPIO_BANK_A == 0) && (bank <= GPIO_BANK_K)); in stm32_get_gpio_bank_base()
128 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); in stm32_get_gpio_bank_base()
131 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) in stm32_get_gpio_bank_offset() argument
134 assert((GPIO_BANK_A == 0) && (bank <= GPIO_BANK_I)); in stm32_get_gpio_bank_offset()
137 if (bank == GPIO_BANK_Z) { in stm32_get_gpio_bank_offset()
141 assert((GPIO_BANK_A == 0) && (bank <= GPIO_BANK_K)); in stm32_get_gpio_bank_offset()
144 return bank * GPIO_BANK_OFFSET; in stm32_get_gpio_bank_offset()
[all …]
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| D | stm32mp1_shared_resources.c | 111 static unsigned int get_gpio_nbpin(unsigned int bank) in get_gpio_nbpin() argument
113 if (bank != GPIO_BANK_Z) { in get_gpio_nbpin()
114 int count = fdt_get_gpio_bank_pin_count(bank); in get_gpio_nbpin()
313 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin) in stm32mp_register_secure_gpio() argument
315 switch (bank) { in stm32mp_register_secure_gpio()
320 ERROR("GPIO bank %u cannot be secured\n", bank); in stm32mp_register_secure_gpio()
325 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin) in stm32mp_register_non_secure_gpio() argument
327 switch (bank) { in stm32mp_register_non_secure_gpio()
336 static bool stm32mp_gpio_bank_is_non_secure(unsigned int bank) in stm32mp_gpio_bank_is_non_secure() argument
343 if (bank != GPIO_BANK_Z) { in stm32mp_gpio_bank_is_non_secure()
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| /trusted-firmware-a-3.6.0-3.5.0/plat/st/common/include/ |
| D | stm32mp_shared_resources.h | 33 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin);
34 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin);
48 static inline void stm32mp_register_secure_gpio(unsigned int bank __unused, in stm32mp_register_secure_gpio()
53 static inline void stm32mp_register_non_secure_gpio(unsigned int bank __unused, in stm32mp_register_non_secure_gpio()
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| D | stm32mp_common.h | 89 uintptr_t stm32_get_gpio_bank_base(unsigned int bank);
90 unsigned long stm32_get_gpio_bank_clock(unsigned int bank);
91 uint32_t stm32_get_gpio_bank_offset(unsigned int bank);
92 bool stm32_gpio_is_secure_at_reset(unsigned int bank);
95 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank);
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| D | stm32mp_dt.h | 44 int fdt_get_gpio_bank_pin_count(unsigned int bank);
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| /trusted-firmware-a-3.6.0-3.5.0/drivers/st/bsec/ |
| D | bsec2.c | 190 uint32_t bank = otp_bank_offset(otp); in bsec_check_error() local
192 if ((mmio_read_32(bsec_base + BSEC_ERROR_OFF + bank) & bit) != 0U) { in bsec_check_error()
200 if ((mmio_read_32(bsec_base + BSEC_DISTURBED_OFF + bank) & bit) != 0U) { in bsec_check_error()
683 uint32_t bank = otp_bank_offset(otp); in bsec_set_sr_lock() local
695 mmio_write_32(bsec_base + BSEC_SRLOCK_OFF + bank, otp_mask); in bsec_set_sr_lock()
709 uint32_t bank = otp_bank_offset(otp); in bsec_read_sr_lock() local
717 bank_value = mmio_read_32(bsec_base + BSEC_SRLOCK_OFF + bank); in bsec_read_sr_lock()
731 uint32_t bank = otp_bank_offset(otp); in bsec_set_sw_lock() local
743 mmio_write_32(bsec_base + BSEC_SWLOCK_OFF + bank, otp_mask); in bsec_set_sw_lock()
757 uint32_t bank = otp_bank_offset(otp); in bsec_read_sw_lock() local
[all …]
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| /trusted-firmware-a-3.6.0-3.5.0/include/drivers/st/ |
| D | stm32_gpio.h | 59 void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure);
60 void set_gpio_reset_cfg(uint32_t bank, uint32_t pin);
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| /trusted-firmware-a-3.6.0-3.5.0/plat/rockchip/rk3399/drivers/gpio/ |
| D | rk3399_gpio.c | 181 uint32_t bank = GET_GPIO_BANK(gpio); in get_pull() local
188 assert(bank <= info->max_bank); in get_pull()
191 val = (mmio_read_32(info->pull_base + 4 * bank) >> (id * 2)) & GPIO_P_MASK; in get_pull()
194 return pull_type_hw2sw[info->pull_enc[bank]][val]; in get_pull()
200 uint32_t bank = GET_GPIO_BANK(gpio); in set_pull() local
207 assert(bank <= info->max_bank); in set_pull()
209 uint8_t val = pull_type_sw2hw[info->pull_enc[bank]][pull]; in set_pull()
215 info->pull_base + 4 * bank, in set_pull()
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| /trusted-firmware-a-3.6.0-3.5.0/drivers/st/fmc/ |
| D | stm32_fmc2_nand.c | 799 uint8_t bank; in stm32_fmc2_init() local
830 bank = fdt32_to_cpu(*cuint); in stm32_fmc2_init()
831 if ((bank >= MAX_BANK) || ((bank_assigned & BIT(bank)) != 0U)) { in stm32_fmc2_init()
834 bank_assigned |= BIT(bank); in stm32_fmc2_init()
835 bank_address[bank] = fdt32_to_cpu(*(cuint + 2)); in stm32_fmc2_init()
861 bank = fdt32_to_cpu(*cuint); in stm32_fmc2_init()
862 if (bank >= MAX_BANK) { in stm32_fmc2_init()
866 bank_address[bank]; in stm32_fmc2_init()
868 bank = fdt32_to_cpu(*(cuint + 3)); in stm32_fmc2_init()
869 if (bank >= MAX_BANK) { in stm32_fmc2_init()
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| /trusted-firmware-a-3.6.0-3.5.0/drivers/renesas/common/ddr/ddr_b/ |
| D | boot_init_dram_regdef.h | 24 #define DBMEMCONF_REG(d3, row, bank, col, dw) \ argument
25 (((d3) << 30) | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
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| /trusted-firmware-a-3.6.0-3.5.0/fdts/ |
| D | stm32mp151.dtsi | 552 st,bank-name = "GPIOA";
563 st,bank-name = "GPIOB";
574 st,bank-name = "GPIOC";
585 st,bank-name = "GPIOD";
596 st,bank-name = "GPIOE";
607 st,bank-name = "GPIOF";
618 st,bank-name = "GPIOG";
629 st,bank-name = "GPIOH";
640 st,bank-name = "GPIOI";
651 st,bank-name = "GPIOJ";
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| D | stm32mp131.dtsi | 482 st,bank-name = "GPIOA";
494 st,bank-name = "GPIOB";
506 st,bank-name = "GPIOC";
518 st,bank-name = "GPIOD";
530 st,bank-name = "GPIOE";
542 st,bank-name = "GPIOF";
554 st,bank-name = "GPIOG";
566 st,bank-name = "GPIOH";
578 st,bank-name = "GPIOI";
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| D | corstone700_fvp.dts | 23 bank-width = <4>;
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| D | n1sdp-single-chip.dts | 23 * In the first 2GB of DRAM bank the top 16MB are reserved by firmware as secure memory.
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| D | morello-fvp.dts | 80 /* The first bank of memory, memory map is actually provided by UEFI. */
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| D | rtsm_ve-motherboard.dtsi | 102 bank-width = <4>;
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| D | morello-soc.dts | 61 /* The first bank of memory, memory map is actually provided by UEFI. */
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| /trusted-firmware-a-3.6.0-3.5.0/plat/st/common/ |
| D | stm32mp_dt.c | 371 int fdt_get_gpio_bank_pin_count(unsigned int bank) in fdt_get_gpio_bank_pin_count() argument
377 pinctrl_node = stm32_get_gpio_bank_pinctrl_node(fdt, bank); in fdt_get_gpio_bank_pin_count()
382 bank_offset = stm32_get_gpio_bank_offset(bank); in fdt_get_gpio_bank_pin_count()
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| /trusted-firmware-a-3.6.0-3.5.0/plat/intel/soc/agilex/soc/ |
| D | agilex_memory_controller.c | 175 uint32_t data, dram_addr_order, ddr_conf, bank, row, col, in configure_ddr_sched_ctrl_regs() local
191 bank = IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(data) + in configure_ddr_sched_ctrl_regs()
194 ddr_conf = match_ddr_conf(DDR_CONFIG(dram_addr_order, bank, col, row)); in configure_ddr_sched_ctrl_regs()
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| /trusted-firmware-a-3.6.0-3.5.0/plat/intel/soc/stratix10/soc/ |
| D | s10_memory_controller.c | 204 uint32_t data, dram_addr_order, ddr_conf, bank, row, col, in configure_ddr_sched_ctrl_regs() local
220 bank = IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(data) + in configure_ddr_sched_ctrl_regs()
223 ddr_conf = match_ddr_conf(DDR_CONFIG(dram_addr_order, bank, col, row)); in configure_ddr_sched_ctrl_regs()
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| /trusted-firmware-a-3.6.0-3.5.0/docs/components/ |
| D | firmware-update.rst | 49 An active bank stores running firmware, whereas an update bank contains
52 Once Firmwares are updated in the update bank of the non-volatile
53 storage, then ``Update Agent`` marks the update bank as the active bank,
67 By default, the platform uses the active bank of non-volatile storage to boot
80 If the platform fails to boot from active bank due to any reasons such
85 bank.
88 bank (e.g. due to ageing effect of non-volatile storage) then the platform can
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| D | rmm-el3-comms-spec.rst | 575 NS DRAM Bank structure contains information about each Non-secure DRAM bank:
582 | size | 8 | uint64_t | Size of bank in bytes |
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| /trusted-firmware-a-3.6.0-3.5.0/docs/plat/nxp/ |
| D | nxp-layerscape.rst | 209 - DRAM0 Bank: Maximum size of this bank is fixed to 2GB, DRAM0 size is defined in platform_def.h i…
342 Notes: ls1028ardb has no flexspi-Nor Alt Bank, so use "sf probe 0:0" for current bank.
360 -- Then reset to alternate bank to boot up ATF.
418 -- Then reset to alternate bank to boot up ATF.
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| /trusted-firmware-a-3.6.0-3.5.0/plat/intel/soc/common/drivers/qspi/ |
| D | cadence_qspi.c | 225 int cad_qspi_device_bank_select(uint32_t bank) in cad_qspi_device_bank_select() argument
234 0, 1, &bank); in cad_qspi_device_bank_select()
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