1 /* 2 * Copyright (c) 2016 - 2020, Broadcom 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CSL_SD_PROT_H 8 #define CSL_SD_PROT_H 9 10 #define SD_CARD_UNKNOWN 0 /* bad type or unrecognized */ 11 #define SD_CARD_SD 1 /* IO only card */ 12 #define SD_CARD_SDIO 2 /* memory only card */ 13 #define SD_CARD_COMBO 3 /* IO and memory combo card */ 14 #define SD_CARD_MMC 4 /* memory only card */ 15 #define SD_CARD_CEATA 5 /* IO and memory combo card */ 16 17 #define SD_IO_FIXED_ADDRESS 0 /* fix Address */ 18 #define SD_IO_INCREMENT_ADDRESS 1 19 20 #define SD_HIGH_CAPACITY_CARD 0x40000000 21 22 #define MMC_CMD_IDLE_RESET_ARG 0xF0F0F0F0 23 24 /* Supported operating voltages are 3.2-3.3 and 3.3-3.4 */ 25 #define MMC_OCR_OP_VOLT 0x00300000 26 /* Enable sector access mode */ 27 #define MMC_OCR_SECTOR_ACCESS_MODE 0x40000000 28 29 /* command index */ 30 #define SD_CMD_GO_IDLE_STATE 0 /* mandatory for SDIO */ 31 #define SD_CMD_SEND_OPCOND 1 32 #define SD_CMD_ALL_SEND_CID 2 33 #define SD_CMD_MMC_SET_RCA 3 34 #define SD_CMD_MMC_SET_DSR 4 35 #define SD_CMD_IO_SEND_OP_COND 5 /* mandatory for SDIO */ 36 #define SD_ACMD_SET_BUS_WIDTH 6 37 #define SD_CMD_SWITCH_FUNC 6 38 #define SD_CMD_SELECT_DESELECT_CARD 7 39 #define SD_CMD_READ_EXT_CSD 8 40 #define SD_CMD_SEND_CSD 9 41 #define SD_CMD_SEND_CID 10 42 #define SD_CMD_STOP_TRANSMISSION 12 43 #define SD_CMD_SEND_STATUS 13 44 #define SD_ACMD_SD_STATUS 13 45 #define SD_CMD_GO_INACTIVE_STATE 15 46 #define SD_CMD_SET_BLOCKLEN 16 47 #define SD_CMD_READ_SINGLE_BLOCK 17 48 #define SD_CMD_READ_MULTIPLE_BLOCK 18 49 #define SD_CMD_WRITE_BLOCK 24 50 #define SD_CMD_WRITE_MULTIPLE_BLOCK 25 51 #define SD_CMD_PROGRAM_CSD 27 52 #define SD_CMD_SET_WRITE_PROT 28 53 #define SD_CMD_CLR_WRITE_PROT 29 54 #define SD_CMD_SEND_WRITE_PROT 30 55 #define SD_CMD_ERASE_WR_BLK_START 32 56 #define SD_CMD_ERASE_WR_BLK_END 33 57 #define SD_CMD_ERASE_GROUP_START 35 58 #define SD_CMD_ERASE_GROUP_END 36 59 #define SD_CMD_ERASE 38 60 #define SD_CMD_LOCK_UNLOCK 42 61 #define SD_CMD_IO_RW_DIRECT 52 /* mandatory for SDIO */ 62 #define SD_CMD_IO_RW_EXTENDED 53 /* mandatory for SDIO */ 63 #define SD_CMD_APP_CMD 55 64 #define SD_CMD_GEN_CMD 56 65 #define SD_CMD_READ_OCR 58 66 #define SD_CMD_CRC_ON_OFF 59 /* mandatory for SDIO */ 67 #define SD_ACMD_SEND_NUM_WR_BLOCKS 22 68 #define SD_ACMD_SET_WR_BLOCK_ERASE_CNT 23 69 #define SD_ACMD_SD_SEND_OP_COND 41 70 #define SD_ACMD_SET_CLR_CARD_DETECT 42 71 #define SD_ACMD_SEND_SCR 51 72 73 /* response parameters */ 74 #define SD_RSP_NO_NONE 0 75 #define SD_RSP_NO_1 1 76 #define SD_RSP_NO_2 2 77 #define SD_RSP_NO_3 3 78 #define SD_RSP_NO_4 4 79 #define SD_RSP_NO_5 5 80 #define SD_RSP_NO_6 6 81 82 /* Modified R6 response (to CMD3) */ 83 #define SD_RSP_MR6_COM_CRC_ERROR 0x8000 84 #define SD_RSP_MR6_ILLEGAL_COMMAND 0x4000 85 #define SD_RSP_MR6_ERROR 0x2000 86 87 /* Modified R1 in R4 Response (to CMD5) */ 88 #define SD_RSP_MR1_SBIT 0x80 89 #define SD_RSP_MR1_PARAMETER_ERROR 0x40 90 #define SD_RSP_MR1_RFU5 0x20 91 #define SD_RSP_MR1_FUNC_NUM_ERROR 0x10 92 #define SD_RSP_MR1_COM_CRC_ERROR 0x80 93 #define SD_RSP_MR1_ILLEGAL_COMMAND 0x40 94 #define SD_RSP_MR1_RFU1 0x20 95 #define SD_RSP_MR1_IDLE_STATE 0x01 96 97 /* R5 response (to CMD52 and CMD53) */ 98 #define SD_RSP_R5_COM_CRC_ERROR 0x80 99 #define SD_RSP_R5_ILLEGAL_COMMAND 0x40 100 #define SD_RSP_R5_IO_CURRENTSTATE1 0x20 101 #define SD_RSP_R5_IO_CURRENTSTATE0 0x10 102 #define SD_RSP_R5_ERROR 0x80 103 #define SD_RSP_R5_RFU 0x40 104 #define SD_RSP_R5_FUNC_NUM_ERROR 0x20 105 #define SD_RSP_R5_OUT_OF_RANGE 0x01 106 107 /* argument for SD_CMD_IO_RW_DIRECT and SD_CMD_IO_RW_EXTENDED */ 108 #define SD_OP_READ 0 /* Read_Write */ 109 #define SD_OP_WRITE 1 /* Read_Write */ 110 111 #define SD_RW_NORMAL 0 /* no RAW */ 112 #define SD_RW_RAW 1 /* RAW */ 113 114 #define SD_BYTE_MODE 0 /* Byte Mode */ 115 #define SD_BLOCK_MODE 1 /* BlockMode */ 116 117 #define SD_FIXED_ADDRESS 0 /* fix Address */ 118 #define SD_INCREMENT_ADDRESS 1 /* IncrementAddress */ 119 120 #define SD_CMD5_ARG_IO_OCR_MASK 0x00FFFFFF 121 #define SD_CMD5_ARG_IO_OCR_SHIFT 0 122 #define SD_CMD55_ARG_RCA_SHIFT 16 123 #define SD_CMD59_ARG_CRC_OPTION_MASK 0x01 124 #define SD_CMD59_ARG_CRC_OPTION_SHIFT 0 125 126 /* SD_CMD_IO_RW_DIRECT Argument */ 127 #define SdioIoRWDirectArg(rw, raw, func, addr, data) \ 128 (((rw & 1) << 31) | ((func & 0x7) << 28) | \ 129 ((raw & 1) << 27) | ((addr & 0x1FFFF) << 9) | \ 130 (data & 0xFF)) 131 132 /* build SD_CMD_IO_RW_EXTENDED Argument */ 133 #define SdioIoRWExtArg(rw, blk, func, addr, inc_addr, count) \ 134 (((rw & 1) << 31) | ((func & 0x7) << 28) | \ 135 ((blk & 1) << 27) | ((inc_addr & 1) << 26) | \ 136 ((addr & 0x1FFFF) << 9) | (count & 0x1FF)) 137 138 /* 139 * The Common I/O area shall be implemented on all SDIO cards and 140 * is accessed the the host via I/O reads and writes to function 0, 141 * the registers within the CIA are provided to enable/disable 142 * the operationo fthe i/o function. 143 */ 144 145 /* cccr_sdio_rev */ 146 #define SDIO_REV_SDIOID_MASK 0xf0 /* SDIO spec revision number */ 147 #define SDIO_REV_CCCRID_MASK 0x0f /* CCCR format version number */ 148 149 /* sd_rev */ 150 #define SDIO_REV_PHY_MASK 0x0f /* SD format version number */ 151 #define SDIO_FUNC_ENABLE_1 0x02 /* function 1 I/O enable */ 152 #define SDIO_FUNC_READY_1 0x02 /* function 1 I/O ready */ 153 #define SDIO_INTR_CTL_FUNC1_EN 0x2 /* interrupt enable for function 1 */ 154 #define SDIO_INTR_CTL_MASTER_EN 0x1 /* interrupt enable master */ 155 #define SDIO_INTR_STATUS_FUNC1 0x2 /* interrupt pending for function 1 */ 156 #define SDIO_IO_ABORT_RESET_ALL 0x08 /* I/O card reset */ 157 #define SDIO_IO_ABORT_FUNC_MASK 0x07 /* abort selection: function x */ 158 #define SDIO_BUS_CARD_DETECT_DIS 0x80 /* Card Detect disable */ 159 #define SDIO_BUS_SPI_CONT_INTR_CAP 0x40 /* support continuous SPI interrupt */ 160 #define SDIO_BUS_SPI_CONT_INTR_EN 0x20 /* continuous SPI interrupt enable */ 161 #define SDIO_BUS_DATA_WIDTH_MASK 0x03 /* bus width mask */ 162 #define SDIO_BUS_DATA_WIDTH_4BIT 0x02 /* bus width 4-bit mode */ 163 #define SDIO_BUS_DATA_WIDTH_1BIT 0x00 /* bus width 1-bit mode */ 164 165 /* capability */ 166 #define SDIO_CAP_4BLS 0x80 /* 4-bit support for low speed card */ 167 #define SDIO_CAP_LSC 0x40 /* low speed card */ 168 #define SDIO_CAP_E4MI 0x20 /* enable int between block in 4-bit mode */ 169 #define SDIO_CAP_S4MI 0x10 /* support int between block in 4-bit mode */ 170 #define SDIO_CAP_SBS 0x08 /* support suspend/resume */ 171 #define SDIO_CAP_SRW 0x04 /* support read wait */ 172 #define SDIO_CAP_SMB 0x02 /* support multi-block transfer */ 173 #define SDIO_CAP_SDC 0x01 /* Support Direct cmd during multi-uint8 transfer */ 174 175 /* CIA FBR1 registers */ 176 #define SDIO_FUNC1_INFO 0x100 /* basic info for function 1 */ 177 #define SDIO_FUNC1_EXT 0x101 /* extension of standard I/O device */ 178 #define SDIO_CIS_FUNC1_BASE_LOW 0x109 /* function 1 cis address bit 0-7 */ 179 #define SDIO_CIS_FUNC1_BASE_MID 0x10A /* function 1 cis address bit 8-15 */ 180 #define SDIO_CIS_FUNC1_BASE_HIGH 0x10B /* function 1 cis address bit 16 */ 181 #define SDIO_CSA_BASE_LOW 0x10C /* CSA base address uint8_t 0 */ 182 #define SDIO_CSA_BASE_MID 0x10D /* CSA base address uint8_t 1 */ 183 #define SDIO_CSA_BASE_HIGH 0x10E /* CSA base address uint8_t 2 */ 184 #define SDIO_CSA_DATA_OFFSET 0x10F /* CSA data register */ 185 #define SDIO_IO_BLK_SIZE_LOW 0x110 /* I/O block size uint8_t 0 */ 186 #define SDIO_IO_BLK_SIZE_HIGH 0x111 /* I/O block size uint8_t 1 */ 187 188 /* SD_SDIO_FUNC1_INFO bits */ 189 #define SDIO_FUNC1_INFO_DIC 0x0f /* device interface code */ 190 #define SDIO_FUNC1_INFO_CSA 0x40 /* CSA support flag */ 191 #define SDIO_FUNC1_INFO_CSA_EN 0x80 /* CSA enabled */ 192 193 /* SD_SDIO_FUNC1_EXT bits */ 194 #define SDIO_FUNC1_EXT_SHP 0x03 /* support high power */ 195 #define SDIO_FUNC1_EXT_EHP 0x04 /* enable high power */ 196 197 /* devctr */ 198 /* I/O device interface code */ 199 #define SDIO_DEVCTR_DEVINTER 0x0f 200 /* support CSA */ 201 #define SDIO_DEVCTR_CSA_SUP 0x40 202 /* enable CSA */ 203 #define SDIO_DEVCTR_CSA_EN 0x80 204 205 /* ext_dev */ 206 /* supports high-power mask */ 207 #define SDIO_HIGHPWR_SUPPORT_M 0x3 208 /* enable high power */ 209 #define SDIO_HIGHPWR_EN 0x4 210 /* standard power function(up to 200mA */ 211 #define SDIO_HP_STD 0 212 /* need high power to operate */ 213 #define SDIO_HP_REQUIRED 0x2 214 /* can work with standard power, but prefer high power */ 215 #define SDIO_HP_DESIRED 0x3 216 217 /* misc define */ 218 /* macro to calculate fbr register base */ 219 #define FBR_REG_BASE(n) (n*0x100) 220 #define SDIO_FUNC_0 0 221 #define SDIO_FUNC_1 1 222 #define SDIO_FUNC_2 2 223 #define SDIO_FUNC_3 3 224 #define SDIO_FUNC_4 4 225 #define SDIO_FUNC_5 5 226 #define SDIO_FUNC_6 6 227 #define SDIO_FUNC_7 7 228 229 /* maximum block size for block mode operation */ 230 #define SDIO_MAX_BLOCK_SIZE 2048 231 /* minimum block size for block mode operation */ 232 #define SDIO_MIN_BLOCK_SIZE 1 233 234 /* Card registers: status bit position */ 235 #define SDIO_STATUS_OUTOFRANGE 31 236 #define SDIO_STATUS_COMCRCERROR 23 237 #define SDIO_STATUS_ILLEGALCOMMAND 22 238 #define SDIO_STATUS_ERROR 19 239 #define SDIO_STATUS_IOCURRENTSTATE3 12 240 #define SDIO_STATUS_IOCURRENTSTATE2 11 241 #define SDIO_STATUS_IOCURRENTSTATE1 10 242 #define SDIO_STATUS_IOCURRENTSTATE0 9 243 #define SDIO_STATUS_FUN_NUM_ERROR 4 244 245 #define GET_SDIOCARD_STATUS(x) ((x >> 9) & 0x0f) 246 #define SDIO_STATUS_STATE_IDLE 0 247 #define SDIO_STATUS_STATE_READY 1 248 #define SDIO_STATUS_STATE_IDENT 2 249 #define SDIO_STATUS_STATE_STBY 3 250 #define SDIO_STATUS_STATE_TRAN 4 251 #define SDIO_STATUS_STATE_DATA 5 252 #define SDIO_STATUS_STATE_RCV 6 253 #define SDIO_STATUS_STATE_PRG 7 254 #define SDIO_STATUS_STATE_DIS 8 255 256 /* sprom */ 257 #define SBSDIO_SPROM_CS 0x10000 /* command and status */ 258 #define SBSDIO_SPROM_INFO 0x10001 /* info register */ 259 #define SBSDIO_SPROM_DATA_LOW 0x10002 /* indirect access data uint8_t 0 */ 260 #define SBSDIO_SPROM_DATA_HIGH 0x10003 /* indirect access data uint8_t 1 */ 261 #define SBSDIO_SPROM_ADDR_LOW 0x10004 /* indirect access addr uint8_t 0 */ 262 #define SBSDIO_SPROM_ADDR_HIGH 0x10005 /* indirect access addr uint8_t 0 */ 263 #define SBSDIO_CHIP_CTRL_DATA 0x10006 /* xtal_pu data output */ 264 #define SBSDIO_CHIP_CTRL_EN 0x10007 /* xtal_pu enable */ 265 #define SBSDIO_WATERMARK 0x10008 /* retired in rev 7 */ 266 #define SBSDIO_DEVICE_CTL 0x10009 /* control busy signal generation */ 267 268 #define SBSDIO_SPROM_IDLE 0 269 #define SBSDIO_SPROM_WRITE 1 270 #define SBSDIO_SPROM_READ 2 271 #define SBSDIO_SPROM_WEN 4 272 #define SBSDIO_SPROM_WDS 7 273 #define SBSDIO_SPROM_DONE 8 274 275 /* SBSDIO_SPROM_INFO */ 276 #define SBSDIO_SROM_SZ_MASK 0x03 /* SROM size, 1: 4k, 2: 16k */ 277 #define SBSDIO_SROM_BLANK 0x04 /* depreciated in corerev 6 */ 278 #define SBSDIO_SROM_OTP 0x80 /* OTP present */ 279 280 /* SBSDIO_CHIP_CTRL */ 281 /* or'd with onchip xtal_pu, 1: power on oscillator */ 282 #define SBSDIO_CHIP_CTRL_XTAL 0x01 283 284 /* SBSDIO_WATERMARK */ 285 /* number of bytes minus 1 for sd device to wait before sending data to host */ 286 #define SBSDIO_WATERMARK_MASK 0x3f 287 288 /* SBSDIO_DEVICE_CTL */ 289 /* 1: device will assert busy signal when receiving CMD53 */ 290 #define SBSDIO_DEVCTL_SETBUSY 0x01 291 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */ 292 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 293 294 /* function 1 OCP space */ 295 /* sb offset addr is <= 15 bits, 32k */ 296 #define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF 297 #define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000 298 /* sdsdio function 1 OCP space has 16/32 bit section */ 299 #define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000 300 301 /* direct(mapped) cis space */ 302 /* MAPPED common CIS address */ 303 #define SBSDIO_CIS_BASE_COMMON 0x1000 304 /* function 0(common) cis size in bytes */ 305 #define SBSDIO_CIS_FUNC0_LIMIT 0x020 306 /* function 1 cis size in bytes */ 307 #define SBSDIO_CIS_SIZE_LIMIT 0x200 308 /* cis offset addr is < 17 bits */ 309 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF 310 /* manfid tuple length, include tuple, link bytes */ 311 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6 312 313 /* indirect cis access (in sprom) */ 314 /* 8 control bytes first, CIS starts from 8th uint8_t */ 315 #define SBSDIO_SPROM_CIS_OFFSET 0x8 316 /* sdio uint8_t mode: maximum length of one data command */ 317 #define SBSDIO_BYTEMODE_DATALEN_MAX 64 318 /* 4317 supports less */ 319 #define SBSDIO_BYTEMODE_DATALEN_MAX_4317 52 320 /* sdio core function one address mask */ 321 #define SBSDIO_CORE_ADDR_MASK 0x1FFFF 322 323 /* CEATA defines */ 324 #define CEATA_EXT_CSDBLOCK_SIZE 512 325 #define CEATA_FAST_IO 39 326 #define CEATA_MULTIPLE_REGISTER_RW 60 327 #define CEATA_MULTIPLE_BLOCK_RW 61 328 329 /* defines CE ATA task file registers */ 330 #define CEATA_SCT_CNT_EXP_REG 0x02 331 #define CEATA_LBA_LOW_EXP_REG 0x03 332 #define CEATA_LBA_MID_EXP_REG 0x04 333 #define CEATA_LBA_HIGH_EXP_REG 0x05 334 #define CEATA_CNTRL_REG 0x06 335 #define CEATA_FEATURE_REG 0x09 /* write */ 336 #define CEATA_ERROR_REG 0x09 /* read */ 337 #define CEATA_SCT_CNT_REG 0x0A 338 #define CEATA_LBA_LOW_REG 0x0B 339 #define CEATA_LBA_MID_REG 0x0C 340 #define CEATA_LBA_HIGH_REG 0x0D 341 #define CEATA_DEV_HEAD_REG 0x0E 342 #define CEATA_STA_REG 0x0F /* read */ 343 #define CEATA_CMD_REG 0x0F /* write */ 344 345 /* defines CEATA control and status registers for ce ata client driver */ 346 #define CEATA_SCR_TEMPC_REG 0x80 347 #define CEATA_SCR_TEMPMAXP_REG 0x84 348 #define CEATA_TEMPMINP_REG 0x88 349 #define CEATA_SCR_STATUS_REG 0x8C 350 #define CEATA_SCR_REALLOCSA_REG 0x90 351 #define CEATA_SCR_ERETRACTSA_REG 0x94 352 #define CEATA_SCR_CAPABILITIES_REG 0x98 353 #define CEATA_SCR_CONTROL_REG 0xC0 354 355 /* defines for SCR capabilities register bits for ce ata client driver */ 356 #define CEATA_SCR_CAP_512 0x00000001 357 #define CEATA_SCR_CAP_1K 0x00000002 358 #define CEATA_SCR_CAP_4K 0x00000004 359 360 /* defines CE ATA Control reg bits for ce ata client driver */ 361 #define CEATA_CNTRL_ENABLE_INTR 0x00 362 #define CEATA_CNTRL_DISABLE_INTR 0x02 363 #define CEATA_CNTRL_SRST 0x04 364 #define CEATA_CNTRL_RSRST 0x00 365 366 /* define CE ATA Status reg bits for ce ata client driver */ 367 #define CEATA_STA_ERROR_BIT 0x01 368 #define CEATA_STA_OVR_BIT 0x02 369 #define CEATA_STA_SPT_BIT 0x04 370 #define CEATA_STA_DRQ_BIT 0x08 371 #define CEATA_STA_DRDY_BIT 0x40 372 #define CEATA_STA_BSY_BIT 0x80 373 374 /* define CE ATA Error reg bits for ce ata client driver */ 375 #define CEATA_ERROR_ABORTED_BIT 0x04 376 #define CEATA_ERROR_IDNF_BIT 0x10 377 #define CEATA_ERROR_UNCORRECTABLE_BIT 0x40 378 #define CEATA_ERROR_ICRC_BIT 0x80 379 380 /* define CE ATA Commands for ce ata client driver */ 381 #define CEATA_CMD_IDENTIFY_DEVICE 0xEC 382 #define CEATA_CMD_READ_DMA_EXT 0x25 383 #define CEATA_CMD_WRITE_DMA_EXT 0x35 384 #define CEATA_CMD_STANDBY_IMMEDIATE 0xE0 385 #define CEATA_CMD_FLUSH_CACHE_EXT 0xEA 386 387 struct csd_mmc { 388 uint32_t padding:8; 389 uint32_t structure:2; 390 uint32_t csdSpecVer:4; 391 uint32_t reserved1:2; 392 uint32_t taac:8; 393 uint32_t nsac:8; 394 uint32_t speed:8; 395 uint32_t classes:12; 396 uint32_t rdBlkLen:4; 397 uint32_t rdBlkPartial:1; 398 uint32_t wrBlkMisalign:1; 399 uint32_t rdBlkMisalign:1; 400 uint32_t dsr:1; 401 uint32_t reserved2:2; 402 uint32_t size:12; 403 uint32_t vddRdCurrMin:3; 404 uint32_t vddRdCurrMax:3; 405 uint32_t vddWrCurrMin:3; 406 uint32_t vddWrCurrMax:3; 407 uint32_t devSizeMulti:3; 408 uint32_t eraseGrpSize:5; 409 uint32_t eraseGrpSizeMulti:5; 410 uint32_t wrProtGroupSize:5; 411 uint32_t wrProtGroupEnable:1; 412 uint32_t manuDefEcc:2; 413 uint32_t wrSpeedFactor:3; 414 uint32_t wrBlkLen:4; 415 uint32_t wrBlkPartial:1; 416 uint32_t reserved5:4; 417 uint32_t protAppl:1; 418 uint32_t fileFormatGrp:1; 419 uint32_t copyFlag:1; 420 uint32_t permWrProt:1; 421 uint32_t tmpWrProt:1; 422 uint32_t fileFormat:2; 423 uint32_t eccCode:2; 424 }; 425 426 /* CSD register*/ 427 union sd_csd { 428 uint32_t csd[4]; 429 struct csd_mmc mmc; 430 }; 431 432 struct sd_card_data { 433 union sd_csd csd; 434 }; 435 #endif /* CSL_SD_PROT_H */ 436
