1 /* 2 * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_SPM_REG 8 #define MT_SPM_REG 9 10 #include "pcm_def.h" 11 #include <platform_def.h> 12 #include "sleep_def.h" 13 14 /* Define and Declare */ 15 #define POWERON_CONFIG_EN (SPM_BASE + 0x000) 16 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004) 17 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008) 18 #define SPM_CLK_CON (SPM_BASE + 0x00C) 19 #define SPM_CLK_SETTLE (SPM_BASE + 0x010) 20 #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014) 21 #define PCM_CON0 (SPM_BASE + 0x018) 22 #define PCM_CON1 (SPM_BASE + 0x01C) 23 #define SPM_POWER_ON_VAL2 (SPM_BASE + 0x020) 24 #define SPM_POWER_ON_VAL3 (SPM_BASE + 0x024) 25 #define PCM_REG_DATA_INI (SPM_BASE + 0x028) 26 #define PCM_PWR_IO_EN (SPM_BASE + 0x02C) 27 #define PCM_TIMER_VAL (SPM_BASE + 0x030) 28 #define PCM_WDT_VAL (SPM_BASE + 0x034) 29 #define SPM_SW_RST_CON (SPM_BASE + 0x040) 30 #define SPM_SW_RST_CON_SET (SPM_BASE + 0x044) 31 #define SPM_SW_RST_CON_CLR (SPM_BASE + 0x048) 32 #define SPM_SRC6_MASK (SPM_BASE + 0x04C) 33 #define MD32_CLK_CON (SPM_BASE + 0x084) 34 #define SPM_SRAM_RSV_CON (SPM_BASE + 0x088) 35 #define SPM_SWINT (SPM_BASE + 0x08C) 36 #define SPM_SWINT_SET (SPM_BASE + 0x090) 37 #define SPM_SWINT_CLR (SPM_BASE + 0x094) 38 #define SPM_SCP_MAILBOX (SPM_BASE + 0x098) 39 #define SCP_SPM_MAILBOX (SPM_BASE + 0x09C) 40 #define SPM_WAKEUP_EVENT_SENS (SPM_BASE + 0x0A0) 41 #define SPM_WAKEUP_EVENT_CLEAR (SPM_BASE + 0x0A4) 42 #define SPM_SCP_IRQ (SPM_BASE + 0x0AC) 43 #define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x0B0) 44 #define SPM_IRQ_MASK (SPM_BASE + 0x0B4) 45 #define SPM_SRC_REQ (SPM_BASE + 0x0B8) 46 #define SPM_SRC_MASK (SPM_BASE + 0x0BC) 47 #define SPM_SRC2_MASK (SPM_BASE + 0x0C0) 48 #define SPM_SRC3_MASK (SPM_BASE + 0x0C4) 49 #define SPM_SRC4_MASK (SPM_BASE + 0x0C8) 50 #define SPM_SRC5_MASK (SPM_BASE + 0x0CC) 51 #define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x0D0) 52 #define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x0D4) 53 #define SPM_SRC7_MASK (SPM_BASE + 0x0D8) 54 #define SCP_CLK_CON (SPM_BASE + 0x0DC) 55 #define PCM_DEBUG_CON (SPM_BASE + 0x0E0) 56 #define DDREN_DBC_CON (SPM_BASE + 0x0E8) 57 #define SPM_RESOURCE_ACK_CON4 (SPM_BASE + 0x0EC) 58 #define SPM_RESOURCE_ACK_CON0 (SPM_BASE + 0x0F0) 59 #define SPM_RESOURCE_ACK_CON1 (SPM_BASE + 0x0F4) 60 #define SPM_RESOURCE_ACK_CON2 (SPM_BASE + 0x0F8) 61 #define SPM_RESOURCE_ACK_CON3 (SPM_BASE + 0x0FC) 62 #define PCM_REG0_DATA (SPM_BASE + 0x100) 63 #define PCM_REG2_DATA (SPM_BASE + 0x104) 64 #define PCM_REG6_DATA (SPM_BASE + 0x108) 65 #define PCM_REG7_DATA (SPM_BASE + 0x10C) 66 #define PCM_REG13_DATA (SPM_BASE + 0x110) 67 #define SRC_REQ_STA_0 (SPM_BASE + 0x114) 68 #define SRC_REQ_STA_1 (SPM_BASE + 0x118) 69 #define SRC_REQ_STA_2 (SPM_BASE + 0x11C) 70 #define PCM_TIMER_OUT (SPM_BASE + 0x120) 71 #define PCM_WDT_OUT (SPM_BASE + 0x124) 72 #define SPM_IRQ_STA (SPM_BASE + 0x128) 73 #define SRC_REQ_STA_4 (SPM_BASE + 0x12C) 74 #define MD32PCM_WAKEUP_STA (SPM_BASE + 0x130) 75 #define MD32PCM_EVENT_STA (SPM_BASE + 0x134) 76 #define SPM_WAKEUP_STA (SPM_BASE + 0x138) 77 #define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x13C) 78 #define SPM_WAKEUP_MISC (SPM_BASE + 0x140) 79 #define MM_DVFS_HALT (SPM_BASE + 0x144) 80 #define BUS_PROTECT_RDY (SPM_BASE + 0x150) 81 #define BUS_PROTECT1_RDY (SPM_BASE + 0x154) 82 #define BUS_PROTECT2_RDY (SPM_BASE + 0x158) 83 #define BUS_PROTECT3_RDY (SPM_BASE + 0x15C) 84 #define SUBSYS_IDLE_STA (SPM_BASE + 0x160) 85 #define PCM_STA (SPM_BASE + 0x164) 86 #define SRC_REQ_STA_3 (SPM_BASE + 0x168) 87 #define PWR_STATUS (SPM_BASE + 0x16C) 88 #define PWR_STATUS_2ND (SPM_BASE + 0x170) 89 #define CPU_PWR_STATUS (SPM_BASE + 0x174) 90 #define OTHER_PWR_STATUS (SPM_BASE + 0x178) 91 #define SPM_VTCXO_EVENT_COUNT_STA (SPM_BASE + 0x17C) 92 #define SPM_INFRA_EVENT_COUNT_STA (SPM_BASE + 0x180) 93 #define SPM_VRF18_EVENT_COUNT_STA (SPM_BASE + 0x184) 94 #define SPM_APSRC_EVENT_COUNT_STA (SPM_BASE + 0x188) 95 #define SPM_DDREN_EVENT_COUNT_STA (SPM_BASE + 0x18C) 96 #define MD32PCM_STA (SPM_BASE + 0x190) 97 #define MD32PCM_PC (SPM_BASE + 0x194) 98 #define DVFSRC_EVENT_STA (SPM_BASE + 0x1A4) 99 #define BUS_PROTECT4_RDY (SPM_BASE + 0x1A8) 100 #define BUS_PROTECT5_RDY (SPM_BASE + 0x1AC) 101 #define BUS_PROTECT6_RDY (SPM_BASE + 0x1B0) 102 #define BUS_PROTECT7_RDY (SPM_BASE + 0x1B4) 103 #define BUS_PROTECT8_RDY (SPM_BASE + 0x1B8) 104 #define SPM_TWAM_LAST_STA0 (SPM_BASE + 0x1D0) 105 #define SPM_TWAM_LAST_STA1 (SPM_BASE + 0x1D4) 106 #define SPM_TWAM_LAST_STA2 (SPM_BASE + 0x1D8) 107 #define SPM_TWAM_LAST_STA3 (SPM_BASE + 0x1DC) 108 #define SPM_TWAM_CURR_STA0 (SPM_BASE + 0x1E0) 109 #define SPM_TWAM_CURR_STA1 (SPM_BASE + 0x1E4) 110 #define SPM_TWAM_CURR_STA2 (SPM_BASE + 0x1E8) 111 #define SPM_TWAM_CURR_STA3 (SPM_BASE + 0x1EC) 112 #define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x1F0) 113 #define SPM_CG_CHECK_STA (SPM_BASE + 0x1F4) 114 #define SPM_DVFS_STA (SPM_BASE + 0x1F8) 115 #define SPM_DVFS_OPP_STA (SPM_BASE + 0x1FC) 116 #define SPM_MCUSYS_PWR_CON (SPM_BASE + 0x200) 117 #define SPM_CPUTOP_PWR_CON (SPM_BASE + 0x204) 118 #define SPM_CPU0_PWR_CON (SPM_BASE + 0x208) 119 #define SPM_CPU1_PWR_CON (SPM_BASE + 0x20C) 120 #define SPM_CPU2_PWR_CON (SPM_BASE + 0x210) 121 #define SPM_CPU3_PWR_CON (SPM_BASE + 0x214) 122 #define SPM_CPU4_PWR_CON (SPM_BASE + 0x218) 123 #define SPM_CPU5_PWR_CON (SPM_BASE + 0x21C) 124 #define SPM_CPU6_PWR_CON (SPM_BASE + 0x220) 125 #define SPM_CPU7_PWR_CON (SPM_BASE + 0x224) 126 #define ARMPLL_CLK_CON (SPM_BASE + 0x22C) 127 #define MCUSYS_IDLE_STA (SPM_BASE + 0x230) 128 #define GIC_WAKEUP_STA (SPM_BASE + 0x234) 129 #define CPU_SPARE_CON (SPM_BASE + 0x238) 130 #define CPU_SPARE_CON_SET (SPM_BASE + 0x23C) 131 #define CPU_SPARE_CON_CLR (SPM_BASE + 0x240) 132 #define ARMPLL_CLK_SEL (SPM_BASE + 0x244) 133 #define EXT_INT_WAKEUP_REQ (SPM_BASE + 0x248) 134 #define EXT_INT_WAKEUP_REQ_SET (SPM_BASE + 0x24C) 135 #define EXT_INT_WAKEUP_REQ_CLR (SPM_BASE + 0x250) 136 #define CPU_IRQ_MASK (SPM_BASE + 0x260) 137 #define CPU_IRQ_MASK_SET (SPM_BASE + 0x264) 138 #define CPU_IRQ_MASK_CLR (SPM_BASE + 0x268) 139 #define CPU_WFI_EN (SPM_BASE + 0x280) 140 #define CPU_WFI_EN_SET (SPM_BASE + 0x284) 141 #define CPU_WFI_EN_CLR (SPM_BASE + 0x288) 142 #define ROOT_CPUTOP_ADDR (SPM_BASE + 0x2A0) 143 #define ROOT_CORE_ADDR (SPM_BASE + 0x2A4) 144 #define SPM2SW_MAILBOX_0 (SPM_BASE + 0x2D0) 145 #define SPM2SW_MAILBOX_1 (SPM_BASE + 0x2D4) 146 #define SPM2SW_MAILBOX_2 (SPM_BASE + 0x2D8) 147 #define SPM2SW_MAILBOX_3 (SPM_BASE + 0x2DC) 148 #define SW2SPM_WAKEUP (SPM_BASE + 0x2E0) 149 #define SW2SPM_WAKEUP_SET (SPM_BASE + 0x2E4) 150 #define SW2SPM_WAKEUP_CLR (SPM_BASE + 0x2E8) 151 #define SW2SPM_MAILBOX_0 (SPM_BASE + 0x2EC) 152 #define SW2SPM_MAILBOX_1 (SPM_BASE + 0x2F0) 153 #define SW2SPM_MAILBOX_2 (SPM_BASE + 0x2F4) 154 #define SW2SPM_MAILBOX_3 (SPM_BASE + 0x2F8) 155 #define SW2SPM_CFG (SPM_BASE + 0x2FC) 156 #define MD1_PWR_CON (SPM_BASE + 0x300) 157 #define CONN_PWR_CON (SPM_BASE + 0x304) 158 #define MFG0_PWR_CON (SPM_BASE + 0x308) 159 #define MFG1_PWR_CON (SPM_BASE + 0x30C) 160 #define MFG2_PWR_CON (SPM_BASE + 0x310) 161 #define MFG3_PWR_CON (SPM_BASE + 0x314) 162 #define MFG4_PWR_CON (SPM_BASE + 0x318) 163 #define MFG5_PWR_CON (SPM_BASE + 0x31C) 164 #define MFG6_PWR_CON (SPM_BASE + 0x320) 165 #define IFR_PWR_CON (SPM_BASE + 0x324) 166 #define IFR_SUB_PWR_CON (SPM_BASE + 0x328) 167 #define DPY_PWR_CON (SPM_BASE + 0x32C) 168 #define DRAMC_MD32_PWR_CON (SPM_BASE + 0x330) 169 #define ISP_PWR_CON (SPM_BASE + 0x334) 170 #define ISP2_PWR_CON (SPM_BASE + 0x338) 171 #define IPE_PWR_CON (SPM_BASE + 0x33C) 172 #define VDE_PWR_CON (SPM_BASE + 0x340) 173 #define VDE2_PWR_CON (SPM_BASE + 0x344) 174 #define VEN_PWR_CON (SPM_BASE + 0x348) 175 #define VEN_CORE1_PWR_CON (SPM_BASE + 0x34C) 176 #define MDP_PWR_CON (SPM_BASE + 0x350) 177 #define DIS_PWR_CON (SPM_BASE + 0x354) 178 #define AUDIO_PWR_CON (SPM_BASE + 0x358) 179 #define CAM_PWR_CON (SPM_BASE + 0x35C) 180 #define CAM_RAWA_PWR_CON (SPM_BASE + 0x360) 181 #define CAM_RAWB_PWR_CON (SPM_BASE + 0x364) 182 #define CAM_RAWC_PWR_CON (SPM_BASE + 0x368) 183 #define SYSRAM_CON (SPM_BASE + 0x36C) 184 #define SYSROM_CON (SPM_BASE + 0x370) 185 #define SSPM_SRAM_CON (SPM_BASE + 0x374) 186 #define SCP_SRAM_CON (SPM_BASE + 0x378) 187 #define DPY_SHU_SRAM_CON (SPM_BASE + 0x37C) 188 #define UFS_SRAM_CON (SPM_BASE + 0x380) 189 #define DEVAPC_IFR_SRAM_CON (SPM_BASE + 0x384) 190 #define DEVAPC_SUBIFR_SRAM_CON (SPM_BASE + 0x388) 191 #define DEVAPC_ACP_SRAM_CON (SPM_BASE + 0x38C) 192 #define USB_SRAM_CON (SPM_BASE + 0x390) 193 #define DUMMY_SRAM_CON (SPM_BASE + 0x394) 194 #define MD_EXT_BUCK_ISO_CON (SPM_BASE + 0x398) 195 #define EXT_BUCK_ISO (SPM_BASE + 0x39C) 196 #define DXCC_SRAM_CON (SPM_BASE + 0x3A0) 197 #define MSDC_PWR_CON (SPM_BASE + 0x3A4) 198 #define DEBUGTOP_SRAM_CON (SPM_BASE + 0x3A8) 199 #define DP_TX_PWR_CON (SPM_BASE + 0x3AC) 200 #define DPMAIF_SRAM_CON (SPM_BASE + 0x3B0) 201 #define DPY_SHU2_SRAM_CON (SPM_BASE + 0x3B4) 202 #define DRAMC_MCU2_SRAM_CON (SPM_BASE + 0x3B8) 203 #define DRAMC_MCU_SRAM_CON (SPM_BASE + 0x3BC) 204 #define MCUPM_PWR_CON (SPM_BASE + 0x3C0) 205 #define DPY2_PWR_CON (SPM_BASE + 0x3C4) 206 #define SPM_SRAM_CON (SPM_BASE + 0x3C8) 207 #define PERI_PWR_CON (SPM_BASE + 0x3D0) 208 #define NNA0_PWR_CON (SPM_BASE + 0x3D4) 209 #define NNA1_PWR_CON (SPM_BASE + 0x3D8) 210 #define NNA2_PWR_CON (SPM_BASE + 0x3DC) 211 #define NNA_PWR_CON (SPM_BASE + 0x3E0) 212 #define ADSP_PWR_CON (SPM_BASE + 0x3E4) 213 #define DPY_SRAM_CON (SPM_BASE + 0x3E8) 214 #define SPM_MEM_CK_SEL (SPM_BASE + 0x400) 215 #define SPM_BUS_PROTECT_MASK_B (SPM_BASE + 0x404) 216 #define SPM_BUS_PROTECT1_MASK_B (SPM_BASE + 0x408) 217 #define SPM_BUS_PROTECT2_MASK_B (SPM_BASE + 0x40C) 218 #define SPM_BUS_PROTECT3_MASK_B (SPM_BASE + 0x410) 219 #define SPM_BUS_PROTECT4_MASK_B (SPM_BASE + 0x414) 220 #define SPM_EMI_BW_MODE (SPM_BASE + 0x418) 221 #define AP2MD_PEER_WAKEUP (SPM_BASE + 0x41C) 222 #define ULPOSC_CON (SPM_BASE + 0x420) 223 #define SPM2MM_CON (SPM_BASE + 0x424) 224 #define SPM_BUS_PROTECT5_MASK_B (SPM_BASE + 0x428) 225 #define SPM2MCUPM_CON (SPM_BASE + 0x42C) 226 #define AP_MDSRC_REQ (SPM_BASE + 0x430) 227 #define SPM2EMI_ENTER_ULPM (SPM_BASE + 0x434) 228 #define SPM2MD_DVFS_CON (SPM_BASE + 0x438) 229 #define MD2SPM_DVFS_CON (SPM_BASE + 0x43C) 230 #define SPM_BUS_PROTECT6_MASK_B (SPM_BASE + 0x440) 231 #define SPM_BUS_PROTECT7_MASK_B (SPM_BASE + 0x444) 232 #define SPM_BUS_PROTECT8_MASK_B (SPM_BASE + 0x448) 233 #define SPM_PLL_CON (SPM_BASE + 0x44C) 234 #define RC_SPM_CTRL (SPM_BASE + 0x450) 235 #define SPM_DRAM_MCU_SW_CON_0 (SPM_BASE + 0x454) 236 #define SPM_DRAM_MCU_SW_CON_1 (SPM_BASE + 0x458) 237 #define SPM_DRAM_MCU_SW_CON_2 (SPM_BASE + 0x45C) 238 #define SPM_DRAM_MCU_SW_CON_3 (SPM_BASE + 0x460) 239 #define SPM_DRAM_MCU_SW_CON_4 (SPM_BASE + 0x464) 240 #define SPM_DRAM_MCU_STA_0 (SPM_BASE + 0x468) 241 #define SPM_DRAM_MCU_STA_1 (SPM_BASE + 0x46C) 242 #define SPM_DRAM_MCU_STA_2 (SPM_BASE + 0x470) 243 #define SPM_DRAM_MCU_SW_SEL_0 (SPM_BASE + 0x474) 244 #define RELAY_DVFS_LEVEL (SPM_BASE + 0x478) 245 #define DRAMC_DPY_CLK_SW_CON_0 (SPM_BASE + 0x480) 246 #define DRAMC_DPY_CLK_SW_CON_1 (SPM_BASE + 0x484) 247 #define DRAMC_DPY_CLK_SW_CON_2 (SPM_BASE + 0x488) 248 #define DRAMC_DPY_CLK_SW_CON_3 (SPM_BASE + 0x48C) 249 #define DRAMC_DPY_CLK_SW_SEL_0 (SPM_BASE + 0x490) 250 #define DRAMC_DPY_CLK_SW_SEL_1 (SPM_BASE + 0x494) 251 #define DRAMC_DPY_CLK_SW_SEL_2 (SPM_BASE + 0x498) 252 #define DRAMC_DPY_CLK_SW_SEL_3 (SPM_BASE + 0x49C) 253 #define DRAMC_DPY_CLK_SPM_CON (SPM_BASE + 0x4A0) 254 #define SPM_DVFS_LEVEL (SPM_BASE + 0x4A4) 255 #define SPM_CIRQ_CON (SPM_BASE + 0x4A8) 256 #define SPM_DVFS_MISC (SPM_BASE + 0x4AC) 257 #define RG_MODULE_SW_CG_0_MASK_REQ_0 (SPM_BASE + 0x4B4) 258 #define RG_MODULE_SW_CG_0_MASK_REQ_1 (SPM_BASE + 0x4B8) 259 #define RG_MODULE_SW_CG_0_MASK_REQ_2 (SPM_BASE + 0x4BC) 260 #define RG_MODULE_SW_CG_1_MASK_REQ_0 (SPM_BASE + 0x4C0) 261 #define RG_MODULE_SW_CG_1_MASK_REQ_1 (SPM_BASE + 0x4C4) 262 #define RG_MODULE_SW_CG_1_MASK_REQ_2 (SPM_BASE + 0x4C8) 263 #define RG_MODULE_SW_CG_2_MASK_REQ_0 (SPM_BASE + 0x4CC) 264 #define RG_MODULE_SW_CG_2_MASK_REQ_1 (SPM_BASE + 0x4D0) 265 #define RG_MODULE_SW_CG_2_MASK_REQ_2 (SPM_BASE + 0x4D4) 266 #define RG_MODULE_SW_CG_3_MASK_REQ_0 (SPM_BASE + 0x4D8) 267 #define RG_MODULE_SW_CG_3_MASK_REQ_1 (SPM_BASE + 0x4DC) 268 #define RG_MODULE_SW_CG_3_MASK_REQ_2 (SPM_BASE + 0x4E0) 269 #define PWR_STATUS_MASK_REQ_0 (SPM_BASE + 0x4E4) 270 #define PWR_STATUS_MASK_REQ_1 (SPM_BASE + 0x4E8) 271 #define PWR_STATUS_MASK_REQ_2 (SPM_BASE + 0x4EC) 272 #define SPM_CG_CHECK_CON (SPM_BASE + 0x4F0) 273 #define SPM_SRC_RDY_STA (SPM_BASE + 0x4F4) 274 #define SPM_DVS_DFS_LEVEL (SPM_BASE + 0x4F8) 275 #define SPM_FORCE_DVFS (SPM_BASE + 0x4FC) 276 #define RC_M00_SRCLKEN_CFG (SPM_BASE + 0x520) 277 #define SPM_SW_FLAG_0 (SPM_BASE + 0x600) 278 #define SPM_SW_DEBUG_0 (SPM_BASE + 0x604) 279 #define SPM_SW_FLAG_1 (SPM_BASE + 0x608) 280 #define SPM_SW_DEBUG_1 (SPM_BASE + 0x60C) 281 #define SPM_SW_RSV_0 (SPM_BASE + 0x610) 282 #define SPM_SW_RSV_1 (SPM_BASE + 0x614) 283 #define SPM_SW_RSV_2 (SPM_BASE + 0x618) 284 #define SPM_SW_RSV_3 (SPM_BASE + 0x61C) 285 #define SPM_SW_RSV_4 (SPM_BASE + 0x620) 286 #define SPM_SW_RSV_5 (SPM_BASE + 0x624) 287 #define SPM_SW_RSV_6 (SPM_BASE + 0x628) 288 #define SPM_SW_RSV_7 (SPM_BASE + 0x62C) 289 #define SPM_SW_RSV_8 (SPM_BASE + 0x630) 290 #define SPM_BK_WAKE_EVENT (SPM_BASE + 0x634) 291 #define SPM_BK_VTCXO_DUR (SPM_BASE + 0x638) 292 #define SPM_BK_WAKE_MISC (SPM_BASE + 0x63C) 293 #define SPM_BK_PCM_TIMER (SPM_BASE + 0x640) 294 #define SPM_RSV_CON_0 (SPM_BASE + 0x650) 295 #define SPM_RSV_CON_1 (SPM_BASE + 0x654) 296 #define SPM_RSV_STA_0 (SPM_BASE + 0x658) 297 #define SPM_RSV_STA_1 (SPM_BASE + 0x65C) 298 #define SPM_SPARE_CON (SPM_BASE + 0x660) 299 #define SPM_SPARE_CON_SET (SPM_BASE + 0x664) 300 #define SPM_SPARE_CON_CLR (SPM_BASE + 0x668) 301 #define SPM_CROSS_WAKE_M00_REQ (SPM_BASE + 0x66C) 302 #define SPM_CROSS_WAKE_M01_REQ (SPM_BASE + 0x670) 303 #define SPM_CROSS_WAKE_M02_REQ (SPM_BASE + 0x674) 304 #define SPM_CROSS_WAKE_M03_REQ (SPM_BASE + 0x678) 305 #define SCP_VCORE_LEVEL (SPM_BASE + 0x67C) 306 #define SC_MM_CK_SEL_CON (SPM_BASE + 0x680) 307 #define SPARE_ACK_MASK (SPM_BASE + 0x684) 308 #define SPM_SPARE_FUNCTION (SPM_BASE + 0x688) 309 #define SPM_DV_CON_0 (SPM_BASE + 0x68C) 310 #define SPM_DV_CON_1 (SPM_BASE + 0x690) 311 #define SPM_DV_STA (SPM_BASE + 0x694) 312 #define CONN_XOWCN_DEBUG_EN (SPM_BASE + 0x698) 313 #define SPM_SEMA_M0 (SPM_BASE + 0x69C) 314 #define SPM_SEMA_M1 (SPM_BASE + 0x6A0) 315 #define SPM_SEMA_M2 (SPM_BASE + 0x6A4) 316 #define SPM_SEMA_M3 (SPM_BASE + 0x6A8) 317 #define SPM_SEMA_M4 (SPM_BASE + 0x6AC) 318 #define SPM_SEMA_M5 (SPM_BASE + 0x6B0) 319 #define SPM_SEMA_M6 (SPM_BASE + 0x6B4) 320 #define SPM_SEMA_M7 (SPM_BASE + 0x6B8) 321 #define SPM2ADSP_MAILBOX (SPM_BASE + 0x6BC) 322 #define ADSP2SPM_MAILBOX (SPM_BASE + 0x6C0) 323 #define SPM_ADSP_IRQ (SPM_BASE + 0x6C4) 324 #define SPM_MD32_IRQ (SPM_BASE + 0x6C8) 325 #define SPM2PMCU_MAILBOX_0 (SPM_BASE + 0x6CC) 326 #define SPM2PMCU_MAILBOX_1 (SPM_BASE + 0x6D0) 327 #define SPM2PMCU_MAILBOX_2 (SPM_BASE + 0x6D4) 328 #define SPM2PMCU_MAILBOX_3 (SPM_BASE + 0x6D8) 329 #define PMCU2SPM_MAILBOX_0 (SPM_BASE + 0x6DC) 330 #define PMCU2SPM_MAILBOX_1 (SPM_BASE + 0x6E0) 331 #define PMCU2SPM_MAILBOX_2 (SPM_BASE + 0x6E4) 332 #define PMCU2SPM_MAILBOX_3 (SPM_BASE + 0x6E8) 333 #define UFS_PSRI_SW (SPM_BASE + 0x6EC) 334 #define UFS_PSRI_SW_SET (SPM_BASE + 0x6F0) 335 #define UFS_PSRI_SW_CLR (SPM_BASE + 0x6F4) 336 #define SPM_AP_SEMA (SPM_BASE + 0x6F8) 337 #define SPM_SPM_SEMA (SPM_BASE + 0x6FC) 338 #define SPM_DVFS_CON (SPM_BASE + 0x700) 339 #define SPM_DVFS_CON_STA (SPM_BASE + 0x704) 340 #define SPM_PMIC_SPMI_CON (SPM_BASE + 0x708) 341 #define SPM_DVFS_CMD0 (SPM_BASE + 0x710) 342 #define SPM_DVFS_CMD1 (SPM_BASE + 0x714) 343 #define SPM_DVFS_CMD2 (SPM_BASE + 0x718) 344 #define SPM_DVFS_CMD3 (SPM_BASE + 0x71C) 345 #define SPM_DVFS_CMD4 (SPM_BASE + 0x720) 346 #define SPM_DVFS_CMD5 (SPM_BASE + 0x724) 347 #define SPM_DVFS_CMD6 (SPM_BASE + 0x728) 348 #define SPM_DVFS_CMD7 (SPM_BASE + 0x72C) 349 #define SPM_DVFS_CMD8 (SPM_BASE + 0x730) 350 #define SPM_DVFS_CMD9 (SPM_BASE + 0x734) 351 #define SPM_DVFS_CMD10 (SPM_BASE + 0x738) 352 #define SPM_DVFS_CMD11 (SPM_BASE + 0x73C) 353 #define SPM_DVFS_CMD12 (SPM_BASE + 0x740) 354 #define SPM_DVFS_CMD13 (SPM_BASE + 0x744) 355 #define SPM_DVFS_CMD14 (SPM_BASE + 0x748) 356 #define SPM_DVFS_CMD15 (SPM_BASE + 0x74C) 357 #define SPM_DVFS_CMD16 (SPM_BASE + 0x750) 358 #define SPM_DVFS_CMD17 (SPM_BASE + 0x754) 359 #define SPM_DVFS_CMD18 (SPM_BASE + 0x758) 360 #define SPM_DVFS_CMD19 (SPM_BASE + 0x75C) 361 #define SPM_DVFS_CMD20 (SPM_BASE + 0x760) 362 #define SPM_DVFS_CMD21 (SPM_BASE + 0x764) 363 #define SPM_DVFS_CMD22 (SPM_BASE + 0x768) 364 #define SPM_DVFS_CMD23 (SPM_BASE + 0x76C) 365 #define SYS_TIMER_VALUE_L (SPM_BASE + 0x770) 366 #define SYS_TIMER_VALUE_H (SPM_BASE + 0x774) 367 #define SYS_TIMER_START_L (SPM_BASE + 0x778) 368 #define SYS_TIMER_START_H (SPM_BASE + 0x77C) 369 #define SYS_TIMER_LATCH_L_00 (SPM_BASE + 0x780) 370 #define SYS_TIMER_LATCH_H_00 (SPM_BASE + 0x784) 371 #define SYS_TIMER_LATCH_L_01 (SPM_BASE + 0x788) 372 #define SYS_TIMER_LATCH_H_01 (SPM_BASE + 0x78C) 373 #define SYS_TIMER_LATCH_L_02 (SPM_BASE + 0x790) 374 #define SYS_TIMER_LATCH_H_02 (SPM_BASE + 0x794) 375 #define SYS_TIMER_LATCH_L_03 (SPM_BASE + 0x798) 376 #define SYS_TIMER_LATCH_H_03 (SPM_BASE + 0x79C) 377 #define SYS_TIMER_LATCH_L_04 (SPM_BASE + 0x7A0) 378 #define SYS_TIMER_LATCH_H_04 (SPM_BASE + 0x7A4) 379 #define SYS_TIMER_LATCH_L_05 (SPM_BASE + 0x7A8) 380 #define SYS_TIMER_LATCH_H_05 (SPM_BASE + 0x7AC) 381 #define SYS_TIMER_LATCH_L_06 (SPM_BASE + 0x7B0) 382 #define SYS_TIMER_LATCH_H_06 (SPM_BASE + 0x7B4) 383 #define SYS_TIMER_LATCH_L_07 (SPM_BASE + 0x7B8) 384 #define SYS_TIMER_LATCH_H_07 (SPM_BASE + 0x7BC) 385 #define SYS_TIMER_LATCH_L_08 (SPM_BASE + 0x7C0) 386 #define SYS_TIMER_LATCH_H_08 (SPM_BASE + 0x7C4) 387 #define SYS_TIMER_LATCH_L_09 (SPM_BASE + 0x7C8) 388 #define SYS_TIMER_LATCH_H_09 (SPM_BASE + 0x7CC) 389 #define SYS_TIMER_LATCH_L_10 (SPM_BASE + 0x7D0) 390 #define SYS_TIMER_LATCH_H_10 (SPM_BASE + 0x7D4) 391 #define SYS_TIMER_LATCH_L_11 (SPM_BASE + 0x7D8) 392 #define SYS_TIMER_LATCH_H_11 (SPM_BASE + 0x7DC) 393 #define SYS_TIMER_LATCH_L_12 (SPM_BASE + 0x7E0) 394 #define SYS_TIMER_LATCH_H_12 (SPM_BASE + 0x7E4) 395 #define SYS_TIMER_LATCH_L_13 (SPM_BASE + 0x7E8) 396 #define SYS_TIMER_LATCH_H_13 (SPM_BASE + 0x7EC) 397 #define SYS_TIMER_LATCH_L_14 (SPM_BASE + 0x7F0) 398 #define SYS_TIMER_LATCH_H_14 (SPM_BASE + 0x7F4) 399 #define SYS_TIMER_LATCH_L_15 (SPM_BASE + 0x7F8) 400 #define SYS_TIMER_LATCH_H_15 (SPM_BASE + 0x7FC) 401 #define PCM_WDT_LATCH_0 (SPM_BASE + 0x800) 402 #define PCM_WDT_LATCH_1 (SPM_BASE + 0x804) 403 #define PCM_WDT_LATCH_2 (SPM_BASE + 0x808) 404 #define PCM_WDT_LATCH_3 (SPM_BASE + 0x80C) 405 #define PCM_WDT_LATCH_4 (SPM_BASE + 0x810) 406 #define PCM_WDT_LATCH_5 (SPM_BASE + 0x814) 407 #define PCM_WDT_LATCH_6 (SPM_BASE + 0x818) 408 #define PCM_WDT_LATCH_7 (SPM_BASE + 0x81C) 409 #define PCM_WDT_LATCH_8 (SPM_BASE + 0x820) 410 #define PCM_WDT_LATCH_9 (SPM_BASE + 0x824) 411 #define PCM_WDT_LATCH_10 (SPM_BASE + 0x828) 412 #define PCM_WDT_LATCH_11 (SPM_BASE + 0x82C) 413 #define PCM_WDT_LATCH_12 (SPM_BASE + 0x830) 414 #define PCM_WDT_LATCH_13 (SPM_BASE + 0x834) 415 #define PCM_WDT_LATCH_14 (SPM_BASE + 0x838) 416 #define PCM_WDT_LATCH_15 (SPM_BASE + 0x83C) 417 #define PCM_WDT_LATCH_16 (SPM_BASE + 0x840) 418 #define PCM_WDT_LATCH_17 (SPM_BASE + 0x844) 419 #define PCM_WDT_LATCH_18 (SPM_BASE + 0x848) 420 #define PCM_WDT_LATCH_SPARE_0 (SPM_BASE + 0x84C) 421 #define PCM_WDT_LATCH_SPARE_1 (SPM_BASE + 0x850) 422 #define PCM_WDT_LATCH_SPARE_2 (SPM_BASE + 0x854) 423 #define PCM_WDT_LATCH_CONN_0 (SPM_BASE + 0x870) 424 #define PCM_WDT_LATCH_CONN_1 (SPM_BASE + 0x874) 425 #define PCM_WDT_LATCH_CONN_2 (SPM_BASE + 0x878) 426 #define DRAMC_GATING_ERR_LATCH_CH0_0 (SPM_BASE + 0x8A0) 427 #define DRAMC_GATING_ERR_LATCH_CH0_1 (SPM_BASE + 0x8A4) 428 #define DRAMC_GATING_ERR_LATCH_CH0_2 (SPM_BASE + 0x8A8) 429 #define DRAMC_GATING_ERR_LATCH_CH0_3 (SPM_BASE + 0x8AC) 430 #define DRAMC_GATING_ERR_LATCH_CH0_4 (SPM_BASE + 0x8B0) 431 #define DRAMC_GATING_ERR_LATCH_CH0_5 (SPM_BASE + 0x8B4) 432 #define DRAMC_GATING_ERR_LATCH_CH0_6 (SPM_BASE + 0x8B8) 433 #define DRAMC_GATING_ERR_LATCH_SPARE_0 (SPM_BASE + 0x8F4) 434 #define SPM_ACK_CHK_CON_0 (SPM_BASE + 0x900) 435 #define SPM_ACK_CHK_PC_0 (SPM_BASE + 0x904) 436 #define SPM_ACK_CHK_SEL_0 (SPM_BASE + 0x908) 437 #define SPM_ACK_CHK_TIMER_0 (SPM_BASE + 0x90C) 438 #define SPM_ACK_CHK_STA_0 (SPM_BASE + 0x910) 439 #define SPM_ACK_CHK_SWINT_0 (SPM_BASE + 0x914) 440 #define SPM_ACK_CHK_CON_1 (SPM_BASE + 0x918) 441 #define SPM_ACK_CHK_PC_1 (SPM_BASE + 0x91C) 442 #define SPM_ACK_CHK_SEL_1 (SPM_BASE + 0x920) 443 #define SPM_ACK_CHK_TIMER_1 (SPM_BASE + 0x924) 444 #define SPM_ACK_CHK_STA_1 (SPM_BASE + 0x928) 445 #define SPM_ACK_CHK_SWINT_1 (SPM_BASE + 0x92C) 446 #define SPM_ACK_CHK_CON_2 (SPM_BASE + 0x930) 447 #define SPM_ACK_CHK_PC_2 (SPM_BASE + 0x934) 448 #define SPM_ACK_CHK_SEL_2 (SPM_BASE + 0x938) 449 #define SPM_ACK_CHK_TIMER_2 (SPM_BASE + 0x93C) 450 #define SPM_ACK_CHK_STA_2 (SPM_BASE + 0x940) 451 #define SPM_ACK_CHK_SWINT_2 (SPM_BASE + 0x944) 452 #define SPM_ACK_CHK_CON_3 (SPM_BASE + 0x948) 453 #define SPM_ACK_CHK_PC_3 (SPM_BASE + 0x94C) 454 #define SPM_ACK_CHK_SEL_3 (SPM_BASE + 0x950) 455 #define SPM_ACK_CHK_TIMER_3 (SPM_BASE + 0x954) 456 #define SPM_ACK_CHK_STA_3 (SPM_BASE + 0x958) 457 #define SPM_ACK_CHK_SWINT_3 (SPM_BASE + 0x95C) 458 #define SPM_COUNTER_0 (SPM_BASE + 0x960) 459 #define SPM_COUNTER_1 (SPM_BASE + 0x964) 460 #define SPM_COUNTER_2 (SPM_BASE + 0x968) 461 #define SYS_TIMER_CON (SPM_BASE + 0x96C) 462 #define SPM_TWAM_CON (SPM_BASE + 0x970) 463 #define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x974) 464 #define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x978) 465 #define SPM_TWAM_EVENT_CLEAR (SPM_BASE + 0x97C) 466 #define OPP0_TABLE (SPM_BASE + 0x980) 467 #define OPP1_TABLE (SPM_BASE + 0x984) 468 #define OPP2_TABLE (SPM_BASE + 0x988) 469 #define OPP3_TABLE (SPM_BASE + 0x98C) 470 #define OPP4_TABLE (SPM_BASE + 0x990) 471 #define OPP5_TABLE (SPM_BASE + 0x994) 472 #define OPP6_TABLE (SPM_BASE + 0x998) 473 #define OPP7_TABLE (SPM_BASE + 0x99C) 474 #define OPP8_TABLE (SPM_BASE + 0x9A0) 475 #define OPP9_TABLE (SPM_BASE + 0x9A4) 476 #define OPP10_TABLE (SPM_BASE + 0x9A8) 477 #define OPP11_TABLE (SPM_BASE + 0x9AC) 478 #define OPP12_TABLE (SPM_BASE + 0x9B0) 479 #define OPP13_TABLE (SPM_BASE + 0x9B4) 480 #define OPP14_TABLE (SPM_BASE + 0x9B8) 481 #define OPP15_TABLE (SPM_BASE + 0x9BC) 482 #define OPP16_TABLE (SPM_BASE + 0x9C0) 483 #define OPP17_TABLE (SPM_BASE + 0x9C4) 484 #define SHU0_ARRAY (SPM_BASE + 0x9C8) 485 #define SHU1_ARRAY (SPM_BASE + 0x9CC) 486 #define SHU2_ARRAY (SPM_BASE + 0x9D0) 487 #define SHU3_ARRAY (SPM_BASE + 0x9D4) 488 #define SHU4_ARRAY (SPM_BASE + 0x9D8) 489 #define SHU5_ARRAY (SPM_BASE + 0x9DC) 490 #define SHU6_ARRAY (SPM_BASE + 0x9E0) 491 #define SHU7_ARRAY (SPM_BASE + 0x9E4) 492 #define SHU8_ARRAY (SPM_BASE + 0x9E8) 493 #define SHU9_ARRAY (SPM_BASE + 0x9EC) 494 495 /* POWERON_CONFIG_EN (0x10006000 + 0x000) */ 496 #define BCLK_CG_EN_LSB (1U << 0) /* 1b */ 497 #define PROJECT_CODE_LSB (1U << 16) /* 16b */ 498 499 /* SPM_POWER_ON_VAL0 (0x10006000 + 0x004) */ 500 #define POWER_ON_VAL0_LSB (1U << 0) /* 32b */ 501 502 /* SPM_POWER_ON_VAL1 (0x10006000 + 0x008) */ 503 #define POWER_ON_VAL1_LSB (1U << 0) /* 32b */ 504 505 /* SPM_CLK_CON (0x10006000 + 0x00C) */ 506 #define REG_SRCCLKEN0_CTL_LSB (1U << 0) /* 2b */ 507 #define REG_SRCCLKEN1_CTL_LSB (1U << 2) /* 2b */ 508 #define RC_SW_SRCCLKEN_RC (1U << 3) /* 1b */ 509 #define RC_SW_SRCCLKEN_FPM (1U << 4) /* 1b */ 510 #define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */ 511 #define REG_SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */ 512 #define REG_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */ 513 #define REG_MD1_C32RM_EN_LSB (1U << 9) /* 1b */ 514 #define REG_MD2_C32RM_EN_LSB (1U << 10) /* 1b */ 515 #define REG_CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */ 516 #define REG_CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */ 517 #define REG_SRCCLKEN0_EN_LSB (1U << 13) /* 1b */ 518 #define REG_SRCCLKEN1_EN_LSB (1U << 14) /* 1b */ 519 #define SCP_DCM_EN_LSB (1U << 15) /* 1b */ 520 #define REG_SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 8b */ 521 #define REG_SYSCLK1_SRC_MASK_B_LSB (1U << 24) /* 8b */ 522 523 /* SPM_CLK_SETTLE (0x10006000 + 0x010) */ 524 #define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */ 525 526 /* SPM_AP_STANDBY_CON (0x10006000 + 0x014) */ 527 #define REG_WFI_OP_LSB (1U << 0) /* 1b */ 528 #define REG_WFI_TYPE_LSB (1U << 1) /* 1b */ 529 #define REG_MP0_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */ 530 #define REG_MP1_CPUTOP_IDLE_MASK_LSB (1U << 3) /* 1b */ 531 #define REG_MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */ 532 #define REG_MD_APSRC_1_SEL_LSB (1U << 25) /* 1b */ 533 #define REG_MD_APSRC_0_SEL_LSB (1U << 26) /* 1b */ 534 #define REG_CONN_APSRC_SEL_LSB (1U << 29) /* 1b */ 535 536 /* PCM_CON0 (0x10006000 + 0x018) */ 537 #define PCM_CK_EN_LSB (1U << 2) /* 1b */ 538 #define RG_EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */ 539 #define PCM_CK_FROM_CKSYS_LSB (1U << 4) /* 1b */ 540 #define PCM_SW_RESET_LSB (1U << 15) /* 1b */ 541 #define PCM_CON0_PROJECT_CODE_LSB (1U << 16) /* 16b */ 542 543 /* PCM_CON1 (0x10006000 + 0x01C) */ 544 #define REG_IM_SLEEP_EN_LSB (1U << 1) /* 1b */ 545 #define REG_SPM_SRAM_CTRL_MUX_LSB (1U << 2) /* 1b */ 546 #define RG_AHBMIF_APBEN_LSB (1U << 3) /* 1b */ 547 #define RG_PCM_TIMER_EN_LSB (1U << 5) /* 1b */ 548 #define REG_SPM_EVENT_COUNTER_CLR_LSB (1U << 6) /* 1b */ 549 #define RG_DIS_MIF_PROT_LSB (1U << 7) /* 1b */ 550 #define RG_PCM_WDT_EN_LSB (1U << 8) /* 1b */ 551 #define RG_PCM_WDT_WAKE_LSB (1U << 9) /* 1b */ 552 #define SPM_LEAVE_SUSPEND_MERGE_MASK_LSB (1U << 10) /* 1b */ 553 #define REG_SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */ 554 #define REG_MD32_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */ 555 #define RG_PCM_IRQ_MSK_LSB (1U << 15) /* 1b */ 556 #define PCM_CON1_PROJECT_CODE_LSB (1U << 16) /* 16b */ 557 558 /* SPM_POWER_ON_VAL2 (0x10006000 + 0x020) */ 559 #define POWER_ON_VAL2_LSB (1U << 0) /* 32b */ 560 561 /* SPM_POWER_ON_VAL3 (0x10006000 + 0x024) */ 562 #define POWER_ON_VAL3_LSB (1U << 0) /* 32b */ 563 564 /* PCM_REG_DATA_INI (0x10006000 + 0x028) */ 565 #define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */ 566 567 /* PCM_PWR_IO_EN (0x10006000 + 0x02C) */ 568 #define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */ 569 #define RG_RF_SYNC_EN_LSB (1U << 16) /* 8b */ 570 571 /* PCM_TIMER_VAL (0x10006000 + 0x030) */ 572 #define REG_PCM_TIMER_VAL_LSB (1U << 0) /* 32b */ 573 574 /* PCM_WDT_VAL (0x10006000 + 0x034) */ 575 #define RG_PCM_WDT_VAL_LSB (1U << 0) /* 32b */ 576 577 /* SPM_SW_RST_CON (0x10006000 + 0x040) */ 578 #define SPM_SW_RST_CON_LSB (1U << 0) /* 16b */ 579 #define SPM_SW_RST_CON_PROJECT_CODE_LSB (1U << 16) /* 16b */ 580 581 /* SPM_SW_RST_CON_SET (0x10006000 + 0x044) */ 582 #define SPM_SW_RST_CON_SET_LSB (1U << 0) /* 16b */ 583 #define SPM_SW_RST_CON_SET_PROJECT_CODE_LSB (1U << 16) /* 16b */ 584 585 /* SPM_SW_RST_CON_CLR (0x10006000 + 0x048) */ 586 #define SPM_SW_RST_CON_CLR_LSB (1U << 0) /* 16b */ 587 #define SPM_SW_RST_CON_CLR_PROJECT_CODE_LSB (1U << 16) /* 16b */ 588 589 /* SPM_SRC6_MASK (0x10006000 + 0x04C) */ 590 #define REG_CCIF_EVENT_INFRA_REQ_MASK_B_LSB (1U << 0) /* 16b */ 591 #define REG_CCIF_EVENT_APSRC_REQ_MASK_B_LSB (1U << 16) /* 16b */ 592 593 /* MD32_CLK_CON (0x10006000 + 0x084) */ 594 #define REG_MD32_26M_CK_SEL_LSB (1U << 0) /* 1b */ 595 #define REG_MD32_DCM_EN_LSB (1U << 1) /* 1b */ 596 597 /* SPM_SRAM_RSV_CON (0x10006000 + 0x088) */ 598 #define SPM_SRAM_SLEEP_B_ECO_EN_LSB (1U << 0) /* 1b */ 599 600 /* SPM_SWINT (0x10006000 + 0x08C) */ 601 #define SPM_SWINT_LSB (1U << 0) /* 32b */ 602 603 /* SPM_SWINT_SET (0x10006000 + 0x090) */ 604 #define SPM_SWINT_SET_LSB (1U << 0) /* 32b */ 605 606 /* SPM_SWINT_CLR (0x10006000 + 0x094) */ 607 #define SPM_SWINT_CLR_LSB (1U << 0) /* 32b */ 608 609 /* SPM_SCP_MAILBOX (0x10006000 + 0x098) */ 610 #define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */ 611 612 /* SCP_SPM_MAILBOX (0x10006000 + 0x09C) */ 613 #define SCP_SPM_MAILBOX_LSB (1U << 0) /* 32b */ 614 615 /* SPM_WAKEUP_EVENT_SENS (0x10006000 + 0x0A0) */ 616 #define REG_WAKEUP_EVENT_SENS_LSB (1U << 0) /* 32b */ 617 618 /* SPM_WAKEUP_EVENT_CLEAR (0x10006000 + 0x0A4) */ 619 #define REG_WAKEUP_EVENT_CLR_LSB (1U << 0) /* 32b */ 620 621 /* SPM_SCP_IRQ (0x10006000 + 0x0AC) */ 622 #define SC_SPM2SCP_WAKEUP_LSB (1U << 0) /* 1b */ 623 #define SC_SCP2SPM_WAKEUP_LSB (1U << 4) /* 1b */ 624 625 /* SPM_CPU_WAKEUP_EVENT (0x10006000 + 0x0B0) */ 626 #define REG_CPU_WAKEUP_LSB (1U << 0) /* 1b */ 627 628 /* SPM_IRQ_MASK (0x10006000 + 0x0B4) */ 629 #define REG_SPM_IRQ_MASK_LSB (1U << 0) /* 32b */ 630 631 /* SPM_SRC_REQ (0x10006000 + 0x0B8) */ 632 #define REG_SPM_APSRC_REQ_LSB (1U << 0) /* 1b */ 633 #define REG_SPM_F26M_REQ_LSB (1U << 1) /* 1b */ 634 #define REG_SPM_INFRA_REQ_LSB (1U << 3) /* 1b */ 635 #define REG_SPM_VRF18_REQ_LSB (1U << 4) /* 1b */ 636 #define REG_SPM_DDREN_REQ_LSB (1U << 7) /* 1b */ 637 #define REG_SPM_DVFS_REQ_LSB (1U << 8) /* 1b */ 638 #define REG_SPM_SW_MAILBOX_REQ_LSB (1U << 9) /* 1b */ 639 #define REG_SPM_SSPM_MAILBOX_REQ_LSB (1U << 10) /* 1b */ 640 #define REG_SPM_ADSP_MAILBOX_REQ_LSB (1U << 11) /* 1b */ 641 #define REG_SPM_SCP_MAILBOX_REQ_LSB (1U << 12) /* 1b */ 642 643 /* SPM_SRC_MASK (0x10006000 + 0x0BC) */ 644 #define REG_MD_0_SRCCLKENA_MASK_B_LSB (1U << 0) /* 1b */ 645 #define REG_MD_0_INFRA_REQ_MASK_B_LSB (1U << 1) /* 1b */ 646 #define REG_MD_0_APSRC_REQ_MASK_B_LSB (1U << 2) /* 1b */ 647 #define REG_MD_0_VRF18_REQ_MASK_B_LSB (1U << 3) /* 1b */ 648 #define REG_MD_0_DDREN_REQ_MASK_B_LSB (1U << 4) /* 1b */ 649 #define REG_MD_1_SRCCLKENA_MASK_B_LSB (1U << 5) /* 1b */ 650 #define REG_MD_1_INFRA_REQ_MASK_B_LSB (1U << 6) /* 1b */ 651 #define REG_MD_1_APSRC_REQ_MASK_B_LSB (1U << 7) /* 1b */ 652 #define REG_MD_1_VRF18_REQ_MASK_B_LSB (1U << 8) /* 1b */ 653 #define REG_MD_1_DDREN_REQ_MASK_B_LSB (1U << 9) /* 1b */ 654 #define REG_CONN_SRCCLKENA_MASK_B_LSB (1U << 10) /* 1b */ 655 #define REG_CONN_SRCCLKENB_MASK_B_LSB (1U << 11) /* 1b */ 656 #define REG_CONN_INFRA_REQ_MASK_B_LSB (1U << 12) /* 1b */ 657 #define REG_CONN_APSRC_REQ_MASK_B_LSB (1U << 13) /* 1b */ 658 #define REG_CONN_VRF18_REQ_MASK_B_LSB (1U << 14) /* 1b */ 659 #define REG_CONN_DDREN_REQ_MASK_B_LSB (1U << 15) /* 1b */ 660 #define REG_CONN_VFE28_MASK_B_LSB (1U << 16) /* 1b */ 661 #define REG_SRCCLKENI_SRCCLKENA_MASK_B_LSB (1U << 17) /* 3b */ 662 #define REG_SRCCLKENI_INFRA_REQ_MASK_B_LSB (1U << 20) /* 3b */ 663 #define REG_INFRASYS_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ 664 #define REG_INFRASYS_DDREN_REQ_MASK_B_LSB (1U << 26) /* 1b */ 665 #define REG_SSPM_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */ 666 #define REG_SSPM_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */ 667 #define REG_SSPM_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */ 668 #define REG_SSPM_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */ 669 #define REG_SSPM_DDREN_REQ_MASK_B_LSB (1U << 31) /* 1b */ 670 671 /* SPM_SRC2_MASK (0x10006000 + 0x0C0) */ 672 #define REG_SCP_SRCCLKENA_MASK_B_LSB (1U << 0) /* 1b */ 673 #define REG_SCP_INFRA_REQ_MASK_B_LSB (1U << 1) /* 1b */ 674 #define REG_SCP_APSRC_REQ_MASK_B_LSB (1U << 2) /* 1b */ 675 #define REG_SCP_VRF18_REQ_MASK_B_LSB (1U << 3) /* 1b */ 676 #define REG_SCP_DDREN_REQ_MASK_B_LSB (1U << 4) /* 1b */ 677 #define REG_AUDIO_DSP_SRCCLKENA_MASK_B_LSB (1U << 5) /* 1b */ 678 #define REG_AUDIO_DSP_INFRA_REQ_MASK_B_LSB (1U << 6) /* 1b */ 679 #define REG_AUDIO_DSP_APSRC_REQ_MASK_B_LSB (1U << 7) /* 1b */ 680 #define REG_AUDIO_DSP_VRF18_REQ_MASK_B_LSB (1U << 8) /* 1b */ 681 #define REG_AUDIO_DSP_DDREN_REQ_MASK_B_LSB (1U << 9) /* 1b */ 682 #define REG_UFS_SRCCLKENA_MASK_B_LSB (1U << 10) /* 1b */ 683 #define REG_UFS_INFRA_REQ_MASK_B_LSB (1U << 11) /* 1b */ 684 #define REG_UFS_APSRC_REQ_MASK_B_LSB (1U << 12) /* 1b */ 685 #define REG_UFS_VRF18_REQ_MASK_B_LSB (1U << 13) /* 1b */ 686 #define REG_UFS_DDREN_REQ_MASK_B_LSB (1U << 14) /* 1b */ 687 #define REG_DISP0_APSRC_REQ_MASK_B_LSB (1U << 15) /* 1b */ 688 #define REG_DISP0_DDREN_REQ_MASK_B_LSB (1U << 16) /* 1b */ 689 #define REG_DISP1_APSRC_REQ_MASK_B_LSB (1U << 17) /* 1b */ 690 #define REG_DISP1_DDREN_REQ_MASK_B_LSB (1U << 18) /* 1b */ 691 #define REG_GCE_INFRA_REQ_MASK_B_LSB (1U << 19) /* 1b */ 692 #define REG_GCE_APSRC_REQ_MASK_B_LSB (1U << 20) /* 1b */ 693 #define REG_GCE_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */ 694 #define REG_GCE_DDREN_REQ_MASK_B_LSB (1U << 22) /* 1b */ 695 #define REG_APU_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */ 696 #define REG_APU_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */ 697 #define REG_APU_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ 698 #define REG_APU_VRF18_REQ_MASK_B_LSB (1U << 26) /* 1b */ 699 #define REG_APU_DDREN_REQ_MASK_B_LSB (1U << 27) /* 1b */ 700 #define REG_CG_CHECK_SRCCLKENA_MASK_B_LSB (1U << 28) /* 1b */ 701 #define REG_CG_CHECK_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */ 702 #define REG_CG_CHECK_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */ 703 #define REG_CG_CHECK_DDREN_REQ_MASK_B_LSB (1U << 31) /* 1b */ 704 705 /* SPM_SRC3_MASK (0x10006000 + 0x0C4) */ 706 #define REG_DVFSRC_EVENT_TRIGGER_MASK_B_LSB (1U << 0) /* 1b */ 707 #define REG_SW2SPM_WAKEUP_MASK_B_LSB (1U << 1) /* 4b */ 708 #define REG_ADSP2SPM_WAKEUP_MASK_B_LSB (1U << 5) /* 1b */ 709 #define REG_SSPM2SPM_WAKEUP_MASK_B_LSB (1U << 6) /* 4b */ 710 #define REG_SCP2SPM_WAKEUP_MASK_B_LSB (1U << 10) /* 1b */ 711 #define REG_CSYSPWRUP_ACK_MASK_LSB (1U << 11) /* 1b */ 712 #define REG_SPM_RESERVED_SRCCLKENA_MASK_B_LSB (1U << 12) /* 1b */ 713 #define REG_SPM_RESERVED_INFRA_REQ_MASK_B_LSB (1U << 13) /* 1b */ 714 #define REG_SPM_RESERVED_APSRC_REQ_MASK_B_LSB (1U << 14) /* 1b */ 715 #define REG_SPM_RESERVED_VRF18_REQ_MASK_B_LSB (1U << 15) /* 1b */ 716 #define REG_SPM_RESERVED_DDREN_REQ_MASK_B_LSB (1U << 16) /* 1b */ 717 #define REG_MCUPM_SRCCLKENA_MASK_B_LSB (1U << 17) /* 1b */ 718 #define REG_MCUPM_INFRA_REQ_MASK_B_LSB (1U << 18) /* 1b */ 719 #define REG_MCUPM_APSRC_REQ_MASK_B_LSB (1U << 19) /* 1b */ 720 #define REG_MCUPM_VRF18_REQ_MASK_B_LSB (1U << 20) /* 1b */ 721 #define REG_MCUPM_DDREN_REQ_MASK_B_LSB (1U << 21) /* 1b */ 722 #define REG_MSDC0_SRCCLKENA_MASK_B_LSB (1U << 22) /* 1b */ 723 #define REG_MSDC0_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */ 724 #define REG_MSDC0_APSRC_REQ_MASK_B_LSB (1U << 24) /* 1b */ 725 #define REG_MSDC0_VRF18_REQ_MASK_B_LSB (1U << 25) /* 1b */ 726 #define REG_MSDC0_DDREN_REQ_MASK_B_LSB (1U << 26) /* 1b */ 727 #define REG_MSDC1_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */ 728 #define REG_MSDC1_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */ 729 #define REG_MSDC1_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */ 730 #define REG_MSDC1_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */ 731 #define REG_MSDC1_DDREN_REQ_MASK_B_LSB (1U << 31) /* 1b */ 732 733 /* SPM_SRC4_MASK (0x10006000 + 0x0C8) */ 734 #define REG_CCIF_EVENT_SRCCLKENA_MASK_B_LSB (1U << 0) /* 16b */ 735 #define REG_BAK_PSRI_SRCCLKENA_MASK_B_LSB (1U << 16) /* 1b */ 736 #define REG_BAK_PSRI_INFRA_REQ_MASK_B_LSB (1U << 17) /* 1b */ 737 #define REG_BAK_PSRI_APSRC_REQ_MASK_B_LSB (1U << 18) /* 1b */ 738 #define REG_BAK_PSRI_VRF18_REQ_MASK_B_LSB (1U << 19) /* 1b */ 739 #define REG_BAK_PSRI_DDREN_REQ_MASK_B_LSB (1U << 20) /* 1b */ 740 #define REG_DRAMC_MD32_INFRA_REQ_MASK_B_LSB (1U << 21) /* 2b */ 741 #define REG_DRAMC_MD32_VRF18_REQ_MASK_B_LSB (1U << 23) /* 2b */ 742 #define REG_CONN_SRCCLKENB2PWRAP_MASK_B_LSB (1U << 25) /* 1b */ 743 #define REG_DRAMC_MD32_APSRC_REQ_MASK_B_LSB (1U << 26) /* 2b */ 744 745 /* SPM_SRC5_MASK (0x10006000 + 0x0CC) */ 746 #define REG_MCUSYS_MERGE_APSRC_REQ_MASK_B_LSB (1U << 0) /* 9b */ 747 #define REG_MCUSYS_MERGE_DDREN_REQ_MASK_B_LSB (1U << 9) /* 9b */ 748 #define REG_AFE_SRCCLKENA_MASK_B_LSB (1U << 18) /* 1b */ 749 #define REG_AFE_INFRA_REQ_MASK_B_LSB (1U << 19) /* 1b */ 750 #define REG_AFE_APSRC_REQ_MASK_B_LSB (1U << 20) /* 1b */ 751 #define REG_AFE_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */ 752 #define REG_AFE_DDREN_REQ_MASK_B_LSB (1U << 22) /* 1b */ 753 #define REG_MSDC2_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */ 754 #define REG_MSDC2_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */ 755 #define REG_MSDC2_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ 756 #define REG_MSDC2_VRF18_REQ_MASK_B_LSB (1U << 26) /* 1b */ 757 #define REG_MSDC2_DDREN_REQ_MASK_B_LSB (1U << 27) /* 1b */ 758 /* SPM_WAKEUP_EVENT_MASK (0x10006000 + 0x0D0) */ 759 #define REG_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */ 760 761 /* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000 + 0x0D4) */ 762 #define REG_EXT_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */ 763 764 /* SPM_SRC7_MASK (0x10006000 + 0x0D8) */ 765 #define REG_PCIE_SRCCLKENA_MASK_B_LSB (1U << 0) /* 1b */ 766 #define REG_PCIE_INFRA_REQ_MASK_B_LSB (1U << 1) /* 1b */ 767 #define REG_PCIE_APSRC_REQ_MASK_B_LSB (1U << 2) /* 1b */ 768 #define REG_PCIE_VRF18_REQ_MASK_B_LSB (1U << 3) /* 1b */ 769 #define REG_PCIE_DDREN_REQ_MASK_B_LSB (1U << 4) /* 1b */ 770 #define REG_DPMAIF_SRCCLKENA_MASK_B_LSB (1U << 5) /* 1b */ 771 #define REG_DPMAIF_INFRA_REQ_MASK_B_LSB (1U << 6) /* 1b */ 772 #define REG_DPMAIF_APSRC_REQ_MASK_B_LSB (1U << 7) /* 1b */ 773 #define REG_DPMAIF_VRF18_REQ_MASK_B_LSB (1U << 8) /* 1b */ 774 #define REG_DPMAIF_DDREN_REQ_MASK_B_LSB (1U << 9) /* 1b */ 775 776 /* SCP_CLK_CON (0x10006000 + 0x0DC) */ 777 #define REG_SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */ 778 #define REG_SCP_DCM_EN_LSB (1U << 1) /* 1b */ 779 #define SCP_SECURE_VREQ_MASK_LSB (1U << 2) /* 1b */ 780 #define SCP_SLP_REQ_LSB (1U << 3) /* 1b */ 781 #define SCP_SLP_ACK_LSB (1U << 4) /* 1b */ 782 783 /* PCM_DEBUG_CON (0x10006000 + 0x0E0) */ 784 #define PCM_DEBUG_OUT_ENABLE_LSB (1U << 0) /* 1b */ 785 786 /* DDREN_DBC_CON (0x10006000 + 0x0E8) */ 787 #define REG_DDREN_DBC_LEN_LSB (1U << 0) /* 10b */ 788 #define REG_DDREN_DBC_EN_LSB (1U << 16) /* 1b */ 789 790 /* SPM_RESOURCE_ACK_CON4 (0x10006000 + 0x0EC) */ 791 #define REG_DPMAIF_SRCCLKENA_ACK_MASK_LSB (1U << 0) /* 1b */ 792 #define REG_DPMAIF_INFRA_ACK_MASK_LSB (1U << 1) /* 1b */ 793 #define REG_DPMAIF_APSRC_ACK_MASK_LSB (1U << 2) /* 1b */ 794 #define REG_DPMAIF_VRF18_ACK_MASK_LSB (1U << 3) /* 1b */ 795 #define REG_DPMAIF_DDREN_ACK_MASK_LSB (1U << 4) /* 1b */ 796 797 /* SPM_RESOURCE_ACK_CON0 (0x10006000 + 0x0F0) */ 798 #define REG_MD_0_SRCCLKENA_ACK_MASK_LSB (1U << 0) /* 1b */ 799 #define REG_MD_0_INFRA_ACK_MASK_LSB (1U << 1) /* 1b */ 800 #define REG_MD_0_APSRC_ACK_MASK_LSB (1U << 2) /* 1b */ 801 #define REG_MD_0_VRF18_ACK_MASK_LSB (1U << 3) /* 1b */ 802 #define REG_MD_0_DDREN_ACK_MASK_LSB (1U << 4) /* 1b */ 803 #define REG_MD_1_SRCCLKENA_ACK_MASK_LSB (1U << 5) /* 1b */ 804 #define REG_MD_1_INFRA_ACK_MASK_LSB (1U << 6) /* 1b */ 805 #define REG_MD_1_APSRC_ACK_MASK_LSB (1U << 7) /* 1b */ 806 #define REG_MD_1_VRF18_ACK_MASK_LSB (1U << 8) /* 1b */ 807 #define REG_MD_1_DDREN_ACK_MASK_LSB (1U << 9) /* 1b */ 808 #define REG_CONN_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */ 809 #define REG_CONN_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */ 810 #define REG_CONN_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */ 811 #define REG_CONN_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */ 812 #define REG_CONN_DDREN_ACK_MASK_LSB (1U << 14) /* 1b */ 813 #define REG_SSPM_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */ 814 #define REG_SSPM_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */ 815 #define REG_SSPM_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */ 816 #define REG_SSPM_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */ 817 #define REG_SSPM_DDREN_ACK_MASK_LSB (1U << 19) /* 1b */ 818 #define REG_SCP_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */ 819 #define REG_SCP_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */ 820 #define REG_SCP_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */ 821 #define REG_SCP_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */ 822 #define REG_SCP_DDREN_ACK_MASK_LSB (1U << 24) /* 1b */ 823 #define REG_AUDIO_DSP_SRCCLKENA_ACK_MASK_LSB (1U << 25) /* 1b */ 824 #define REG_AUDIO_DSP_INFRA_ACK_MASK_LSB (1U << 26) /* 1b */ 825 #define REG_AUDIO_DSP_APSRC_ACK_MASK_LSB (1U << 27) /* 1b */ 826 #define REG_AUDIO_DSP_VRF18_ACK_MASK_LSB (1U << 28) /* 1b */ 827 #define REG_AUDIO_DSP_DDREN_ACK_MASK_LSB (1U << 29) /* 1b */ 828 #define REG_DISP0_DDREN_ACK_MASK_LSB (1U << 30) /* 1b */ 829 #define REG_DISP1_APSRC_ACK_MASK_LSB (1U << 31) /* 1b */ 830 831 /* SPM_RESOURCE_ACK_CON1 (0x10006000 + 0x0F4) */ 832 #define REG_UFS_SRCCLKENA_ACK_MASK_LSB (1U << 0) /* 1b */ 833 #define REG_UFS_INFRA_ACK_MASK_LSB (1U << 1) /* 1b */ 834 #define REG_UFS_APSRC_ACK_MASK_LSB (1U << 2) /* 1b */ 835 #define REG_UFS_VRF18_ACK_MASK_LSB (1U << 3) /* 1b */ 836 #define REG_UFS_DDREN_ACK_MASK_LSB (1U << 4) /* 1b */ 837 #define REG_APU_SRCCLKENA_ACK_MASK_LSB (1U << 5) /* 1b */ 838 #define REG_APU_INFRA_ACK_MASK_LSB (1U << 6) /* 1b */ 839 #define REG_APU_APSRC_ACK_MASK_LSB (1U << 7) /* 1b */ 840 #define REG_APU_VRF18_ACK_MASK_LSB (1U << 8) /* 1b */ 841 #define REG_APU_DDREN_ACK_MASK_LSB (1U << 9) /* 1b */ 842 #define REG_MCUPM_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */ 843 #define REG_MCUPM_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */ 844 #define REG_MCUPM_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */ 845 #define REG_MCUPM_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */ 846 #define REG_MCUPM_DDREN_ACK_MASK_LSB (1U << 14) /* 1b */ 847 #define REG_MSDC0_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */ 848 #define REG_MSDC0_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */ 849 #define REG_MSDC0_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */ 850 #define REG_MSDC0_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */ 851 #define REG_MSDC0_DDREN_ACK_MASK_LSB (1U << 19) /* 1b */ 852 #define REG_MSDC1_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */ 853 #define REG_MSDC1_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */ 854 #define REG_MSDC1_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */ 855 #define REG_MSDC1_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */ 856 #define REG_MSDC1_DDREN_ACK_MASK_LSB (1U << 24) /* 1b */ 857 #define REG_DISP0_APSRC_ACK_MASK_LSB (1U << 25) /* 1b */ 858 #define REG_DISP1_DDREN_ACK_MASK_LSB (1U << 26) /* 1b */ 859 #define REG_GCE_INFRA_ACK_MASK_LSB (1U << 27) /* 1b */ 860 #define REG_GCE_APSRC_ACK_MASK_LSB (1U << 28) /* 1b */ 861 #define REG_GCE_VRF18_ACK_MASK_LSB (1U << 29) /* 1b */ 862 #define REG_GCE_DDREN_ACK_MASK_LSB (1U << 30) /* 1b */ 863 864 /* SPM_RESOURCE_ACK_CON2 (0x10006000 + 0x0F8) */ 865 #define SPM_SRCCLKENA_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */ 866 #define SPM_INFRA_ACK_WAIT_CYCLE_LSB (1U << 8) /* 8b */ 867 #define SPM_APSRC_ACK_WAIT_CYCLE_LSB (1U << 16) /* 8b */ 868 #define SPM_VRF18_ACK_WAIT_CYCLE_LSB (1U << 24) /* 8b */ 869 870 /* SPM_RESOURCE_ACK_CON3 (0x10006000 + 0x0FC) */ 871 #define SPM_DDREN_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */ 872 #define REG_BAK_PSRI_SRCCLKENA_ACK_MASK_LSB (1U << 8) /* 1b */ 873 #define REG_BAK_PSRI_INFRA_ACK_MASK_LSB (1U << 9) /* 1b */ 874 #define REG_BAK_PSRI_APSRC_ACK_MASK_LSB (1U << 10) /* 1b */ 875 #define REG_BAK_PSRI_VRF18_ACK_MASK_LSB (1U << 11) /* 1b */ 876 #define REG_BAK_PSRI_DDREN_ACK_MASK_LSB (1U << 12) /* 1b */ 877 #define REG_AFE_SRCCLKENA_ACK_MASK_LSB (1U << 13) /* 1b */ 878 #define REG_AFE_INFRA_ACK_MASK_LSB (1U << 14) /* 1b */ 879 #define REG_AFE_APSRC_ACK_MASK_LSB (1U << 15) /* 1b */ 880 #define REG_AFE_VRF18_ACK_MASK_LSB (1U << 16) /* 1b */ 881 #define REG_AFE_DDREN_ACK_MASK_LSB (1U << 17) /* 1b */ 882 #define REG_MSDC2_SRCCLKENA_ACK_MASK_LSB (1U << 18) /* 1b */ 883 #define REG_MSDC2_INFRA_ACK_MASK_LSB (1U << 19) /* 1b */ 884 #define REG_MSDC2_APSRC_ACK_MASK_LSB (1U << 20) /* 1b */ 885 #define REG_MSDC2_VRF18_ACK_MASK_LSB (1U << 21) /* 1b */ 886 #define REG_MSDC2_DDREN_ACK_MASK_LSB (1U << 22) /* 1b */ 887 #define REG_PCIE_SRCCLKENA_ACK_MASK_LSB (1U << 23) /* 1b */ 888 #define REG_PCIE_INFRA_ACK_MASK_LSB (1U << 24) /* 1b */ 889 #define REG_PCIE_APSRC_ACK_MASK_LSB (1U << 25) /* 1b */ 890 #define REG_PCIE_VRF18_ACK_MASK_LSB (1U << 26) /* 1b */ 891 #define REG_PCIE_DDREN_ACK_MASK_LSB (1U << 27) /* 1b */ 892 893 /* PCM_REG0_DATA (0x10006000 + 0x100) */ 894 #define PCM_REG0_RF_LSB (1U << 0) /* 32b */ 895 896 /* PCM_REG2_DATA (0x10006000 + 0x104) */ 897 #define PCM_REG2_RF_LSB (1U << 0) /* 32b */ 898 899 /* PCM_REG6_DATA (0x10006000 + 0x108) */ 900 #define PCM_REG6_RF_LSB (1U << 0) /* 32b */ 901 902 /* PCM_REG7_DATA (0x10006000 + 0x10C) */ 903 #define PCM_REG7_RF_LSB (1U << 0) /* 32b */ 904 905 /* PCM_REG13_DATA (0x10006000 + 0x110) */ 906 #define PCM_REG13_RF_LSB (1U << 0) /* 32b */ 907 908 /* SRC_REQ_STA_0 (0x10006000 + 0x114) */ 909 #define MD_0_SRCCLKENA_LSB (1U << 0) /* 1b */ 910 #define MD_0_INFRA_REQ_LSB (1U << 1) /* 1b */ 911 #define MD_0_APSRC_REQ_LSB (1U << 2) /* 1b */ 912 #define MD_0_VRF18_REQ_LSB (1U << 4) /* 1b */ 913 #define MD_0_DDREN_REQ_LSB (1U << 5) /* 1b */ 914 #define MD_1_SRCCLKENA_LSB (1U << 6) /* 1b */ 915 #define MD_1_INFRA_REQ_LSB (1U << 7) /* 1b */ 916 #define MD_1_APSRC_REQ_LSB (1U << 8) /* 1b */ 917 #define MD_1_VRF18_REQ_LSB (1U << 10) /* 1b */ 918 #define MD_1_DDREN_REQ_LSB (1U << 11) /* 1b */ 919 #define CONN_SRCCLKENA_LSB (1U << 12) /* 1b */ 920 #define CONN_SRCCLKENB_LSB (1U << 13) /* 1b */ 921 #define CONN_INFRA_REQ_LSB (1U << 14) /* 1b */ 922 #define CONN_APSRC_REQ_LSB (1U << 15) /* 1b */ 923 #define CONN_VRF18_REQ_LSB (1U << 16) /* 1b */ 924 #define CONN_DDREN_REQ_LSB (1U << 17) /* 1b */ 925 #define SRCCLKENI_LSB (1U << 18) /* 3b */ 926 #define SSPM_SRCCLKENA_LSB (1U << 21) /* 1b */ 927 #define SSPM_INFRA_REQ_LSB (1U << 22) /* 1b */ 928 #define SSPM_APSRC_REQ_LSB (1U << 23) /* 1b */ 929 #define SSPM_VRF18_REQ_LSB (1U << 24) /* 1b */ 930 #define SSPM_DDREN_REQ_LSB (1U << 25) /* 1b */ 931 #define DISP0_APSRC_REQ_LSB (1U << 26) /* 1b */ 932 #define DISP0_DDREN_REQ_LSB (1U << 27) /* 1b */ 933 #define DISP1_APSRC_REQ_LSB (1U << 28) /* 1b */ 934 #define DISP1_DDREN_REQ_LSB (1U << 29) /* 1b */ 935 #define DVFSRC_EVENT_TRIGGER_LSB (1U << 30) /* 1b */ 936 937 /* SRC_REQ_STA_1 (0x10006000 + 0x118) */ 938 #define SCP_SRCCLKENA_LSB (1U << 0) /* 1b */ 939 #define SCP_INFRA_REQ_LSB (1U << 1) /* 1b */ 940 #define SCP_APSRC_REQ_LSB (1U << 2) /* 1b */ 941 #define SCP_VRF18_REQ_LSB (1U << 3) /* 1b */ 942 #define SCP_DDREN_REQ_LSB (1U << 4) /* 1b */ 943 #define AUDIO_DSP_SRCCLKENA_LSB (1U << 5) /* 1b */ 944 #define AUDIO_DSP_INFRA_REQ_LSB (1U << 6) /* 1b */ 945 #define AUDIO_DSP_APSRC_REQ_LSB (1U << 7) /* 1b */ 946 #define AUDIO_DSP_VRF18_REQ_LSB (1U << 8) /* 1b */ 947 #define AUDIO_DSP_DDREN_REQ_LSB (1U << 9) /* 1b */ 948 #define UFS_SRCCLKENA_LSB (1U << 10) /* 1b */ 949 #define UFS_INFRA_REQ_LSB (1U << 11) /* 1b */ 950 #define UFS_APSRC_REQ_LSB (1U << 12) /* 1b */ 951 #define UFS_VRF18_REQ_LSB (1U << 13) /* 1b */ 952 #define UFS_DDREN_REQ_LSB (1U << 14) /* 1b */ 953 #define GCE_INFRA_REQ_LSB (1U << 15) /* 1b */ 954 #define GCE_APSRC_REQ_LSB (1U << 16) /* 1b */ 955 #define GCE_VRF18_REQ_LSB (1U << 17) /* 1b */ 956 #define GCE_DDREN_REQ_LSB (1U << 18) /* 1b */ 957 #define INFRASYS_APSRC_REQ_LSB (1U << 19) /* 1b */ 958 #define INFRASYS_DDREN_REQ_LSB (1U << 20) /* 1b */ 959 #define MSDC0_SRCCLKENA_LSB (1U << 21) /* 1b */ 960 #define MSDC0_INFRA_REQ_LSB (1U << 22) /* 1b */ 961 #define MSDC0_APSRC_REQ_LSB (1U << 23) /* 1b */ 962 #define MSDC0_VRF18_REQ_LSB (1U << 24) /* 1b */ 963 #define MSDC0_DDREN_REQ_LSB (1U << 25) /* 1b */ 964 #define MSDC1_SRCCLKENA_LSB (1U << 26) /* 1b */ 965 #define MSDC1_INFRA_REQ_LSB (1U << 27) /* 1b */ 966 #define MSDC1_APSRC_REQ_LSB (1U << 28) /* 1b */ 967 #define MSDC1_VRF18_REQ_LSB (1U << 29) /* 1b */ 968 #define MSDC1_DDREN_REQ_LSB (1U << 30) /* 1b */ 969 970 /* SRC_REQ_STA_2 (0x10006000 + 0x11C) */ 971 #define MCUSYS_MERGE_DDR_EN_LSB (1U << 0) /* 9b */ 972 #define EMI_SELF_REFRESH_CH_LSB (1U << 9) /* 2b */ 973 #define SW2SPM_WAKEUP_LSB (1U << 11) /* 4b */ 974 #define SC_ADSP2SPM_WAKEUP_LSB (1U << 15) /* 1b */ 975 #define SC_SSPM2SPM_WAKEUP_LSB (1U << 16) /* 4b */ 976 #define SRC_REQ_STA_2_SC_SCP2SPM_WAKEUP_LSB (1U << 20) /* 1b */ 977 #define SPM_RESERVED_SRCCLKENA_LSB (1U << 21) /* 1b */ 978 #define SPM_RESERVED_INFRA_REQ_LSB (1U << 22) /* 1b */ 979 #define SPM_RESERVED_APSRC_REQ_LSB (1U << 23) /* 1b */ 980 #define SPM_RESERVED_VRF18_REQ_LSB (1U << 24) /* 1b */ 981 #define SPM_RESERVED_DDREN_REQ_LSB (1U << 25) /* 1b */ 982 #define MCUPM_SRCCLKENA_LSB (1U << 26) /* 1b */ 983 #define MCUPM_INFRA_REQ_LSB (1U << 27) /* 1b */ 984 #define MCUPM_APSRC_REQ_LSB (1U << 28) /* 1b */ 985 #define MCUPM_VRF18_REQ_LSB (1U << 29) /* 1b */ 986 #define MCUPM_DDREN_REQ_LSB (1U << 30) /* 1b */ 987 988 /* PCM_TIMER_OUT (0x10006000 + 0x120) */ 989 #define PCM_TIMER_LSB (1U << 0) /* 32b */ 990 991 /* PCM_WDT_OUT (0x10006000 + 0x124) */ 992 #define PCM_WDT_TIMER_VAL_OUT_LSB (1U << 0) /* 32b */ 993 994 /* SPM_IRQ_STA (0x10006000 + 0x128) */ 995 #define TWAM_IRQ_LSB (1U << 2) /* 1b */ 996 #define PCM_IRQ_LSB (1U << 3) /* 1b */ 997 998 /* SRC_REQ_STA_4 (0x10006000 + 0x12C) */ 999 #define APU_SRCCLKENA_LSB (1U << 0) /* 1b */ 1000 #define APU_INFRA_REQ_LSB (1U << 1) /* 1b */ 1001 #define APU_APSRC_REQ_LSB (1U << 2) /* 1b */ 1002 #define APU_VRF18_REQ_LSB (1U << 3) /* 1b */ 1003 #define APU_DDREN_REQ_LSB (1U << 4) /* 1b */ 1004 #define BAK_PSRI_SRCCLKENA_LSB (1U << 5) /* 1b */ 1005 #define BAK_PSRI_INFRA_REQ_LSB (1U << 6) /* 1b */ 1006 #define BAK_PSRI_APSRC_REQ_LSB (1U << 7) /* 1b */ 1007 #define BAK_PSRI_VRF18_REQ_LSB (1U << 8) /* 1b */ 1008 #define BAK_PSRI_DDREN_REQ_LSB (1U << 9) /* 1b */ 1009 #define MSDC2_SRCCLKENA_LSB (1U << 10) /* 1b */ 1010 #define MSDC2_INFRA_REQ_LSB (1U << 11) /* 1b */ 1011 #define MSDC2_APSRC_REQ_LSB (1U << 12) /* 1b */ 1012 #define MSDC2_VRF18_REQ_LSB (1U << 13) /* 1b */ 1013 #define MSDC2_DDREN_REQ_LSB (1U << 14) /* 1b */ 1014 #define PCIE_SRCCLKENA_LSB (1U << 15) /* 1b */ 1015 #define PCIE_INFRA_REQ_LSB (1U << 16) /* 1b */ 1016 #define PCIE_APSRC_REQ_LSB (1U << 17) /* 1b */ 1017 #define PCIE_VRF18_REQ_LSB (1U << 18) /* 1b */ 1018 #define PCIE_DDREN_REQ_LSB (1U << 19) /* 1b */ 1019 #define DPMAIF_SRCCLKENA_LSB (1U << 20) /* 1b */ 1020 #define DPMAIF_INFRA_REQ_LSB (1U << 21) /* 1b */ 1021 #define DPMAIF_APSRC_REQ_LSB (1U << 22) /* 1b */ 1022 #define DPMAIF_VRF18_REQ_LSB (1U << 23) /* 1b */ 1023 #define DPMAIF_DDREN_REQ_LSB (1U << 24) /* 1b */ 1024 #define AFE_SRCCLKENA_LSB (1U << 25) /* 1b */ 1025 #define AFE_INFRA_REQ_LSB (1U << 26) /* 1b */ 1026 #define AFE_APSRC_REQ_LSB (1U << 27) /* 1b */ 1027 #define AFE_VRF18_REQ_LSB (1U << 28) /* 1b */ 1028 #define AFE_DDREN_REQ_LSB (1U << 29) /* 1b */ 1029 1030 /* MD32PCM_WAKEUP_STA (0x10006000 + 0x130) */ 1031 #define MD32PCM_WAKEUP_STA_LSB (1U << 0) /* 32b */ 1032 1033 /* MD32PCM_EVENT_STA (0x10006000 + 0x134) */ 1034 #define MD32PCM_EVENT_STA_LSB (1U << 0) /* 32b */ 1035 1036 /* SPM_WAKEUP_STA (0x10006000 + 0x138) */ 1037 #define SPM_WAKEUP_EVENT_L_LSB (1U << 0) /* 32b */ 1038 1039 /* SPM_WAKEUP_EXT_STA (0x10006000 + 0x13C) */ 1040 #define EXT_WAKEUP_EVENT_LSB (1U << 0) /* 32b */ 1041 1042 /* SPM_WAKEUP_MISC (0x10006000 + 0x140) */ 1043 #define GIC_WAKEUP_LSB (1U << 0) /* 10b */ 1044 #define DVFSRC_IRQ_LSB (1U << 16) /* 1b */ 1045 #define SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB (1U << 17) /* 1b */ 1046 #define PCM_TIMER_EVENT_LSB (1U << 18) /* 1b */ 1047 #define PMIC_EINT_OUT_B_LSB (1U << 19) /* 2b */ 1048 #define TWAM_IRQ_B_LSB (1U << 21) /* 1b */ 1049 #define SPM_ACK_CHK_WAKEUP_0_LSB (1U << 25) /* 1b */ 1050 #define SPM_ACK_CHK_WAKEUP_1_LSB (1U << 26) /* 1b */ 1051 #define SPM_ACK_CHK_WAKEUP_2_LSB (1U << 27) /* 1b */ 1052 #define SPM_ACK_CHK_WAKEUP_3_LSB (1U << 28) /* 1b */ 1053 #define SPM_ACK_CHK_WAKEUP_ALL_LSB (1U << 29) /* 1b */ 1054 #define PMIC_IRQ_ACK_LSB (1U << 30) /* 1b */ 1055 #define PMIC_SCP_IRQ_LSB (1U << 31) /* 1b */ 1056 1057 /* MM_DVFS_HALT (0x10006000 + 0x144) */ 1058 #define MM_DVFS_HALT_LSB (1U << 0) /* 5b */ 1059 1060 /* BUS_PROTECT_RDY (0x10006000 + 0x150) */ 1061 #define PROTECT_READY_LSB (1U << 0) /* 32b */ 1062 1063 /* BUS_PROTECT1_RDY (0x10006000 + 0x154) */ 1064 #define PROTECT1_READY_LSB (1U << 0) /* 32b */ 1065 1066 /* BUS_PROTECT2_RDY (0x10006000 + 0x158) */ 1067 #define PROTECT2_READY_LSB (1U << 0) /* 32b */ 1068 /* BUS_PROTECT3_RDY (0x10006000 + 0x15C) */ 1069 1070 #define PROTECT3_READY_LSB (1U << 0) /* 32b */ 1071 /* SUBSYS_IDLE_STA (0x10006000 + 0x160) */ 1072 #define SUBSYS_IDLE_SIGNALS_LSB (1U << 0) /* 32b */ 1073 /* PCM_STA (0x10006000 + 0x164) */ 1074 1075 #define PCM_CK_SEL_O_LSB (1U << 0) /* 4b */ 1076 #define EXT_SRC_STA_LSB (1U << 4) /* 3b */ 1077 1078 /* SRC_REQ_STA_3 (0x10006000 + 0x168) */ 1079 #define CCIF_EVENT_STATE_LSB (1U << 0) /* 1b */ 1080 #define F26M_STATE_LSB (1U << 16) /* 1b */ 1081 #define INFRA_STATE_LSB (1U << 17) /* 1b */ 1082 #define APSRC_STATE_LSB (1U << 18) /* 1b */ 1083 #define VRF18_STATE_LSB (1U << 19) /* 1b */ 1084 #define DDREN_STATE_LSB (1U << 20) /* 1b */ 1085 #define DVFS_STATE_LSB (1U << 21) /* 1b */ 1086 #define SW_MAILBOX_STATE_LSB (1U << 22) /* 1b */ 1087 #define SSPM_MAILBOX_STATE_LSB (1U << 23) /* 1b */ 1088 #define ADSP_MAILBOX_STATE_LSB (1U << 24) /* 1b */ 1089 #define SCP_MAILBOX_STATE_LSB (1U << 25) /* 1b */ 1090 1091 /* PWR_STATUS (0x10006000 + 0x16C) */ 1092 #define PWR_STATUS_LSB (1U << 0) /* 32b */ 1093 1094 /* PWR_STATUS_2ND (0x10006000 + 0x170) */ 1095 #define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ 1096 1097 /* CPU_PWR_STATUS (0x10006000 + 0x174) */ 1098 #define MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 0) /* 1b */ 1099 #define MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 1) /* 1b */ 1100 #define MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 2) /* 1b */ 1101 #define MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 3) /* 1b */ 1102 #define MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 4) /* 1b */ 1103 #define MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 5) /* 1b */ 1104 #define MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 6) /* 1b */ 1105 #define MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 7) /* 1b */ 1106 #define MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 8) /* 1b */ 1107 #define MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 9) /* 1b */ 1108 1109 /* OTHER_PWR_STATUSi (0x10006000 + 0x178) */ 1110 #define OTHER_PWR_STATUS_LSB (1U << 0) /* 32b */ 1111 1112 /* SPM_VTCXO_EVENT_COUNT_STA (0x10006000 + 0x17C) */ 1113 #define SPM_SRCCLKENA_SLEEP_COUNT_LSB (1U << 0) /* 16b */ 1114 #define SPM_SRCCLKENA_WAKE_COUNT_LSB (1U << 16) /* 16b */ 1115 1116 /* SPM_INFRA_EVENT_COUNT_STA (0x10006000 + 0x180) */ 1117 #define SPM_INFRA_SLEEP_COUNT_LSB (1U << 0) /* 16b */ 1118 #define SPM_INFRA_WAKE_COUNT_LSB (1U << 16) /* 16b */ 1119 1120 /* SPM_VRF18_EVENT_COUNT_STA (0x10006000 + 0x184) */ 1121 #define SPM_VRF18_SLEEP_COUNT_LSB (1U << 0) /* 16b */ 1122 #define SPM_VRF18_WAKE_COUNT_LSB (1U << 16) /* 16b */ 1123 1124 /* SPM_APSRC_EVENT_COUNT_STA (0x10006000 + 0x188) */ 1125 #define SPM_APSRC_SLEEP_COUNT_LSB (1U << 0) /* 16b */ 1126 #define SPM_APSRC_WAKE_COUNT_LSB (1U << 16) /* 16b */ 1127 1128 /* SPM_DDREN_EVENT_COUNT_STA (0x10006000 + 0x18C) */ 1129 #define SPM_DDREN_SLEEP_COUNT_LSB (1U << 0) /* 16b */ 1130 #define SPM_DDREN_WAKE_COUNT_LSB (1U << 16) /* 16b */ 1131 1132 /* MD32PCM_STA (0x10006000 + 0x190) */ 1133 #define MD32PCM_HALT_LSB (1U << 0) /* 1b */ 1134 #define MD32PCM_GATED_LSB (1U << 1) /* 1b */ 1135 1136 /* MD32PCM_PC (0x10006000 + 0x194) */ 1137 #define MON_PC_LSB (1U << 0) /* 32b */ 1138 1139 /* DVFSRC_EVENT_STA (0x10006000 + 0x1A4) */ 1140 #define DVFSRC_EVENT_LSB (1U << 0) /* 32b */ 1141 1142 /* BUS_PROTECT4_RDY (0x10006000 + 0x1A8) */ 1143 #define PROTECT4_READY_LSB (1U << 0) /* 32b */ 1144 1145 /* BUS_PROTECT5_RDY (0x10006000 + 0x1AC) */ 1146 #define PROTECT5_READY_LSB (1U << 0) /* 32b */ 1147 1148 /* BUS_PROTECT6_RDY (0x10006000 + 0x1B0) */ 1149 #define PROTECT6_READY_LSB (1U << 0) /* 32b */ 1150 1151 /* BUS_PROTECT7_RDY (0x10006000 + 0x1B4) */ 1152 #define PROTECT7_READY_LSB (1U << 0) /* 32b */ 1153 1154 /* BUS_PROTECT8_RDY (0x10006000 + 0x1B8) */ 1155 #define PROTECT8_READY_LSB (1U << 0) /* 32b */ 1156 1157 /* SPM_TWAM_LAST_STA0 (0x10006000 + 0x1D0) */ 1158 #define LAST_IDLE_CNT_0_LSB (1U << 0) /* 32b */ 1159 1160 /* SPM_TWAM_LAST_STA1 (0x10006000 + 0x1D4) */ 1161 #define LAST_IDLE_CNT_1_LSB (1U << 0) /* 32b */ 1162 1163 /* SPM_TWAM_LAST_STA2 (0x10006000 + 0x1D8) */ 1164 #define LAST_IDLE_CNT_2_LSB (1U << 0) /* 32b */ 1165 1166 /* SPM_TWAM_LAST_STA3 (0x10006000 + 0x1DC) */ 1167 #define LAST_IDLE_CNT_3_LSB (1U << 0) /* 32b */ 1168 1169 /* SPM_TWAM_CURR_STA0 (0x10006000 + 0x1E0) */ 1170 #define CURRENT_IDLE_CNT_0_LSB (1U << 0) /* 32b */ 1171 1172 /* SPM_TWAM_CURR_STA1 (0x10006000 + 0x1E4) */ 1173 #define CURRENT_IDLE_CNT_1_LSB (1U << 0) /* 32b */ 1174 1175 /* SPM_TWAM_CURR_STA2 (0x10006000 + 0x1E8) */ 1176 #define CURRENT_IDLE_CNT_2_LSB (1U << 0) /* 32b */ 1177 1178 /* SPM_TWAM_CURR_STA3 (0x10006000 + 0x1EC) */ 1179 #define CURRENT_IDLE_CNT_3_LSB (1U << 0) /* 32b */ 1180 1181 /* SPM_TWAM_TIMER_OUT (0x10006000 + 0x1F0) */ 1182 #define TWAM_TIMER_LSB (1U << 0) /* 32b */ 1183 1184 /* SPM_CG_CHECK_STA (0x10006000 + 0x1F4) */ 1185 #define SPM_CG_CHECK_SLEEP_REQ_0_LSB (1U << 0) /* 1b */ 1186 #define SPM_CG_CHECK_SLEEP_REQ_1_LSB (1U << 1) /* 1b */ 1187 #define SPM_CG_CHECK_SLEEP_REQ_2_LSB (1U << 2) /* 1b */ 1188 1189 /* SPM_DVFS_STA (0x10006000 + 0x1F8) */ 1190 #define TARGET_DVFS_LEVEL_LSB (1U << 0) /* 32b */ 1191 1192 /* SPM_DVFS_OPP_STA (0x10006000 + 0x1FC) */ 1193 #define TARGET_DVFS_OPP_LSB (1U << 0) /* 5b */ 1194 #define CURRENT_DVFS_OPP_LSB (1U << 5) /* 5b */ 1195 #define RELAY_DVFS_OPP_LSB (1U << 10) /* 5b */ 1196 1197 /* SPM_MCUSYS_PWR_CON (0x10006000 + 0x200) */ 1198 #define MCUSYS_SPMC_PWR_RST_B_LSB (1U << 0) /* 1b */ 1199 #define MCUSYS_SPMC_PWR_ON_LSB (1U << 2) /* 1b */ 1200 #define MCUSYS_SPMC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1201 #define MCUSYS_SPMC_RESETPWRON_CONFIG_LSB (1U << 5) /* 1b */ 1202 #define MCUSYS_SPMC_DORMANT_EN_LSB (1U << 6) /* 1b */ 1203 #define MCUSYS_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */ 1204 #define SPM_MCUSYS_PWR_CON_MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 31) /* 1b */ 1205 1206 /* SPM_CPUTOP_PWR_CON (0x10006000 + 0x204) */ 1207 #define MP0_SPMC_PWR_RST_B_CPUTOP_LSB (1U << 0) /* 1b */ 1208 #define MP0_SPMC_PWR_ON_CPUTOP_LSB (1U << 2) /* 1b */ 1209 #define MP0_SPMC_PWR_CLK_DIS_CPUTOP_LSB (1U << 4) /* 1b */ 1210 #define MP0_SPMC_RESETPWRON_CONFIG_CPUTOP_LSB (1U << 5) /* 1b */ 1211 #define MP0_SPMC_DORMANT_EN_CPUTOP_LSB (1U << 6) /* 1b */ 1212 #define MP0_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */ 1213 #define MP0_VSRAM_EXT_OFF_LSB (1U << 8) /* 1b */ 1214 #define SPM_CPUTOP_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 31) /* 1b */ 1215 /* SPM_CPU0_PWR_CON (0x10006000 + 0x208) */ 1216 #define MP0_SPMC_PWR_RST_B_CPU0_LSB (1U << 0) /* 1b */ 1217 #define MP0_SPMC_PWR_ON_CPU0_LSB (1U << 2) /* 1b */ 1218 #define MP0_SPMC_RESETPWRON_CONFIG_CPU0_LSB (1U << 5) /* 1b */ 1219 #define MP0_VPROC_EXT_OFF_CPU0_LSB (1U << 7) /* 1b */ 1220 #define SPM_CPU0_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 31) /* 1b */ 1221 1222 /* SPM_CPU1_PWR_CON (0x10006000 + 0x20C) */ 1223 #define MP0_SPMC_PWR_RST_B_CPU1_LSB (1U << 0) /* 1b */ 1224 #define MP0_SPMC_PWR_ON_CPU1_LSB (1U << 2) /* 1b */ 1225 #define MP0_SPMC_RESETPWRON_CONFIG_CPU1_LSB (1U << 5) /* 1b */ 1226 #define MP0_VPROC_EXT_OFF_CPU1_LSB (1U << 7) /* 1b */ 1227 #define SPM_CPU1_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 31) /* 1b */ 1228 1229 /* SPM_CPU2_PWR_CON (0x10006000 + 0x210) */ 1230 #define MP0_SPMC_PWR_RST_B_CPU2_LSB (1U << 0) /* 1b */ 1231 #define MP0_SPMC_PWR_ON_CPU2_LSB (1U << 2) /* 1b */ 1232 #define MP0_SPMC_RESETPWRON_CONFIG_CPU2_LSB (1U << 5) /* 1b */ 1233 #define MP0_VPROC_EXT_OFF_CPU2_LSB (1U << 7) /* 1b */ 1234 #define SPM_CPU2_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 31) /* 1b */ 1235 1236 /* SPM_CPU3_PWR_CON (0x10006000 + 0x214) */ 1237 #define MP0_SPMC_PWR_RST_B_CPU3_LSB (1U << 0) /* 1b */ 1238 #define MP0_SPMC_PWR_ON_CPU3_LSB (1U << 2) /* 1b */ 1239 #define MP0_SPMC_RESETPWRON_CONFIG_CPU3_LSB (1U << 5) /* 1b */ 1240 #define MP0_VPROC_EXT_OFF_CPU3_LSB (1U << 7) /* 1b */ 1241 #define SPM_CPU3_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 31) /* 1b */ 1242 1243 /* SPM_CPU4_PWR_CON (0x10006000 + 0x218) */ 1244 #define MP0_SPMC_PWR_RST_B_CPU4_LSB (1U << 0) /* 1b */ 1245 #define MP0_SPMC_PWR_ON_CPU4_LSB (1U << 2) /* 1b */ 1246 #define MP0_SPMC_RESETPWRON_CONFIG_CPU4_LSB (1U << 5) /* 1b */ 1247 #define MP0_VPROC_EXT_OFF_CPU4_LSB (1U << 7) /* 1b */ 1248 #define SPM_CPU4_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 31) /* 1b */ 1249 1250 /* SPM_CPU5_PWR_CON (0x10006000 + 0x21C) */ 1251 #define MP0_SPMC_PWR_RST_B_CPU5_LSB (1U << 0) /* 1b */ 1252 #define MP0_SPMC_PWR_ON_CPU5_LSB (1U << 2) /* 1b */ 1253 #define MP0_SPMC_RESETPWRON_CONFIG_CPU5_LSB (1U << 5) /* 1b */ 1254 #define MP0_VPROC_EXT_OFF_CPU5_LSB (1U << 7) /* 1b */ 1255 #define SPM_CPU5_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 31) /* 1b */ 1256 1257 /* SPM_CPU6_PWR_CON (0x10006000 + 0x220) */ 1258 #define MP0_SPMC_PWR_RST_B_CPU6_LSB (1U << 0) /* 1b */ 1259 #define MP0_SPMC_PWR_ON_CPU6_LSB (1U << 2) /* 1b */ 1260 #define MP0_SPMC_RESETPWRON_CONFIG_CPU6_LSB (1U << 5) /* 1b */ 1261 #define MP0_VPROC_EXT_OFF_CPU6_LSB (1U << 7) /* 1b */ 1262 #define SPM_CPU6_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 31) /* 1b */ 1263 1264 /* SPM_CPU7_PWR_CON (0x10006000 + 0x224) */ 1265 #define MP0_SPMC_PWR_RST_B_CPU7_LSB (1U << 0) /* 1b */ 1266 #define MP0_SPMC_PWR_ON_CPU7_LSB (1U << 2) /* 1b */ 1267 #define MP0_SPMC_RESETPWRON_CONFIG_CPU7_LSB (1U << 5) /* 1b */ 1268 #define MP0_VPROC_EXT_OFF_CPU7_LSB (1U << 7) /* 1b */ 1269 #define SPM_CPU7_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 31) /* 1b */ 1270 1271 /* ARMPLL_CLK_CON (0x10006000 + 0x22C) */ 1272 #define SC_ARM_FHC_PAUSE_LSB (1U << 0) /* 6b */ 1273 #define SC_ARM_CK_OFF_LSB (1U << 6) /* 6b */ 1274 #define SC_ARMPLL_OFF_LSB (1U << 12) /* 1b */ 1275 #define SC_ARMBPLL_OFF_LSB (1U << 13) /* 1b */ 1276 #define SC_ARMBPLL1_OFF_LSB (1U << 14) /* 1b */ 1277 #define SC_ARMBPLL2_OFF_LSB (1U << 15) /* 1b */ 1278 #define SC_ARMBPLL3_OFF_LSB (1U << 16) /* 1b */ 1279 #define SC_CCIPLL_CKOFF_LSB (1U << 17) /* 1b */ 1280 #define SC_ARMDDS_OFF_LSB (1U << 18) /* 1b */ 1281 #define SC_ARMBPLL_S_OFF_LSB (1U << 19) /* 1b */ 1282 #define SC_ARMBPLL1_S_OFF_LSB (1U << 20) /* 1b */ 1283 #define SC_ARMBPLL2_S_OFF_LSB (1U << 21) /* 1b */ 1284 #define SC_ARMBPLL3_S_OFF_LSB (1U << 22) /* 1b */ 1285 #define SC_CCIPLL_PWROFF_LSB (1U << 23) /* 1b */ 1286 #define SC_ARMPLLOUT_OFF_LSB (1U << 24) /* 1b */ 1287 #define SC_ARMBPLLOUT_OFF_LSB (1U << 25) /* 1b */ 1288 #define SC_ARMBPLLOUT1_OFF_LSB (1U << 26) /* 1b */ 1289 #define SC_ARMBPLLOUT2_OFF_LSB (1U << 27) /* 1b */ 1290 #define SC_ARMBPLLOUT3_OFF_LSB (1U << 28) /* 1b */ 1291 #define SC_CCIPLL_OUT_OFF_LSB (1U << 29) /* 1b */ 1292 1293 /* MCUSYS_IDLE_STA (0x10006000 + 0x230) */ 1294 #define ARMBUS_IDLE_TO_26M_LSB (1U << 0) /* 1b */ 1295 #define MP0_CLUSTER_IDLE_TO_PWR_OFF_LSB (1U << 1) /* 1b */ 1296 #define MCUSYS_DDR_EN_0_LSB (1U << 2) /* 1b */ 1297 #define MCUSYS_DDR_EN_1_LSB (1U << 3) /* 1b */ 1298 #define MCUSYS_DDR_EN_2_LSB (1U << 4) /* 1b */ 1299 #define MCUSYS_DDR_EN_3_LSB (1U << 5) /* 1b */ 1300 #define MCUSYS_DDR_EN_4_LSB (1U << 6) /* 1b */ 1301 #define MCUSYS_DDR_EN_5_LSB (1U << 7) /* 1b */ 1302 #define MCUSYS_DDR_EN_6_LSB (1U << 8) /* 1b */ 1303 #define MCUSYS_DDR_EN_7_LSB (1U << 9) /* 1b */ 1304 #define MP0_CPU_IDLE_TO_PWR_OFF_LSB (1U << 16) /* 8b */ 1305 #define WFI_AF_SEL_LSB (1U << 24) /* 8b */ 1306 1307 /* GIC_WAKEUP_STA (0x10006000 + 0x234) */ 1308 #define GIC_WAKEUP_STA_GIC_WAKEUP_LSB (1U << 10) /* 10b */ 1309 1310 /* CPU_SPARE_CON (0x10006000 + 0x238) */ 1311 #define CPU_SPARE_CON_LSB (1U << 0) /* 32b */ 1312 1313 /* CPU_SPARE_CON_SET (0x10006000 + 0x23C) */ 1314 #define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */ 1315 1316 /* CPU_SPARE_CON_CLR (0x10006000 + 0x240) */ 1317 #define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ 1318 1319 /* ARMPLL_CLK_SEL (0x10006000 + 0x244) */ 1320 #define ARMPLL_CLK_SEL_LSB (1U << 0) /* 15b */ 1321 1322 /* EXT_INT_WAKEUP_REQ (0x10006000 + 0x248) */ 1323 #define EXT_INT_WAKEUP_REQ_LSB (1U << 0) /* 10b */ 1324 1325 /* EXT_INT_WAKEUP_REQ_SET (0x10006000 + 0x24C) */ 1326 #define EXT_INT_WAKEUP_REQ_SET_LSB (1U << 0) /* 10b */ 1327 1328 /* EXT_INT_WAKEUP_REQ_CLR (0x10006000 + 0x250) */ 1329 #define EXT_INT_WAKEUP_REQ_CLR_LSB (1U << 0) /* 10b */ 1330 1331 /* CPU_IRQ_MASK (0x10006000 + 0x260) */ 1332 #define CPU_IRQ_MASK_LSB (1U << 0) /* 8b */ 1333 1334 /* CPU_IRQ_MASK_SET (0x10006000 + 0x264) */ 1335 #define CPU_IRQ_MASK_SET_LSB (1U << 0) /* 8b */ 1336 1337 /* CPU_IRQ_MASK_CLR (0x10006000 + 0x268) */ 1338 #define CPU_IRQ_MASK_CLR_LSB (1U << 0) /* 8b */ 1339 1340 /* CPU_WFI_EN (0x10006000 + 0x280) */ 1341 #define CPU_WFI_EN_LSB (1U << 0) /* 8b */ 1342 1343 /* CPU_WFI_EN_SET (0x10006000 + 0x284) */ 1344 #define CPU_WFI_EN_SET_LSB (1U << 0) /* 8b */ 1345 1346 /* CPU_WFI_EN_CLR (0x10006000 + 0x288) */ 1347 #define CPU_WFI_EN_CLR_LSB (1U << 0) /* 8b */ 1348 1349 /* ROOT_CPUTOP_ADDR (0x10006000 + 0x2A0) */ 1350 #define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */ 1351 1352 /* ROOT_CORE_ADDR (0x10006000 + 0x2A4) */ 1353 #define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */ 1354 1355 /* SPM2SW_MAILBOX_0 (0x10006000 + 0x2D0) */ 1356 #define SPM2SW_MAILBOX_0_LSB (1U << 0) /* 32b */ 1357 1358 /* SPM2SW_MAILBOX_1 (0x10006000 + 0x2D4) */ 1359 #define SPM2SW_MAILBOX_1_LSB (1U << 0) /* 32b */ 1360 1361 /* SPM2SW_MAILBOX_2 (0x10006000 + 0x2D8) */ 1362 #define SPM2SW_MAILBOX_2_LSB (1U << 0) /* 32b */ 1363 1364 /* SPM2SW_MAILBOX_3 (0x10006000 + 0x2DC) */ 1365 #define SPM2SW_MAILBOX_3_LSB (1U << 0) /* 32b */ 1366 1367 /* SW2SPM_WAKEUP (0x10006000 + 0x2E0) */ 1368 #define SW2SPM_WAKEUP_SW2SPM_WAKEUP_LSB (1U << 0) /* 4b */ 1369 1370 /* SW2SPM_WAKEUP_SET (0x10006000 + 0x2E4) */ 1371 #define SW2SPM_WAKEUP_SET_LSB (1U << 0) /* 4b */ 1372 1373 /* SW2SPM_WAKEUP_CLR (0x10006000 + 0x2E8) */ 1374 #define SW2SPM_WAKEUP_CLR_LSB (1U << 0) /* 4b */ 1375 1376 /* SW2SPM_MAILBOX_0 (0x10006000 + 0x2EC) */ 1377 #define SW2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ 1378 1379 /* SW2SPM_MAILBOX_1 (0x10006000 + 0x2F0) */ 1380 #define SW2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ 1381 1382 /* SW2SPM_MAILBOX_2 (0x10006000 + 0x2F4) */ 1383 #define SW2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ 1384 1385 /* SW2SPM_MAILBOX_3 (0x10006000 + 0x2F8) */ 1386 #define SW2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ 1387 1388 /* SW2SPM_CFG (0x10006000 + 0x2FC) */ 1389 #define SWU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */ 1390 1391 /* MD1_PWR_CON (0x10006000 + 0x300) */ 1392 #define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */ 1393 #define MD1_PWR_ISO_LSB (1U << 1) /* 1b */ 1394 #define MD1_PWR_ON_LSB (1U << 2) /* 1b */ 1395 #define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1396 #define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1397 #define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */ 1398 #define SC_MD1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1399 1400 /* CONN_PWR_CON (0x10006000 + 0x304) */ 1401 #define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */ 1402 #define CONN_PWR_ISO_LSB (1U << 1) /* 1b */ 1403 #define CONN_PWR_ON_LSB (1U << 2) /* 1b */ 1404 #define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1405 #define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1406 1407 /* MFG0_PWR_CON (0x10006000 + 0x308) */ 1408 #define MFG0_PWR_RST_B_LSB (1U << 0) /* 1b */ 1409 #define MFG0_PWR_ISO_LSB (1U << 1) /* 1b */ 1410 #define MFG0_PWR_ON_LSB (1U << 2) /* 1b */ 1411 #define MFG0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1412 #define MFG0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1413 #define MFG0_SRAM_PDN_LSB (1U << 8) /* 1b */ 1414 #define SC_MFG0_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1415 1416 /* MFG1_PWR_CON (0x10006000 + 0x30C) */ 1417 #define MFG1_PWR_RST_B_LSB (1U << 0) /* 1b */ 1418 #define MFG1_PWR_ISO_LSB (1U << 1) /* 1b */ 1419 #define MFG1_PWR_ON_LSB (1U << 2) /* 1b */ 1420 #define MFG1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1421 #define MFG1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1422 #define MFG1_SRAM_PDN_LSB (1U << 8) /* 1b */ 1423 #define SC_MFG1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1424 1425 /* MFG2_PWR_CON (0x10006000 + 0x310) */ 1426 #define MFG2_PWR_RST_B_LSB (1U << 0) /* 1b */ 1427 #define MFG2_PWR_ISO_LSB (1U << 1) /* 1b */ 1428 #define MFG2_PWR_ON_LSB (1U << 2) /* 1b */ 1429 #define MFG2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1430 #define MFG2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1431 #define MFG2_SRAM_PDN_LSB (1U << 8) /* 1b */ 1432 #define SC_MFG2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1433 1434 /* MFG3_PWR_CON (0x10006000 + 0x314) */ 1435 #define MFG3_PWR_RST_B_LSB (1U << 0) /* 1b */ 1436 #define MFG3_PWR_ISO_LSB (1U << 1) /* 1b */ 1437 #define MFG3_PWR_ON_LSB (1U << 2) /* 1b */ 1438 #define MFG3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1439 #define MFG3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1440 #define MFG3_SRAM_PDN_LSB (1U << 8) /* 1b */ 1441 #define SC_MFG3_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1442 1443 /* MFG4_PWR_CON (0x10006000 + 0x318) */ 1444 #define MFG4_PWR_RST_B_LSB (1U << 0) /* 1b */ 1445 #define MFG4_PWR_ISO_LSB (1U << 1) /* 1b */ 1446 #define MFG4_PWR_ON_LSB (1U << 2) /* 1b */ 1447 #define MFG4_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1448 #define MFG4_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1449 #define MFG4_SRAM_PDN_LSB (1U << 8) /* 1b */ 1450 #define SC_MFG4_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1451 1452 /* MFG5_PWR_CON (0x10006000 + 0x31C) */ 1453 #define MFG5_PWR_RST_B_LSB (1U << 0) /* 1b */ 1454 #define MFG5_PWR_ISO_LSB (1U << 1) /* 1b */ 1455 #define MFG5_PWR_ON_LSB (1U << 2) /* 1b */ 1456 #define MFG5_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1457 #define MFG5_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1458 #define MFG5_SRAM_PDN_LSB (1U << 8) /* 1b */ 1459 #define SC_MFG5_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1460 1461 /* MFG6_PWR_CON (0x10006000 + 0x320) */ 1462 #define MFG6_PWR_RST_B_LSB (1U << 0) /* 1b */ 1463 #define MFG6_PWR_ISO_LSB (1U << 1) /* 1b */ 1464 #define MFG6_PWR_ON_LSB (1U << 2) /* 1b */ 1465 #define MFG6_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1466 #define MFG6_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1467 #define MFG6_SRAM_PDN_LSB (1U << 8) /* 1b */ 1468 #define SC_MFG6_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1469 1470 /* IFR_PWR_CON (0x10006000 + 0x324) */ 1471 #define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */ 1472 #define IFR_PWR_ISO_LSB (1U << 1) /* 1b */ 1473 #define IFR_PWR_ON_LSB (1U << 2) /* 1b */ 1474 #define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1475 #define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1476 #define IFR_SRAM_PDN_LSB (1U << 8) /* 1b */ 1477 #define SC_IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1478 1479 /* IFR_SUB_PWR_CON (0x10006000 + 0x328) */ 1480 #define IFR_SUB_PWR_RST_B_LSB (1U << 0) /* 1b */ 1481 #define IFR_SUB_PWR_ISO_LSB (1U << 1) /* 1b */ 1482 #define IFR_SUB_PWR_ON_LSB (1U << 2) /* 1b */ 1483 #define IFR_SUB_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1484 #define IFR_SUB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1485 #define IFR_SUB_SRAM_PDN_LSB (1U << 8) /* 1b */ 1486 #define SC_IFR_SUB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1487 1488 /* DPY_PWR_CON (0x10006000 + 0x32C) */ 1489 #define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */ 1490 #define DPY_PWR_ISO_LSB (1U << 1) /* 1b */ 1491 #define DPY_PWR_ON_LSB (1U << 2) /* 1b */ 1492 #define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1493 #define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1494 1495 /* DRAMC_MD32_PWR_CON (0x10006000 + 0x330) */ 1496 #define DRAMC_MD32_PWR_RST_B_LSB (1U << 0) /* 1b */ 1497 #define DRAMC_MD32_PWR_ISO_LSB (1U << 1) /* 1b */ 1498 #define DRAMC_MD32_PWR_ON_LSB (1U << 2) /* 1b */ 1499 #define DRAMC_MD32_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1500 #define DRAMC_MD32_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1501 #define DRAMC_MD32_SRAM_PDN_LSB (1U << 8) /* 1b */ 1502 #define SC_DRAMC_MD32_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1503 1504 /* ISP_PWR_CON (0x10006000 + 0x334) */ 1505 #define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */ 1506 #define ISP_PWR_ISO_LSB (1U << 1) /* 1b */ 1507 #define ISP_PWR_ON_LSB (1U << 2) /* 1b */ 1508 #define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1509 #define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1510 #define ISP_SRAM_PDN_LSB (1U << 8) /* 1b */ 1511 #define SC_ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1512 1513 /* ISP2_PWR_CON (0x10006000 + 0x338) */ 1514 #define ISP2_PWR_RST_B_LSB (1U << 0) /* 1b */ 1515 #define ISP2_PWR_ISO_LSB (1U << 1) /* 1b */ 1516 #define ISP2_PWR_ON_LSB (1U << 2) /* 1b */ 1517 #define ISP2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1518 #define ISP2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1519 #define ISP2_SRAM_PDN_LSB (1U << 8) /* 1b */ 1520 #define SC_ISP2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1521 1522 /* IPE_PWR_CON (0x10006000 + 0x33C) */ 1523 #define IPE_PWR_RST_B_LSB (1U << 0) /* 1b */ 1524 #define IPE_PWR_ISO_LSB (1U << 1) /* 1b */ 1525 #define IPE_PWR_ON_LSB (1U << 2) /* 1b */ 1526 #define IPE_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1527 #define IPE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1528 #define IPE_SRAM_PDN_LSB (1U << 8) /* 1b */ 1529 #define SC_IPE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1530 1531 /* VDE_PWR_CON (0x10006000 + 0x340) */ 1532 #define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */ 1533 #define VDE_PWR_ISO_LSB (1U << 1) /* 1b */ 1534 #define VDE_PWR_ON_LSB (1U << 2) /* 1b */ 1535 #define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1536 #define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1537 #define VDE_SRAM_PDN_LSB (1U << 8) /* 1b */ 1538 #define SC_VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1539 1540 /* VDE2_PWR_CON (0x10006000 + 0x344) */ 1541 #define VDE2_PWR_RST_B_LSB (1U << 0) /* 1b */ 1542 #define VDE2_PWR_ISO_LSB (1U << 1) /* 1b */ 1543 #define VDE2_PWR_ON_LSB (1U << 2) /* 1b */ 1544 #define VDE2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1545 #define VDE2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1546 #define VDE2_SRAM_PDN_LSB (1U << 8) /* 1b */ 1547 #define SC_VDE2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1548 1549 /* VEN_PWR_CON (0x10006000 + 0x348) */ 1550 #define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */ 1551 #define VEN_PWR_ISO_LSB (1U << 1) /* 1b */ 1552 #define VEN_PWR_ON_LSB (1U << 2) /* 1b */ 1553 #define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1554 #define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1555 #define VEN_SRAM_PDN_LSB (1U << 8) /* 1b */ 1556 #define SC_VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1557 1558 /* VEN_CORE1_PWR_CON (0x10006000 + 0x34C) */ 1559 #define VEN_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */ 1560 #define VEN_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */ 1561 #define VEN_CORE1_PWR_ON_LSB (1U << 2) /* 1b */ 1562 #define VEN_CORE1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1563 #define VEN_CORE1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1564 #define VEN_CORE1_SRAM_PDN_LSB (1U << 8) /* 1b */ 1565 #define SC_VEN_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1566 1567 /* MDP_PWR_CON (0x10006000 + 0x350) */ 1568 #define MDP_PWR_RST_B_LSB (1U << 0) /* 1b */ 1569 #define MDP_PWR_ISO_LSB (1U << 1) /* 1b */ 1570 #define MDP_PWR_ON_LSB (1U << 2) /* 1b */ 1571 #define MDP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1572 #define MDP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1573 #define MDP_SRAM_PDN_LSB (1U << 8) /* 1b */ 1574 #define SC_MDP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1575 1576 /* DIS_PWR_CON (0x10006000 + 0x354) */ 1577 #define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */ 1578 #define DIS_PWR_ISO_LSB (1U << 1) /* 1b */ 1579 #define DIS_PWR_ON_LSB (1U << 2) /* 1b */ 1580 #define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1581 #define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1582 #define DIS_SRAM_PDN_LSB (1U << 8) /* 1b */ 1583 #define SC_DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1584 1585 /* AUDIO_PWR_CON (0x10006000 + 0x358) */ 1586 #define AUDIO_PWR_RST_B_LSB (1U << 0) /* 1b */ 1587 #define AUDIO_PWR_ISO_LSB (1U << 1) /* 1b */ 1588 #define AUDIO_PWR_ON_LSB (1U << 2) /* 1b */ 1589 #define AUDIO_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1590 #define AUDIO_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1591 #define AUDIO_SRAM_PDN_LSB (1U << 8) /* 1b */ 1592 #define SC_AUDIO_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1593 1594 /* CAM_PWR_CON (0x10006000 + 0x35C) */ 1595 #define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */ 1596 #define CAM_PWR_ISO_LSB (1U << 1) /* 1b */ 1597 #define CAM_PWR_ON_LSB (1U << 2) /* 1b */ 1598 #define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1599 #define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1600 #define CAM_SRAM_PDN_LSB (1U << 8) /* 1b */ 1601 #define SC_CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1602 1603 /* CAM_RAWA_PWR_CON (0x10006000 + 0x360) */ 1604 #define CAM_RAWA_PWR_RST_B_LSB (1U << 0) /* 1b */ 1605 #define CAM_RAWA_PWR_ISO_LSB (1U << 1) /* 1b */ 1606 #define CAM_RAWA_PWR_ON_LSB (1U << 2) /* 1b */ 1607 #define CAM_RAWA_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1608 #define CAM_RAWA_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1609 #define CAM_RAWA_SRAM_PDN_LSB (1U << 8) /* 1b */ 1610 #define SC_CAM_RAWA_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1611 1612 /* CAM_RAWB_PWR_CON (0x10006000 + 0x364) */ 1613 #define CAM_RAWB_PWR_RST_B_LSB (1U << 0) /* 1b */ 1614 #define CAM_RAWB_PWR_ISO_LSB (1U << 1) /* 1b */ 1615 #define CAM_RAWB_PWR_ON_LSB (1U << 2) /* 1b */ 1616 #define CAM_RAWB_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1617 #define CAM_RAWB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1618 #define CAM_RAWB_SRAM_PDN_LSB (1U << 8) /* 1b */ 1619 #define SC_CAM_RAWB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1620 1621 /* CAM_RAWC_PWR_CON (0x10006000 + 0x368) */ 1622 #define CAM_RAWC_PWR_RST_B_LSB (1U << 0) /* 1b */ 1623 #define CAM_RAWC_PWR_ISO_LSB (1U << 1) /* 1b */ 1624 #define CAM_RAWC_PWR_ON_LSB (1U << 2) /* 1b */ 1625 #define CAM_RAWC_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1626 #define CAM_RAWC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1627 #define CAM_RAWC_SRAM_PDN_LSB (1U << 8) /* 1b */ 1628 #define SC_CAM_RAWC_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1629 1630 /* SYSRAM_CON (0x10006000 + 0x36C) */ 1631 #define SYSRAM_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1632 #define SYSRAM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1633 #define SYSRAM_SRAM_SLEEP_B_LSB (1U << 4) /* 4b */ 1634 #define SYSRAM_SRAM_PDN_LSB (1U << 16) /* 4b */ 1635 1636 /* SYSROM_CON (0x10006000 + 0x370) */ 1637 #define SYSROM_SRAM_PDN_LSB (1U << 0) /* 8b */ 1638 1639 /* SSPM_SRAM_CON (0x10006000 + 0x374) */ 1640 #define SSPM_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1641 #define SSPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1642 #define SSPM_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1643 #define SSPM_SRAM_PDN_LSB (1U << 16) /* 1b */ 1644 1645 /* SCP_SRAM_CON (0x10006000 + 0x378) */ 1646 #define SCP_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1647 #define SCP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1648 #define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1649 #define SCP_SRAM_PDN_LSB (1U << 16) /* 1b */ 1650 1651 /* DPY_SHU_SRAM_CON (0x10006000 + 0x37C) */ 1652 #define DPY_SHU_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1653 #define DPY_SHU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1654 #define DPY_SHU_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */ 1655 #define DPY_SHU_SRAM_PDN_LSB (1U << 16) /* 2b */ 1656 1657 /* UFS_SRAM_CON (0x10006000 + 0x380) */ 1658 #define UFS_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1659 #define UFS_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1660 #define UFS_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */ 1661 #define UFS_SRAM_PDN_LSB (1U << 16) /* 8b */ 1662 1663 /* DEVAPC_IFR_SRAM_CON (0x10006000 + 0x384) */ 1664 #define DEVAPC_IFR_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1665 #define DEVAPC_IFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1666 #define DEVAPC_IFR_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */ 1667 #define DEVAPC_IFR_SRAM_PDN_LSB (1U << 16) /* 6b */ 1668 1669 /* DEVAPC_SUBIFR_SRAM_CON (0x10006000 + 0x388) */ 1670 #define DEVAPC_SUBIFR_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1671 #define DEVAPC_SUBIFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1672 #define DEVAPC_SUBIFR_SRAM_SLEEP_B_LSB (1U << 4) /* 12b */ 1673 #define DEVAPC_SUBIFR_SRAM_PDN_LSB (1U << 16) /* 12b */ 1674 1675 /* DEVAPC_ACP_SRAM_CON (0x10006000 + 0x38C) */ 1676 #define DEVAPC_ACP_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1677 #define DEVAPC_ACP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1678 #define DEVAPC_ACP_SRAM_SLEEP_B_LSB (1U << 4) /* 12b */ 1679 #define DEVAPC_ACP_SRAM_PDN_LSB (1U << 16) /* 12b */ 1680 1681 /* USB_SRAM_CON (0x10006000 + 0x390) */ 1682 #define USB_SRAM_PDN_LSB (1U << 0) /* 9b */ 1683 1684 /* DUMMY_SRAM_CONi (0x10006000 + 0x394) */ 1685 #define DUMMY_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1686 #define DUMMY_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1687 #define DUMMY_SRAM_SLEEP_B_LSB (1U << 4) /* 12b */ 1688 #define DUMMY_SRAM_PDN_LSB (1U << 16) /* 12b */ 1689 1690 /* MD_EXT_BUCK_ISO_CON (0x10006000 + 0x398) */ 1691 #define VMODEM_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ 1692 #define VMD_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */ 1693 1694 /* EXT_BUCK_ISO (0x10006000 + 0x39C) */ 1695 #define VIMVO_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ 1696 #define GPU_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */ 1697 #define ADSP_EXT_BUCK_ISO_LSB (1U << 2) /* 1b */ 1698 #define IPU_EXT_BUCK_ISO_LSB (1U << 5) /* 3b */ 1699 1700 /* DXCC_SRAM_CON (0x10006000 + 0x3A0) */ 1701 #define DXCC_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1702 #define DXCC_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1703 #define DXCC_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */ 1704 #define DXCC_SRAM_PDN_LSB (1U << 16) /* 8b */ 1705 1706 /* MSDC_PWR_CON (0x10006000 + 0x3A4) */ 1707 #define MSDC_PWR_RST_B_LSB (1U << 0) /* 1b */ 1708 #define MSDC_PWR_ISO_LSB (1U << 1) /* 1b */ 1709 #define MSDC_PWR_ON_LSB (1U << 2) /* 1b */ 1710 #define MSDC_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1711 #define MSDC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1712 #define MSDC_SRAM_CKISO_LSB (1U << 5) /* 1b */ 1713 #define MSDC_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 1714 #define MSDC_SRAM_PDN_LSB (1U << 8) /* 5b */ 1715 #define MSDC_SRAM_SLEEP_B_LSB (1U << 13) /* 5b */ 1716 #define SC_MSDC_SRAM_PDN_ACK_LSB (1U << 18) /* 5b */ 1717 #define SC_MSDC_SRAM_SLEEP_B_ACK_LSB (1U << 23) /* 5b */ 1718 1719 /* DEBUGTOP_SRAM_CON (0x10006000 + 0x3A8) */ 1720 #define DEBUGTOP_SRAM_PDN_LSB (1U << 0) /* 1b */ 1721 1722 /* DP_TX_PWR_CON (0x10006000 + 0x3AC) */ 1723 #define DP_TX_PWR_RST_B_LSB (1U << 0) /* 1b */ 1724 #define DP_TX_PWR_ISO_LSB (1U << 1) /* 1b */ 1725 #define DP_TX_PWR_ON_LSB (1U << 2) /* 1b */ 1726 #define DP_TX_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1727 #define DP_TX_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1728 #define DP_TX_SRAM_PDN_LSB (1U << 8) /* 1b */ 1729 #define SC_DP_TX_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1730 1731 /* DPMAIF_SRAM_CON (0x10006000 + 0x3B0) */ 1732 #define DPMAIF_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1733 #define DPMAIF_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1734 #define DPMAIF_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1735 #define DPMAIF_SRAM_PDN_LSB (1U << 16) /* 1b */ 1736 1737 /* DPY_SHU2_SRAM_CON (0x10006000 + 0x3B4) */ 1738 #define DPY_SHU2_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1739 #define DPY_SHU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1740 #define DPY_SHU2_SRAM_SLEEP_B_LSB (1U << 4) /* 12b */ 1741 #define DPY_SHU2_SRAM_PDN_LSB (1U << 16) /* 12b */ 1742 1743 /* DRAMC_MCU2_SRAM_CON (0x10006000 + 0x3B8) */ 1744 #define DRAMC_MCU2_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1745 #define DRAMC_MCU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1746 #define DRAMC_MCU2_SRAM_SLEEP_B_LSB (1U << 4) /* 12b */ 1747 #define DRAMC_MCU2_SRAM_PDN_LSB (1U << 16) /* 12b */ 1748 1749 /* DRAMC_MCU_SRAM_CON (0x10006000 + 0x3BC) */ 1750 #define DRAMC_MCU_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1751 #define DRAMC_MCU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1752 #define DRAMC_MCU_SRAM_SLEEP_B_LSB (1U << 4) /* 12b */ 1753 #define DRAMC_MCU_SRAM_PDN_LSB (1U << 16) /* 12b */ 1754 1755 /* MCUPM_PWR_CON (0x10006000 + 0x3C0) */ 1756 #define MCUPM_PWR_RST_B_LSB (1U << 0) /* 1b */ 1757 #define MCUPM_PWR_ISO_LSB (1U << 1) /* 1b */ 1758 #define MCUPM_PWR_ON_LSB (1U << 2) /* 1b */ 1759 #define MCUPM_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1760 #define MCUPM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1761 #define MCUPM_SRAM_CKISO_LSB (1U << 5) /* 1b */ 1762 #define MCUPM_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 1763 #define MCUPM_SRAM_PDN_LSB (1U << 8) /* 1b */ 1764 #define MCUPM_SRAM_SLEEP_B_LSB (1U << 9) /* 1b */ 1765 #define SC_MCUPM_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1766 #define SC_MCUPM_SRAM_SLEEP_B_ACK_LSB (1U << 13) /* 1b */ 1767 #define MCUPM_WFI_LSB (1U << 14) /* 1b */ 1768 1769 /* DPY2_PWR_CON (0x10006000 + 0x3C4) */ 1770 #define DPY2_PWR_RST_B_LSB (1U << 0) /* 1b */ 1771 #define DPY2_PWR_ISO_LSB (1U << 1) /* 1b */ 1772 #define DPY2_PWR_ON_LSB (1U << 2) /* 1b */ 1773 #define DPY2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1774 #define DPY2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1775 #define DPY2_SRAM_PDN_LSB (1U << 8) /* 1b */ 1776 #define SC_DPY2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1777 1778 /* SPM_SRAM_CON (0x10006000 + 0x3C8) */ 1779 #define SPM_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1780 #define REG_SPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1781 #define REG_SPM_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */ 1782 #define SPM_SRAM_PDN_LSB (1U << 16) /* 2b */ 1783 1784 /* PERI_PWR_CON (0x10006000 + 0x3D0) */ 1785 #define PERI_PWR_RST_B_LSB (1U << 0) /* 1b */ 1786 #define PERI_PWR_ISO_LSB (1U << 1) /* 1b */ 1787 #define PERI_PWR_ON_LSB (1U << 2) /* 1b */ 1788 #define PERI_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1789 #define PERI_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1790 #define PERI_SRAM_PDN_LSB (1U << 8) /* 1b */ 1791 #define SC_PERI_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1792 1793 /* NNA0_PWR_CON (0x10006000 + 0x3D4) */ 1794 #define NNA0_PWR_RST_B_LSB (1U << 0) /* 1b */ 1795 #define NNA0_PWR_ISO_LSB (1U << 1) /* 1b */ 1796 #define NNA0_PWR_ON_LSB (1U << 2) /* 1b */ 1797 #define NNA0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1798 #define NNA0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1799 #define NNA0_SRAM_PDN_LSB (1U << 8) /* 1b */ 1800 #define SC_NNA0_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1801 1802 /* NNA1_PWR_CON (0x10006000 + 0x3D8) */ 1803 #define NNA1_PWR_RST_B_LSB (1U << 0) /* 1b */ 1804 #define NNA1_PWR_ISO_LSB (1U << 1) /* 1b */ 1805 #define NNA1_PWR_ON_LSB (1U << 2) /* 1b */ 1806 #define NNA1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1807 #define NNA1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1808 #define NNA1_SRAM_PDN_LSB (1U << 8) /* 1b */ 1809 #define SC_NNA1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1810 1811 /* NNA2_PWR_CON (0x10006000 + 0x3DC) */ 1812 #define NNA2_PWR_RST_B_LSB (1U << 0) /* 1b */ 1813 #define NNA2_PWR_ISO_LSB (1U << 1) /* 1b */ 1814 #define NNA2_PWR_ON_LSB (1U << 2) /* 1b */ 1815 #define NNA2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1816 #define NNA2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1817 #define NNA2_SRAM_PDN_LSB (1U << 8) /* 1b */ 1818 #define SC_NNA2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1819 1820 /* NNA_PWR_CON (0x10006000 + 0x3E0) */ 1821 #define NNA_PWR_RST_B_LSB (1U << 0) /* 1b */ 1822 #define NNA_PWR_ISO_LSB (1U << 1) /* 1b */ 1823 #define NNA_PWR_ON_LSB (1U << 2) /* 1b */ 1824 #define NNA_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1825 #define NNA_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1826 #define NNA_SRAM_PDN_LSB (1U << 8) /* 1b */ 1827 #define SC_NNA_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1828 1829 /* ADSP_PWR_CON (0x10006000 + 0x3E4) */ 1830 #define ADSP_PWR_RST_B_LSB (1U << 0) /* 1b */ 1831 #define ADSP_PWR_ISO_LSB (1U << 1) /* 1b */ 1832 #define ADSP_PWR_ON_LSB (1U << 2) /* 1b */ 1833 #define ADSP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1834 #define ADSP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1835 #define ADSP_SRAM_CKISO_LSB (1U << 5) /* 1b */ 1836 #define ADSP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 1837 #define ADSP_SRAM_PDN_LSB (1U << 8) /* 1b */ 1838 #define ADSP_SRAM_SLEEP_B_LSB (1U << 9) /* 1b */ 1839 #define SC_ADSP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1840 #define SC_ADSP_SRAM_SLEEP_B_ACK_LSB (1U << 13) /* 1b */ 1841 1842 /* DPY_SRAM_CON (0x10006000 + 0x3E8) */ 1843 #define DPY_SRAM_PDN_LSB (1U << 16) /* 4b */ 1844 #define SC_DPY_SRAM_PDN_ACK_LSB (1U << 24) /* 4b */ 1845 1846 /* SPM_MEM_CK_SEL (0x10006000 + 0x400) */ 1847 #define SC_MEM_CK_SEL_LSB (1U << 0) /* 1b */ 1848 #define SPM2CKSYS_MEM_CK_MUX_UPDATE_LSB (1U << 1) /* 1b */ 1849 1850 /* SPM_BUS_PROTECT_MASK_B (0x10006000 + 0X404) */ 1851 #define SPM_BUS_PROTECT_MASK_B_LSB (1U << 0) /* 32b */ 1852 1853 /* SPM_BUS_PROTECT1_MASK_B (0x10006000 + 0x408) */ 1854 #define SPM_BUS_PROTECT1_MASK_B_LSB (1U << 0) /* 32b */ 1855 1856 /* SPM_BUS_PROTECT2_MASK_B (0x10006000 + 0x40C) */ 1857 #define SPM_BUS_PROTECT2_MASK_B_LSB (1U << 0) /* 32b */ 1858 1859 /* SPM_BUS_PROTECT3_MASK_B (0x10006000 + 0x410) */ 1860 #define SPM_BUS_PROTECT3_MASK_B_LSB (1U << 0) /* 32b */ 1861 1862 /* SPM_BUS_PROTECT4_MASK_B (0x10006000 + 0x414) */ 1863 #define SPM_BUS_PROTECT4_MASK_B_LSB (1U << 0) /* 32b */ 1864 1865 /* SPM_EMI_BW_MODE (0x10006000 + 0x418) */ 1866 #define EMI_BW_MODE_LSB (1U << 0) /* 1b */ 1867 #define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */ 1868 #define EMI_BW_MODE_2_LSB (1U << 2) /* 1b */ 1869 #define EMI_BOOST_MODE_2_LSB (1U << 3) /* 1b */ 1870 #define SPM_S1_MODE_CH_LSB (1U << 16) /* 2b */ 1871 1872 /* AP2MD_PEER_WAKEUP (0x10006000 + 0x41C) */ 1873 #define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */ 1874 1875 /* ULPOSC_CON (0x10006000 + 0x420) */ 1876 #define ULPOSC_EN_LSB (1U << 0) /* 1b */ 1877 #define ULPOSC_RST_LSB (1U << 1) /* 1b */ 1878 #define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */ 1879 #define ULPOSC_CLK_SEL_LSB (1U << 3) /* 1b */ 1880 1881 /* SPM2MM_CON (0x10006000 + 0x424) */ 1882 #define SPM2MM_FORCE_ULTRA_LSB (1U << 0) /* 1b */ 1883 #define SPM2MM_DBL_OSTD_ACT_LSB (1U << 1) /* 1b */ 1884 #define SPM2MM_ULTRAREQ_LSB (1U << 2) /* 1b */ 1885 #define SPM2MD_ULTRAREQ_LSB (1U << 3) /* 1b */ 1886 #define SPM2ISP_ULTRAREQ_LSB (1U << 4) /* 1b */ 1887 #define MM2SPM_FORCE_ULTRA_ACK_D2T_LSB (1U << 16) /* 1b */ 1888 #define MM2SPM_DBL_OSTD_ACT_ACK_D2T_LSB (1U << 17) /* 1b */ 1889 #define SPM2ISP_ULTRAACK_D2T_LSB (1U << 18) /* 1b */ 1890 #define SPM2MM_ULTRAACK_D2T_LSB (1U << 19) /* 1b */ 1891 #define SPM2MD_ULTRAACK_D2T_LSB (1U << 20) /* 1b */ 1892 1893 /* SPM_BUS_PROTECT5_MASK_B (0x10006000 + 0x428) */ 1894 #define SPM_BUS_PROTECT5_MASK_B_LSB (1U << 0) /* 32b */ 1895 1896 /* SPM2MCUPM_CON (0x10006000 + 0x42C) */ 1897 #define SPM2MCUPM_SW_RST_B_LSB (1U << 0) /* 1b */ 1898 #define SPM2MCUPM_SW_INT_LSB (1U << 1) /* 1b */ 1899 1900 /* AP_MDSRC_REQ (0x10006000 + 0x430) */ 1901 #define AP_MDSMSRC_REQ_LSB (1U << 0) /* 1b */ 1902 #define AP_L1SMSRC_REQ_LSB (1U << 1) /* 1b */ 1903 #define AP_MD2SRC_REQ_LSB (1U << 2) /* 1b */ 1904 #define AP_MDSMSRC_ACK_LSB (1U << 4) /* 1b */ 1905 #define AP_L1SMSRC_ACK_LSB (1U << 5) /* 1b */ 1906 #define AP_MD2SRC_ACK_LSB (1U << 6) /* 1b */ 1907 1908 /* SPM2EMI_ENTER_ULPM (0x10006000 + 0x434) */ 1909 #define SPM2EMI_ENTER_ULPM_LSB (1U << 0) /* 1b */ 1910 1911 /* SPM2MD_DVFS_CON (0x10006000 + 0x438) */ 1912 #define SPM2MD_DVFS_CON_LSB (1U << 0) /* 32b */ 1913 1914 /* MD2SPM_DVFS_CON (0x10006000 + 0x43C) */ 1915 #define MD2SPM_DVFS_CON_LSB (1U << 0) /* 32b */ 1916 1917 /* SPM_BUS_PROTECT6_MASK_B (0x10006000 + 0X440) */ 1918 #define SPM_BUS_PROTECT6_MASK_B_LSB (1U << 0) /* 32b */ 1919 1920 /* SPM_BUS_PROTECT7_MASK_B (0x10006000 + 0x444) */ 1921 #define SPM_BUS_PROTECT7_MASK_B_LSB (1U << 0) /* 32b */ 1922 1923 /* SPM_BUS_PROTECT8_MASK_B (0x10006000 + 0x448) */ 1924 #define SPM_BUS_PROTECT8_MASK_B_LSB (1U << 0) /* 32b */ 1925 1926 /* SPM_PLL_CON (0x10006000 + 0x44C) */ 1927 #define SC_MAINPLLOUT_OFF_LSB (1U << 0) /* 1b */ 1928 #define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */ 1929 #define SC_SPAREPLLOUT_OFF_LSB (1U << 2) /* 2b */ 1930 #define SC_MAINPLL_OFF_LSB (1U << 4) /* 1b */ 1931 #define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */ 1932 #define SC_SPAREPLL_OFF_LSB (1U << 6) /* 2b */ 1933 #define SC_MAINPLL_S_OFF_LSB (1U << 8) /* 1b */ 1934 #define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */ 1935 #define SC_SPAREPLL_S_OFF_LSB (1U << 10) /* 2b */ 1936 #define SC_SPARE_CK_OFF_LSB (1U << 12) /* 4b */ 1937 #define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */ 1938 #define SC_MD32K_CK_OFF_LSB (1U << 17) /* 1b */ 1939 #define SC_CKSQ1_OFF_LSB (1U << 18) /* 1b */ 1940 #define SC_AXI_MEM_CK_OFF_LSB (1U << 19) /* 1b */ 1941 #define SC_CLK_BACKUP_LSB (1U << 20) /* 12b */ 1942 1943 /* RC_SPM_CTRL (0x10006000 + 0x450) */ 1944 #define SPM_AP_26M_RDY_LSB (1U << 0) /* 1b */ 1945 #define SPM2RC_DMY_CTRL_LSB (1U << 2) /* 6b */ 1946 #define RC2SPM_SRCCLKENO_0_ACK_LSB (1U << 16) /* 1b */ 1947 1948 /* SPM_DRAM_MCU_SW_CON_0 (0x10006000 + 0x454) */ 1949 #define SW_DDR_PST_REQ_LSB (1U << 0) /* 2b */ 1950 #define SW_DDR_PST_ABORT_REQ_LSB (1U << 2) /* 2b */ 1951 1952 /* SPM_DRAM_MCU_SW_CON_1 (0x10006000 + 0x458) */ 1953 #define SW_DDR_PST_CH0_LSB (1U << 0) /* 32b */ 1954 1955 /* SPM_DRAM_MCU_SW_CON_2 (0x10006000 + 0x45C) */ 1956 #define SW_DDR_PST_CH1_LSB (1U << 0) /* 32b */ 1957 1958 /* SPM_DRAM_MCU_SW_CON_3 (0x10006000 + 0x460) */ 1959 #define SW_DDR_RESERVED_CH0_LSB (1U << 0) /* 32b */ 1960 1961 /* SPM_DRAM_MCU_SW_CON_4 (0x10006000 + 0x464) */ 1962 #define SW_DDR_RESERVED_CH1_LSB (1U << 0) /* 32b */ 1963 1964 /* SPM_DRAM_MCU_STA_0 (0x10006000 + 0x468) */ 1965 #define SC_DDR_PST_ACK_LSB (1U << 0) /* 2b */ 1966 #define SC_DDR_PST_ABORT_ACK_LSB (1U << 2) /* 2b */ 1967 1968 /* SPM_DRAM_MCU_STA_1 (0x10006000 + 0x46C) */ 1969 #define SC_DDR_CUR_PST_STA_CH0_LSB (1U << 0) /* 32b */ 1970 1971 /* SPM_DRAM_MCU_STA_2 (0x10006000 + 0x470) */ 1972 #define SC_DDR_CUR_PST_STA_CH1_LSB (1U << 0) /* 32b */ 1973 1974 /* SPM_DRAM_MCU_SW_SEL_0 (0x10006000 + 0x474) */ 1975 #define SW_DDR_PST_REQ_SEL_LSB (1U << 0) /* 2b */ 1976 #define SW_DDR_PST_SEL_LSB (1U << 2) /* 2b */ 1977 #define SW_DDR_PST_ABORT_REQ_SEL_LSB (1U << 4) /* 2b */ 1978 #define SW_DDR_RESERVED_SEL_LSB (1U << 6) /* 2b */ 1979 #define SW_DDR_PST_ACK_SEL_LSB (1U << 8) /* 2b */ 1980 #define SW_DDR_PST_ABORT_ACK_SEL_LSB (1U << 10) /* 2b */ 1981 1982 /* RELAY_DVFS_LEVEL (0x10006000 + 0x478) */ 1983 #define RELAY_DVFS_LEVEL_LSB (1U << 0) /* 32b */ 1984 1985 /* DRAMC_DPY_CLK_SW_CON_0 (0x10006000 + 0x480) */ 1986 #define SW_PHYPLL_EN_LSB (1U << 0) /* 2b */ 1987 #define SW_DPY_VREF_EN_LSB (1U << 2) /* 2b */ 1988 #define SW_DPY_DLL_CK_EN_LSB (1U << 4) /* 2b */ 1989 #define SW_DPY_DLL_EN_LSB (1U << 6) /* 2b */ 1990 #define SW_DPY_2ND_DLL_EN_LSB (1U << 8) /* 2b */ 1991 #define SW_MEM_CK_OFF_LSB (1U << 10) /* 2b */ 1992 #define SW_DMSUS_OFF_LSB (1U << 12) /* 2b */ 1993 #define SW_DPY_MODE_SW_LSB (1U << 14) /* 2b */ 1994 #define SW_EMI_CLK_OFF_LSB (1U << 16) /* 2b */ 1995 #define SW_DDRPHY_FB_CK_EN_LSB (1U << 18) /* 2b */ 1996 #define SW_DR_GATE_RETRY_EN_LSB (1U << 20) /* 2b */ 1997 #define SW_DPHY_PRECAL_UP_LSB (1U << 24) /* 2b */ 1998 #define SW_DPY_BCLK_ENABLE_LSB (1U << 26) /* 2b */ 1999 #define SW_TX_TRACKING_DIS_LSB (1U << 28) /* 2b */ 2000 #define SW_DPHY_RXDLY_TRACKING_EN_LSB (1U << 30) /* 2b */ 2001 2002 /* DRAMC_DPY_CLK_SW_CON_1 (0x10006000 + 0x484) */ 2003 #define SW_SHU_RESTORE_LSB (1U << 0) /* 2b */ 2004 #define SW_DMYRD_MOD_LSB (1U << 2) /* 2b */ 2005 #define SW_DMYRD_INTV_LSB (1U << 4) /* 2b */ 2006 #define SW_DMYRD_EN_LSB (1U << 6) /* 2b */ 2007 #define SW_DRS_DIS_REQ_LSB (1U << 8) /* 2b */ 2008 #define SW_DR_SRAM_LOAD_LSB (1U << 10) /* 2b */ 2009 #define SW_DR_SRAM_RESTORE_LSB (1U << 12) /* 2b */ 2010 #define SW_DR_SHU_LEVEL_SRAM_LATCH_LSB (1U << 14) /* 2b */ 2011 #define SW_TX_TRACK_RETRY_EN_LSB (1U << 16) /* 2b */ 2012 #define SW_DPY_MIDPI_EN_LSB (1U << 18) /* 2b */ 2013 #define SW_DPY_PI_RESETB_EN_LSB (1U << 20) /* 2b */ 2014 #define SW_DPY_MCK8X_EN_LSB (1U << 22) /* 2b */ 2015 #define SW_DR_SHU_LEVEL_SRAM_CH0_LSB (1U << 24) /* 4b */ 2016 #define SW_DR_SHU_LEVEL_SRAM_CH1_LSB (1U << 28) /* 4b */ 2017 2018 /* DRAMC_DPY_CLK_SW_CON_2 (0x10006000 + 0x488) */ 2019 #define SW_DR_SHU_LEVEL_LSB (1U << 0) /* 2b */ 2020 #define SW_DR_SHU_EN_LSB (1U << 2) /* 1b */ 2021 #define SW_DR_SHORT_QUEUE_LSB (1U << 3) /* 1b */ 2022 #define SW_PHYPLL_MODE_SW_LSB (1U << 4) /* 1b */ 2023 #define SW_PHYPLL2_MODE_SW_LSB (1U << 5) /* 1b */ 2024 #define SW_PHYPLL_SHU_EN_LSB (1U << 6) /* 1b */ 2025 #define SW_PHYPLL2_SHU_EN_LSB (1U << 7) /* 1b */ 2026 #define SW_DR_RESERVED_0_LSB (1U << 24) /* 2b */ 2027 #define SW_DR_RESERVED_1_LSB (1U << 26) /* 2b */ 2028 #define SW_DR_RESERVED_2_LSB (1U << 28) /* 2b */ 2029 #define SW_DR_RESERVED_3_LSB (1U << 30) /* 2b */ 2030 2031 /* DRAMC_DPY_CLK_SW_CON_3 (0x10006000 + 0x48C) */ 2032 #define SC_DR_SHU_EN_ACK_LSB (1U << 0) /* 4b */ 2033 #define SC_EMI_CLK_OFF_ACK_LSB (1U << 4) /* 4b */ 2034 #define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 8) /* 4b */ 2035 #define SC_DRAMC_DFS_STA_LSB (1U << 12) /* 4b */ 2036 #define SC_DRS_DIS_ACK_LSB (1U << 16) /* 4b */ 2037 #define SC_DR_SRAM_LOAD_ACK_LSB (1U << 20) /* 4b */ 2038 #define SC_DR_SRAM_PLL_LOAD_ACK_LSB (1U << 24) /* 4b */ 2039 #define SC_DR_SRAM_RESTORE_ACK_LSB (1U << 28) /* 4b */ 2040 2041 /* DRAMC_DPY_CLK_SW_SEL_0 (0x10006000 + 0x490) */ 2042 #define SW_PHYPLL_EN_SEL_LSB (1U << 0) /* 2b */ 2043 #define SW_DPY_VREF_EN_SEL_LSB (1U << 2) /* 2b */ 2044 #define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 4) /* 2b */ 2045 #define SW_DPY_DLL_EN_SEL_LSB (1U << 6) /* 2b */ 2046 #define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 8) /* 2b */ 2047 #define SW_MEM_CK_OFF_SEL_LSB (1U << 10) /* 2b */ 2048 #define SW_DMSUS_OFF_SEL_LSB (1U << 12) /* 2b */ 2049 #define SW_DPY_MODE_SW_SEL_LSB (1U << 14) /* 2b */ 2050 #define SW_EMI_CLK_OFF_SEL_LSB (1U << 16) /* 2b */ 2051 #define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 18) /* 2b */ 2052 #define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 20) /* 2b */ 2053 #define SW_DPHY_PRECAL_UP_SEL_LSB (1U << 24) /* 2b */ 2054 #define SW_DPY_BCLK_ENABLE_SEL_LSB (1U << 26) /* 2b */ 2055 #define SW_TX_TRACKING_DIS_SEL_LSB (1U << 28) /* 2b */ 2056 #define SW_DPHY_RXDLY_TRACKING_EN_SEL_LSB (1U << 30) /* 2b */ 2057 2058 /* DRAMC_DPY_CLK_SW_SEL_1 (0x10006000 + 0x494) */ 2059 #define SW_SHU_RESTORE_SEL_LSB (1U << 0) /* 2b */ 2060 #define SW_DMYRD_MOD_SEL_LSB (1U << 2) /* 2b */ 2061 #define SW_DMYRD_INTV_SEL_LSB (1U << 4) /* 2b */ 2062 #define SW_DMYRD_EN_SEL_LSB (1U << 6) /* 2b */ 2063 #define SW_DRS_DIS_REQ_SEL_LSB (1U << 8) /* 2b */ 2064 #define SW_DR_SRAM_LOAD_SEL_LSB (1U << 10) /* 2b */ 2065 #define SW_DR_SRAM_RESTORE_SEL_LSB (1U << 12) /* 2b */ 2066 #define SW_DR_SHU_LEVEL_SRAM_LATCH_SEL_LSB (1U << 14) /* 2b */ 2067 #define SW_TX_TRACK_RETRY_EN_SEL_LSB (1U << 16) /* 2b */ 2068 #define SW_DPY_MIDPI_EN_SEL_LSB (1U << 18) /* 2b */ 2069 #define SW_DPY_PI_RESETB_EN_SEL_LSB (1U << 20) /* 2b */ 2070 #define SW_DPY_MCK8X_EN_SEL_LSB (1U << 22) /* 2b */ 2071 #define SW_DR_SHU_LEVEL_SRAM_SEL_LSB (1U << 24) /* 2b */ 2072 2073 /* DRAMC_DPY_CLK_SW_SEL_2 (0x10006000 + 0x498) */ 2074 #define SW_DR_SHU_LEVEL_SEL_LSB (1U << 0) /* 1b */ 2075 #define SW_DR_SHU_EN_SEL_LSB (1U << 2) /* 1b */ 2076 #define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 3) /* 1b */ 2077 #define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 4) /* 1b */ 2078 #define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 5) /* 1b */ 2079 #define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 6) /* 1b */ 2080 #define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 7) /* 1b */ 2081 #define SW_DR_RESERVED_0_SEL_LSB (1U << 24) /* 2b */ 2082 #define SW_DR_RESERVED_1_SEL_LSB (1U << 26) /* 2b */ 2083 #define SW_DR_RESERVED_2_SEL_LSB (1U << 28) /* 2b */ 2084 #define SW_DR_RESERVED_3_SEL_LSB (1U << 30) /* 2b */ 2085 2086 /* DRAMC_DPY_CLK_SW_SEL_3 (0x10006000 + 0x49C) */ 2087 #define SC_DR_SHU_EN_ACK_SEL_LSB (1U << 0) /* 4b */ 2088 #define SC_EMI_CLK_OFF_ACK_SEL_LSB (1U << 4) /* 4b */ 2089 #define SC_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 8) /* 4b */ 2090 #define SC_DRAMC_DFS_STA_SEL_LSB (1U << 12) /* 4b */ 2091 #define SC_DRS_DIS_ACK_SEL_LSB (1U << 16) /* 4b */ 2092 #define SC_DR_SRAM_LOAD_ACK_SEL_LSB (1U << 20) /* 4b */ 2093 #define SC_DR_SRAM_PLL_LOAD_ACK_SEL_LSB (1U << 24) /* 4b */ 2094 #define SC_DR_SRAM_RESTORE_ACK_SEL_LSB (1U << 28) /* 4b */ 2095 2096 /* DRAMC_DPY_CLK_SPM_CON (0x10006000 + 0x4A0) */ 2097 #define SC_DMYRD_EN_MOD_SEL_PCM_LSB (1U << 0) /* 1b */ 2098 #define SC_DMYRD_INTV_SEL_PCM_LSB (1U << 1) /* 1b */ 2099 #define SC_DMYRD_EN_PCM_LSB (1U << 2) /* 1b */ 2100 #define SC_DRS_DIS_REQ_PCM_LSB (1U << 3) /* 1b */ 2101 #define SC_DR_SHU_LEVEL_SRAM_PCM_LSB (1U << 4) /* 4b */ 2102 #define SC_DR_GATE_RETRY_EN_PCM_LSB (1U << 8) /* 1b */ 2103 #define SC_DR_SHORT_QUEUE_PCM_LSB (1U << 9) /* 1b */ 2104 #define SC_DPY_MIDPI_EN_PCM_LSB (1U << 10) /* 1b */ 2105 #define SC_DPY_PI_RESETB_EN_PCM_LSB (1U << 11) /* 1b */ 2106 #define SC_DPY_MCK8X_EN_PCM_LSB (1U << 12) /* 1b */ 2107 #define SC_DR_RESERVED_0_PCM_LSB (1U << 13) /* 1b */ 2108 #define SC_DR_RESERVED_1_PCM_LSB (1U << 14) /* 1b */ 2109 #define SC_DR_RESERVED_2_PCM_LSB (1U << 15) /* 1b */ 2110 #define SC_DR_RESERVED_3_PCM_LSB (1U << 16) /* 1b */ 2111 #define SC_DMDRAMCSHU_ACK_ALL_LSB (1U << 24) /* 1b */ 2112 #define SC_EMI_CLK_OFF_ACK_ALL_LSB (1U << 25) /* 1b */ 2113 #define SC_DR_SHORT_QUEUE_ACK_ALL_LSB (1U << 26) /* 1b */ 2114 #define SC_DRAMC_DFS_STA_ALL_LSB (1U << 27) /* 1b */ 2115 #define SC_DRS_DIS_ACK_ALL_LSB (1U << 28) /* 1b */ 2116 #define SC_DR_SRAM_LOAD_ACK_ALL_LSB (1U << 29) /* 1b */ 2117 #define SC_DR_SRAM_PLL_LOAD_ACK_ALL_LSB (1U << 30) /* 1b */ 2118 #define SC_DR_SRAM_RESTORE_ACK_ALL_LSB (1U << 31) /* 1b */ 2119 2120 /* SPM_DVFS_LEVEL (0x10006000 + 0x4A4) */ 2121 #define SPM_DVFS_LEVEL_LSB (1U << 0) /* 32b */ 2122 2123 /* SPM_CIRQ_CON (0x10006000 + 0x4A8) */ 2124 #define CIRQ_CLK_SEL_LSB (1U << 0) /* 1b */ 2125 2126 /* SPM_DVFS_MISC (0x10006000 + 0x4AC) */ 2127 #define MSDC_DVFS_REQUEST_LSB (1U << 0) /* 1b */ 2128 #define SPM2EMI_SLP_PROT_EN_LSB (1U << 1) /* 1b */ 2129 #define SPM_DVFS_FORCE_ENABLE_LSB (1U << 2) /* 1b */ 2130 #define FORCE_DVFS_WAKE_LSB (1U << 3) /* 1b */ 2131 #define SPM_DVFSRC_ENABLE_LSB (1U << 4) /* 1b */ 2132 #define SPM_DVFS_DONE_LSB (1U << 5) /* 1b */ 2133 #define DVFSRC_IRQ_WAKEUP_EVENT_MASK_LSB (1U << 6) /* 1b */ 2134 #define SPM2RC_EVENT_ABORT_LSB (1U << 7) /* 1b */ 2135 #define EMI_SLP_IDLE_LSB (1U << 14) /* 1b */ 2136 #define SDIO_READY_TO_SPM_LSB (1U << 15) /* 1b */ 2137 2138 /* RG_MODULE_SW_CG_0_MASK_REQ_0 (0x10006000 + 0x4B4) */ 2139 #define RG_MODULE_SW_CG_0_MASK_REQ_0_LSB (1U << 0) /* 32b */ 2140 2141 /* RG_MODULE_SW_CG_0_MASK_REQ_1 (0x10006000 + 0x4B8) */ 2142 #define RG_MODULE_SW_CG_0_MASK_REQ_1_LSB (1U << 0) /* 32b */ 2143 2144 /* RG_MODULE_SW_CG_0_MASK_REQ_2 (0x10006000 + 0x4BC) */ 2145 #define RG_MODULE_SW_CG_0_MASK_REQ_2_LSB (1U << 0) /* 32b */ 2146 2147 /* RG_MODULE_SW_CG_1_MASK_REQ_0 (0x10006000 + 0x4C0) */ 2148 #define RG_MODULE_SW_CG_1_MASK_REQ_0_LSB (1U << 0) /* 32b */ 2149 2150 /* RG_MODULE_SW_CG_1_MASK_REQ_1 (0x10006000 + 0x4C4) */ 2151 #define RG_MODULE_SW_CG_1_MASK_REQ_1_LSB (1U << 0) /* 32b */ 2152 2153 /* RG_MODULE_SW_CG_1_MASK_REQ_2 (0x10006000 + 0x4C8) */ 2154 #define RG_MODULE_SW_CG_1_MASK_REQ_2_LSB (1U << 0) /* 32b */ 2155 2156 /* RG_MODULE_SW_CG_2_MASK_REQ_0 (0x10006000 + 0x4CC) */ 2157 #define RG_MODULE_SW_CG_2_MASK_REQ_0_LSB (1U << 0) /* 32b */ 2158 2159 /* RG_MODULE_SW_CG_2_MASK_REQ_1 (0x10006000 + 0x4D0) */ 2160 #define RG_MODULE_SW_CG_2_MASK_REQ_1_LSB (1U << 0) /* 32b */ 2161 2162 /* RG_MODULE_SW_CG_2_MASK_REQ_2 (0x10006000 + 0x4D4) */ 2163 #define RG_MODULE_SW_CG_2_MASK_REQ_2_LSB (1U << 0) /* 32b */ 2164 2165 /* RG_MODULE_SW_CG_3_MASK_REQ_0 (0x10006000 + 0x4D8) */ 2166 #define RG_MODULE_SW_CG_3_MASK_REQ_0_LSB (1U << 0) /* 32b */ 2167 2168 /* RG_MODULE_SW_CG_3_MASK_REQ_1 (0x10006000 + 0x4DC) */ 2169 #define RG_MODULE_SW_CG_3_MASK_REQ_1_LSB (1U << 0) /* 32b */ 2170 2171 /* RG_MODULE_SW_CG_3_MASK_REQ_2 (0x10006000 + 0x4E0) */ 2172 #define RG_MODULE_SW_CG_3_MASK_REQ_2_LSB (1U << 0) /* 32b */ 2173 2174 /* PWR_STATUS_MASK_REQ_0 (0x10006000 + 0x4E4) */ 2175 #define PWR_STATUS_MASK_REQ_0_LSB (1U << 0) /* 32b */ 2176 2177 /* PWR_STATUS_MASK_REQ_1 (0x10006000 + 0x4E8) */ 2178 #define PWR_STATUS_MASK_REQ_1_LSB (1U << 0) /* 32b */ 2179 2180 /* PWR_STATUS_MASK_REQ_2 (0x10006000 + 0x4EC) */ 2181 #define PWR_STATUS_MASK_REQ_2_LSB (1U << 0) /* 32b */ 2182 2183 /* SPM_CG_CHECK_CON (0x10006000 + 0x4F0) */ 2184 #define APMIXEDSYS_BUSY_MASK_REQ_0_LSB (1U << 0) /* 5b */ 2185 #define APMIXEDSYS_BUSY_MASK_REQ_1_LSB (1U << 8) /* 5b */ 2186 #define APMIXEDSYS_BUSY_MASK_REQ_2_LSB (1U << 16) /* 5b */ 2187 #define AUDIOSYS_BUSY_MASK_REQ_0_LSB (1U << 24) /* 1b */ 2188 #define AUDIOSYS_BUSY_MASK_REQ_1_LSB (1U << 25) /* 1b */ 2189 #define AUDIOSYS_BUSY_MASK_REQ_2_LSB (1U << 26) /* 1b */ 2190 #define SSUSB_BUSY_MASK_REQ_0_LSB (1U << 27) /* 1b */ 2191 #define SSUSB_BUSY_MASK_REQ_1_LSB (1U << 28) /* 1b */ 2192 #define SSUSB_BUSY_MASK_REQ_2_LSB (1U << 29) /* 1b */ 2193 2194 /* SPM_SRC_RDY_STA (0x10006000 + 0x4F4) */ 2195 #define SPM_INFRA_INTERNAL_ACK_LSB (1U << 0) /* 1b */ 2196 #define SPM_VRF18_INTERNAL_ACK_LSB (1U << 1) /* 1b */ 2197 2198 /* SPM_DVS_DFS_LEVEL (0x10006000 + 0x4F8) */ 2199 #define SPM_DFS_LEVEL_LSB (1U << 0) /* 16b */ 2200 #define SPM_DVS_LEVEL_LSB (1U << 16) /* 16b */ 2201 2202 /* SPM_FORCE_DVFS (0x10006000 + 0x4FC) */ 2203 #define FORCE_DVFS_LEVEL_LSB (1U << 0) /* 32b */ 2204 2205 /* SPM_SW_FLAG_0 (0x10006000 + 0x600) */ 2206 #define SPM_SW_FLAG_LSB (1U << 0) /* 32b */ 2207 2208 /* SPM_SW_DEBUG_0 (0x10006000 + 0x604) */ 2209 #define SPM_SW_DEBUG_0_LSB (1U << 0) /* 32b */ 2210 2211 /* SPM_SW_FLAG_1 (0x10006000 + 0x608) */ 2212 #define SPM_SW_FLAG_1_LSB (1U << 0) /* 32b */ 2213 2214 /* SPM_SW_DEBUG_1 (0x10006000 + 0x60C) */ 2215 #define SPM_SW_DEBUG_1_LSB (1U << 0) /* 32b */ 2216 2217 /* SPM_SW_RSV_0 (0x10006000 + 0x610) */ 2218 #define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */ 2219 2220 /* SPM_SW_RSV_1 (0x10006000 + 0x614) */ 2221 #define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */ 2222 2223 /* SPM_SW_RSV_2 (0x10006000 + 0x618) */ 2224 #define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */ 2225 2226 /* SPM_SW_RSV_3 (0x10006000 + 0x61C) */ 2227 #define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */ 2228 2229 /* SPM_SW_RSV_4 (0x10006000 + 0x620) */ 2230 #define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */ 2231 2232 /* SPM_SW_RSV_5 (0x10006000 + 0x624) */ 2233 #define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */ 2234 2235 /* SPM_SW_RSV_6 (0x10006000 + 0x628) */ 2236 #define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */ 2237 2238 /* SPM_SW_RSV_7 (0x10006000 + 0x62C) */ 2239 #define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */ 2240 2241 /* SPM_SW_RSV_8 (0x10006000 + 0x630) */ 2242 #define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */ 2243 2244 /* SPM_BK_WAKE_EVENT (0x10006000 + 0x634) */ 2245 #define SPM_BK_WAKE_EVENT_LSB (1U << 0) /* 32b */ 2246 2247 /* SPM_BK_VTCXO_DUR (0x10006000 + 0x638) */ 2248 #define SPM_BK_VTCXO_DUR_LSB (1U << 0) /* 32b */ 2249 2250 /* SPM_BK_WAKE_MISC (0x10006000 + 0x63C) */ 2251 #define SPM_BK_WAKE_MISC_LSB (1U << 0) /* 32b */ 2252 2253 /* SPM_BK_PCM_TIMER (0x10006000 + 0x640) */ 2254 #define SPM_BK_PCM_TIMER_LSB (1U << 0) /* 32b */ 2255 2256 /* SPM_RSV_CON_0 (0x10006000 + 0x650) */ 2257 #define SPM_RSV_CON_0_LSB (1U << 0) /* 32b */ 2258 2259 /* SPM_RSV_CON_1 (0x10006000 + 0x654) */ 2260 #define SPM_RSV_CON_1_LSB (1U << 0) /* 32b */ 2261 2262 /* SPM_RSV_STA_0 (0x10006000 + 0x658) */ 2263 #define SPM_RSV_STA_0_LSB (1U << 0) /* 32b */ 2264 2265 /* SPM_RSV_STA_1 (0x10006000 + 0x65C) */ 2266 #define SPM_RSV_STA_1_LSB (1U << 0) /* 32b */ 2267 2268 /* SPM_SPARE_CON (0x10006000 + 0x660) */ 2269 #define SPM_SPARE_CON_LSB (1U << 0) /* 32b */ 2270 2271 /* SPM_SPARE_CON_SET (0x10006000 + 0x664) */ 2272 #define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */ 2273 2274 /* SPM_SPARE_CON_CLR (0x10006000 + 0x668) */ 2275 #define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ 2276 2277 /* SPM_CROSS_WAKE_M00_REQ (0x10006000 + 0x66C) */ 2278 #define SPM_CROSS_WAKE_M00_REQ_LSB (1U << 0) /* 4b */ 2279 #define SPM_CROSS_WAKE_M00_CHK_LSB (1U << 4) /* 4b */ 2280 2281 /* SPM_CROSS_WAKE_M01_REQ (0x10006000 + 0x670) */ 2282 #define SPM_CROSS_WAKE_M01_REQ_LSB (1U << 0) /* 4b */ 2283 #define SPM_CROSS_WAKE_M01_CHK_LSB (1U << 4) /* 4b */ 2284 2285 /* SPM_CROSS_WAKE_M02_REQ (0x10006000 + 0x674) */ 2286 #define SPM_CROSS_WAKE_M02_REQ_LSB (1U << 0) /* 4b */ 2287 #define SPM_CROSS_WAKE_M02_CHK_LSB (1U << 4) /* 4b */ 2288 2289 /* SPM_CROSS_WAKE_M03_REQ (0x10006000 + 0x678) */ 2290 #define SPM_CROSS_WAKE_M03_REQ_LSB (1U << 0) /* 4b */ 2291 #define SPM_CROSS_WAKE_M03_CHK_LSB (1U << 4) /* 4b */ 2292 2293 /* SCP_VCORE_LEVEL (0x10006000 + 0x67C) */ 2294 #define SCP_VCORE_LEVEL_LSB (1U << 0) /* 16b */ 2295 2296 /* SC_MM_CK_SEL_CON (0x10006000 + 0x680) */ 2297 #define SC_MM_CK_SEL_LSB (1U << 0) /* 4b */ 2298 #define SC_MM_CK_SEL_EN_LSB (1U << 4) /* 1b */ 2299 2300 /* SPARE_ACK_MASK (0x10006000 + 0x684) */ 2301 #define SPARE_ACK_MASK_B_LSB (1U << 0) /* 32b */ 2302 2303 /* SPM_SPARE_FUNCTION (0x10006000 + 0x688) */ 2304 #define SPM_SPARE_FUNCTION_LSB (1U << 0) /* 32b */ 2305 2306 /* SPM_DV_CON_0 (0x10006000 + 0x68C) */ 2307 #define SPM_DV_CON_0_LSB (1U << 0) /* 32b */ 2308 2309 /* SPM_DV_CON_1 (0x10006000 + 0x690) */ 2310 #define SPM_DV_CON_1_LSB (1U << 0) /* 32b */ 2311 2312 /* SPM_DV_STA (0x10006000 + 0x694) */ 2313 #define SPM_DV_STA_LSB (1U << 0) /* 32b */ 2314 2315 /* CONN_XOWCN_DEBUG_EN (0x10006000 + 0x698) */ 2316 #define CONN_XOWCN_DEBUG_EN_LSB (1U << 0) /* 1b */ 2317 2318 /* SPM_SEMA_M0 (0x10006000 + 0x69C) */ 2319 #define SPM_SEMA_M0_LSB (1U << 0) /* 8b */ 2320 2321 /* SPM_SEMA_M1 (0x10006000 + 0x6A0) */ 2322 #define SPM_SEMA_M1_LSB (1U << 0) /* 8b */ 2323 2324 /* SPM_SEMA_M2 (0x10006000 + 0x6A4) */ 2325 #define SPM_SEMA_M2_LSB (1U << 0) /* 8b */ 2326 2327 /* SPM_SEMA_M3 (0x10006000 + 0x6A8) */ 2328 #define SPM_SEMA_M3_LSB (1U << 0) /* 8b */ 2329 2330 /* SPM_SEMA_M4 (0x10006000 + 0x6AC) */ 2331 #define SPM_SEMA_M4_LSB (1U << 0) /* 8b */ 2332 2333 /* SPM_SEMA_M5 (0x10006000 + 0x6B0) */ 2334 #define SPM_SEMA_M5_LSB (1U << 0) /* 8b */ 2335 2336 /* SPM_SEMA_M6 (0x10006000 + 0x6B4) */ 2337 #define SPM_SEMA_M6_LSB (1U << 0) /* 8b */ 2338 2339 /* SPM_SEMA_M7 (0x10006000 + 0x6B8) */ 2340 #define SPM_SEMA_M7_LSB (1U << 0) /* 8b */ 2341 2342 /* SPM2ADSP_MAILBOXi (0x10006000 + 0x6BC) */ 2343 #define SPM2ADSP_MAILBOX_LSB (1U << 0) /* 32b */ 2344 2345 /* ADSP2SPM_MAILBOX (0x10006000 + 0x6C0) */ 2346 #define ADSP2SPM_MAILBOX_LSB (1U << 0) /* 32b */ 2347 2348 /* SPM_ADSP_IRQ (0x10006000 + 0x6C4) */ 2349 #define SC_SPM2ADSP_WAKEUP_LSB (1U << 0) /* 1b */ 2350 #define SPM_ADSP_IRQ_SC_ADSP2SPM_WAKEUP_LSB (1U << 4) /* 1b */ 2351 2352 /* SPM_MD32_IRQ (0x10006000 + 0x6C8) */ 2353 #define SC_SPM2SSPM_WAKEUP_LSB (1U << 0) /* 4b */ 2354 #define SPM_MD32_IRQ_SC_SSPM2SPM_WAKEUP_LSB (1U << 4) /* 4b */ 2355 2356 /* SPM2PMCU_MAILBOX_0 (0x10006000 + 0x6CC) */ 2357 #define SPM2PMCU_MAILBOX_0_LSB (1U << 0) /* 32b */ 2358 2359 /* SPM2PMCU_MAILBOX_1 (0x10006000 + 0x6D0) */ 2360 #define SPM2PMCU_MAILBOX_1_LSB (1U << 0) /* 32b */ 2361 2362 /* SPM2PMCU_MAILBOX_2 (0x10006000 + 0x6D4) */ 2363 #define SPM2PMCU_MAILBOX_2_LSB (1U << 0) /* 32b */ 2364 2365 /* SPM2PMCU_MAILBOX_3 (0x10006000 + 0x6D8) */ 2366 #define SPM2PMCU_MAILBOX_3_LSB (1U << 0) /* 32b */ 2367 2368 /* PMCU2SPM_MAILBOX_0 (0x10006000 + 0x6DC) */ 2369 #define PMCU2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ 2370 2371 /* PMCU2SPM_MAILBOX_1 (0x10006000 + 0x6E0) */ 2372 #define PMCU2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ 2373 2374 /* PMCU2SPM_MAILBOX_2 (0x10006000 + 0x6E4) */ 2375 #define PMCU2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ 2376 2377 /* PMCU2SPM_MAILBOX_3 (0x10006000 + 0x6E8) */ 2378 #define PMCU2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ 2379 2380 /* UFS_PSRI_SW (0x10006000 + 0x6EC) */ 2381 #define UFS_PSRI_SW_LSB (1U << 0) /* 1b */ 2382 2383 /* UFS_PSRI_SW_SET (0x10006000 + 0x6F0) */ 2384 #define UFS_PSRI_SW_SET_LSB (1U << 0) /* 1b */ 2385 2386 /* UFS_PSRI_SW_CLR (0x10006000 + 0x6F4) */ 2387 #define UFS_PSRI_SW_CLR_LSB (1U << 0) /* 1b */ 2388 2389 /* SPM_AP_SEMA (0x10006000 + 0x6F8) */ 2390 #define SPM_AP_SEMA_LSB (1U << 0) /* 1b */ 2391 2392 /* SPM_SPM_SEMA (0x10006000 + 0x6FC) */ 2393 #define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */ 2394 2395 /* SPM_DVFS_CON (0x10006000 + 0x700) */ 2396 #define SPM_DVFS_CON_LSB (1U << 0) /* 32b */ 2397 2398 /* SPM_DVFS_CON_STA (0x10006000 + 0x704) */ 2399 #define SPM_DVFS_CON_STA_LSB (1U << 0) /* 32b */ 2400 2401 /* SPM_PMIC_SPMI_CON (0x10006000 + 0x708) */ 2402 #define SPM_PMIC_SPMI_CMD_LSB (1U << 0) /* 2b */ 2403 #define SPM_PMIC_SPMI_SLAVEID_LSB (1U << 2) /* 4b */ 2404 #define SPM_PMIC_SPMI_PMIFID_LSB (1U << 6) /* 1b */ 2405 #define SPM_PMIC_SPMI_DBCNT_LSB (1U << 7) /* 1b */ 2406 2407 /* SPM_DVFS_CMD0 (0x10006000 + 0x710) */ 2408 #define SPM_DVFS_CMD0_LSB (1U << 0) /* 32b */ 2409 2410 /* SPM_DVFS_CMD1 (0x10006000 + 0x714) */ 2411 #define SPM_DVFS_CMD1_LSB (1U << 0) /* 32b */ 2412 2413 /* SPM_DVFS_CMD2 (0x10006000 + 0x718) */ 2414 #define SPM_DVFS_CMD2_LSB (1U << 0) /* 32b */ 2415 2416 /* SPM_DVFS_CMD3 (0x10006000 + 0x71C) */ 2417 #define SPM_DVFS_CMD3_LSB (1U << 0) /* 32b */ 2418 2419 /* SPM_DVFS_CMD4 (0x10006000 + 0x720) */ 2420 #define SPM_DVFS_CMD4_LSB (1U << 0) /* 32b */ 2421 2422 /* SPM_DVFS_CMD5 (0x10006000 + 0x724) */ 2423 #define SPM_DVFS_CMD5_LSB (1U << 0) /* 32b */ 2424 2425 /* SPM_DVFS_CMD6 (0x10006000 + 0x728) */ 2426 #define SPM_DVFS_CMD6_LSB (1U << 0) /* 32b */ 2427 2428 /* SPM_DVFS_CMD7 (0x10006000 + 0x72C) */ 2429 #define SPM_DVFS_CMD7_LSB (1U << 0) /* 32b */ 2430 2431 /* SPM_DVFS_CMD8 (0x10006000 + 0x730) */ 2432 #define SPM_DVFS_CMD8_LSB (1U << 0) /* 32b */ 2433 2434 /* SPM_DVFS_CMD9 (0x10006000 + 0x734) */ 2435 #define SPM_DVFS_CMD9_LSB (1U << 0) /* 32b */ 2436 2437 /* SPM_DVFS_CMD10 (0x10006000 + 0x738) */ 2438 #define SPM_DVFS_CMD10_LSB (1U << 0) /* 32b */ 2439 2440 /* SPM_DVFS_CMD11 (0x10006000 + 0x73C) */ 2441 #define SPM_DVFS_CMD11_LSB (1U << 0) /* 32b */ 2442 2443 /* SPM_DVFS_CMD12 (0x10006000 + 0x740) */ 2444 #define SPM_DVFS_CMD12_LSB (1U << 0) /* 32b */ 2445 2446 /* SPM_DVFS_CMD13 (0x10006000 + 0x744) */ 2447 #define SPM_DVFS_CMD13_LSB (1U << 0) /* 32b */ 2448 2449 /* SPM_DVFS_CMD14 (0x10006000 + 0x748) */ 2450 #define SPM_DVFS_CMD14_LSB (1U << 0) /* 32b */ 2451 2452 /* SPM_DVFS_CMD15 (0x10006000 + 0x74C) */ 2453 #define SPM_DVFS_CMD15_LSB (1U << 0) /* 32b */ 2454 2455 /* SPM_DVFS_CMD16i (0x10006000 + 0x750) */ 2456 #define SPM_DVFS_CMD16_LSB (1U << 0) /* 32b */ 2457 2458 /* SPM_DVFS_CMD17 (0x10006000 + 0x754) */ 2459 #define SPM_DVFS_CMD17_LSB (1U << 0) /* 32b */ 2460 2461 /* SPM_DVFS_CMD18 (0x10006000 + 0x758) */ 2462 #define SPM_DVFS_CMD18_LSB (1U << 0) /* 32b */ 2463 2464 /* SPM_DVFS_CMD19 (0x10006000 + 0x75C) */ 2465 #define SPM_DVFS_CMD19_LSB (1U << 0) /* 32b */ 2466 2467 /* SPM_DVFS_CMD20 (0x10006000 + 0x760) */ 2468 #define SPM_DVFS_CMD20_LSB (1U << 0) /* 32b */ 2469 2470 /* SPM_DVFS_CMD21 (0x10006000 + 0x764) */ 2471 #define SPM_DVFS_CMD21_LSB (1U << 0) /* 32b */ 2472 2473 /* SPM_DVFS_CMD22 (0x10006000 + 0x768) */ 2474 #define SPM_DVFS_CMD22_LSB (1U << 0) /* 32b */ 2475 2476 /* SPM_DVFS_CMD23 (0x10006000 + 0x76C) */ 2477 #define SPM_DVFS_CMD23_LSB (1U << 0) /* 32b */ 2478 2479 /* SYS_TIMER_VALUE_L (0x10006000 + 0x770) */ 2480 #define SYS_TIMER_VALUE_L_LSB (1U << 0) /* 32b */ 2481 2482 /* SYS_TIMER_VALUE_H (0x10006000 + 0x774) */ 2483 #define SYS_TIMER_VALUE_H_LSB (1U << 0) /* 32b */ 2484 2485 /* SYS_TIMER_START_L (0x10006000 + 0x778) */ 2486 #define SYS_TIMER_START_L_LSB (1U << 0) /* 32b */ 2487 2488 /* SYS_TIMER_START_H (0x10006000 + 0x77C) */ 2489 #define SYS_TIMER_START_H_LSB (1U << 0) /* 32b */ 2490 2491 /* SYS_TIMER_LATCH_L_00 (0x10006000 + 0x780) */ 2492 #define SYS_TIMER_LATCH_L_00_LSB (1U << 0) /* 32b */ 2493 2494 /* SYS_TIMER_LATCH_H_00 (0x10006000 + 0x784) */ 2495 #define SYS_TIMER_LATCH_H_00_LSB (1U << 0) /* 32b */ 2496 2497 /* SYS_TIMER_LATCH_L_01 (0x10006000 + 0x788) */ 2498 #define SYS_TIMER_LATCH_L_01_LSB (1U << 0) /* 32b */ 2499 2500 /* SYS_TIMER_LATCH_H_01 (0x10006000 + 0x78C) */ 2501 #define SYS_TIMER_LATCH_H_01_LSB (1U << 0) /* 32b */ 2502 2503 /* SYS_TIMER_LATCH_L_02 (0x10006000 + 0x790) */ 2504 #define SYS_TIMER_LATCH_L_02_LSB (1U << 0) /* 32b */ 2505 2506 /* SYS_TIMER_LATCH_H_02 (0x10006000 + 0x794) */ 2507 #define SYS_TIMER_LATCH_H_02_LSB (1U << 0) /* 32b */ 2508 2509 /* SYS_TIMER_LATCH_L_03 (0x10006000 + 0x798) */ 2510 #define SYS_TIMER_LATCH_L_03_LSB (1U << 0) /* 32b */ 2511 2512 /* SYS_TIMER_LATCH_H_03 (0x10006000 + 0x79C) */ 2513 #define SYS_TIMER_LATCH_H_03_LSB (1U << 0) /* 32b */ 2514 2515 /* SYS_TIMER_LATCH_L_04 (0x10006000 + 0x7A0) */ 2516 #define SYS_TIMER_LATCH_L_04_LSB (1U << 0) /* 32b */ 2517 2518 /* SYS_TIMER_LATCH_H_04 (0x10006000 + 0x7A4) */ 2519 #define SYS_TIMER_LATCH_H_04_LSB (1U << 0) /* 32b */ 2520 2521 /* SYS_TIMER_LATCH_L_05 (0x10006000 + 0x7A8) */ 2522 #define SYS_TIMER_LATCH_L_05_LSB (1U << 0) /* 32b */ 2523 2524 /* SYS_TIMER_LATCH_H_05 (0x10006000 + 0x7AC) */ 2525 #define SYS_TIMER_LATCH_H_05_LSB (1U << 0) /* 32b */ 2526 2527 /* SYS_TIMER_LATCH_L_06 (0x10006000 + 0x7B0) */ 2528 #define SYS_TIMER_LATCH_L_06_LSB (1U << 0) /* 32b */ 2529 2530 /* SYS_TIMER_LATCH_H_06 (0x10006000 + 0x7B4) */ 2531 #define SYS_TIMER_LATCH_H_06_LSB (1U << 0) /* 32b */ 2532 2533 /* SYS_TIMER_LATCH_L_07 (0x10006000 + 0x7B8) */ 2534 #define SYS_TIMER_LATCH_L_07_LSB (1U << 0) /* 32b */ 2535 2536 /* SYS_TIMER_LATCH_H_07 (0x10006000 + 0x7BC) */ 2537 #define SYS_TIMER_LATCH_H_07_LSB (1U << 0) /* 32b */ 2538 2539 /* SYS_TIMER_LATCH_L_08 (0x10006000 + 0x7C0) */ 2540 #define SYS_TIMER_LATCH_L_08_LSB (1U << 0) /* 32b */ 2541 2542 /* SYS_TIMER_LATCH_H_08 (0x10006000 + 0x7C4) */ 2543 #define SYS_TIMER_LATCH_H_08_LSB (1U << 0) /* 32b */ 2544 2545 /* SYS_TIMER_LATCH_L_09 (0x10006000 + 0x7C8) */ 2546 #define SYS_TIMER_LATCH_L_09_LSB (1U << 0) /* 32b */ 2547 2548 /* SYS_TIMER_LATCH_H_09 (0x10006000 + 0x7CC) */ 2549 #define SYS_TIMER_LATCH_H_09_LSB (1U << 0) /* 32b */ 2550 2551 /* SYS_TIMER_LATCH_L_10 (0x10006000 + 0x7D0) */ 2552 #define SYS_TIMER_LATCH_L_10_LSB (1U << 0) /* 32b */ 2553 2554 /* SYS_TIMER_LATCH_H_10 (0x10006000 + 0x7D4) */ 2555 #define SYS_TIMER_LATCH_H_10_LSB (1U << 0) /* 32b */ 2556 2557 /* SYS_TIMER_LATCH_L_11 (0x10006000 + 0x7D8) */ 2558 #define SYS_TIMER_LATCH_L_11_LSB (1U << 0) /* 32b */ 2559 2560 /* SYS_TIMER_LATCH_H_11 (0x10006000 + 0x7DC) */ 2561 #define SYS_TIMER_LATCH_H_11_LSB (1U << 0) /* 32b */ 2562 2563 /* SYS_TIMER_LATCH_L_12 (0x10006000 + 0x7E0) */ 2564 #define SYS_TIMER_LATCH_L_12_LSB (1U << 0) /* 32b */ 2565 2566 /* SYS_TIMER_LATCH_H_12 (0x10006000 + 0x7E4) */ 2567 #define SYS_TIMER_LATCH_H_12_LSB (1U << 0) /* 32b */ 2568 2569 /* SYS_TIMER_LATCH_L_13 (0x10006000 + 0x7E8) */ 2570 #define SYS_TIMER_LATCH_L_13_LSB (1U << 0) /* 32b */ 2571 2572 /* SYS_TIMER_LATCH_H_13 (0x10006000 + 0x7EC) */ 2573 #define SYS_TIMER_LATCH_H_13_LSB (1U << 0) /* 32b */ 2574 2575 /* SYS_TIMER_LATCH_L_14 (0x10006000 + 0x7F0) */ 2576 #define SYS_TIMER_LATCH_L_14_LSB (1U << 0) /* 32b */ 2577 2578 /* SYS_TIMER_LATCH_H_14 (0x10006000 + 0x7F4) */ 2579 #define SYS_TIMER_LATCH_H_14_LSB (1U << 0) /* 32b */ 2580 2581 /* SYS_TIMER_LATCH_L_15 (0x10006000 + 0x7F8) */ 2582 #define SYS_TIMER_LATCH_L_15_LSB (1U << 0) /* 32b */ 2583 2584 /* SYS_TIMER_LATCH_H_15 (0x10006000 + 0x7FC) */ 2585 #define SYS_TIMER_LATCH_H_15_LSB (1U << 0) /* 32b */ 2586 2587 /* PCM_WDT_LATCH_0 (0x10006000 + 0x800) */ 2588 #define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */ 2589 2590 /* PCM_WDT_LATCH_1 (0x10006000 + 0x804) */ 2591 #define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */ 2592 2593 /* PCM_WDT_LATCH_2 (0x10006000 + 0x808) */ 2594 #define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */ 2595 2596 /* PCM_WDT_LATCH_3 (0x10006000 + 0x80C) */ 2597 #define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */ 2598 2599 /* PCM_WDT_LATCH_4 (0x10006000 + 0x810) */ 2600 #define PCM_WDT_LATCH_4_LSB (1U << 0) /* 32b */ 2601 2602 /* PCM_WDT_LATCH_5 (0x10006000 + 0x814) */ 2603 #define PCM_WDT_LATCH_5_LSB (1U << 0) /* 32b */ 2604 2605 /* PCM_WDT_LATCH_6 (0x10006000 + 0x818) */ 2606 #define PCM_WDT_LATCH_6_LSB (1U << 0) /* 32b */ 2607 2608 /* PCM_WDT_LATCH_7 (0x10006000 + 0x81C) */ 2609 #define PCM_WDT_LATCH_7_LSB (1U << 0) /* 32b */ 2610 2611 /* PCM_WDT_LATCH_8 (0x10006000 + 0x820) */ 2612 #define PCM_WDT_LATCH_8_LSB (1U << 0) /* 32b */ 2613 2614 /* PCM_WDT_LATCH_9 (0x10006000 + 0x824) */ 2615 #define PCM_WDT_LATCH_9_LSB (1U << 0) /* 32b */ 2616 2617 /* PCM_WDT_LATCH_10 (0x10006000 + 0x828) */ 2618 #define PCM_WDT_LATCH_10_LSB (1U << 0) /* 32b */ 2619 2620 /* PCM_WDT_LATCH_11 (0x10006000 + 0x82C) */ 2621 #define PCM_WDT_LATCH_11_LSB (1U << 0) /* 32b */ 2622 2623 /* PCM_WDT_LATCH_12 (0x10006000 + 0x830) */ 2624 #define PCM_WDT_LATCH_12_LSB (1U << 0) /* 32b */ 2625 2626 /* PCM_WDT_LATCH_13 (0x10006000 + 0x834) */ 2627 #define PCM_WDT_LATCH_13_LSB (1U << 0) /* 32b */ 2628 2629 /* PCM_WDT_LATCH_14 (0x10006000 + 0x838) */ 2630 #define PCM_WDT_LATCH_14_LSB (1U << 0) /* 32b */ 2631 2632 /* PCM_WDT_LATCH_15 (0x10006000 + 0x83C) */ 2633 #define PCM_WDT_LATCH_15_LSB (1U << 0) /* 32b */ 2634 2635 /* PCM_WDT_LATCH_16 (0x10006000 + 0x840) */ 2636 #define PCM_WDT_LATCH_16_LSB (1U << 0) /* 32b */ 2637 2638 /* PCM_WDT_LATCH_17 (0x10006000 + 0x844) */ 2639 #define PCM_WDT_LATCH_17_LSB (1U << 0) /* 32b */ 2640 2641 /* PCM_WDT_LATCH_18 (0x10006000 + 0x848) */ 2642 #define PCM_WDT_LATCH_18_LSB (1U << 0) /* 32b */ 2643 2644 /* PCM_WDT_LATCH_SPARE_0 (0x10006000 + 0x84C) */ 2645 #define PCM_WDT_LATCH_SPARE_0_LSB (1U << 0) /* 32b */ 2646 2647 /* PCM_WDT_LATCH_SPARE_1 (0x10006000 + 0x850) */ 2648 #define PCM_WDT_LATCH_SPARE_1_LSB (1U << 0) /* 32b */ 2649 2650 /* PCM_WDT_LATCH_SPARE_2 (0x10006000 + 0x854) */ 2651 #define PCM_WDT_LATCH_SPARE_2_LSB (1U << 0) /* 32b */ 2652 2653 /* PCM_WDT_LATCH_CONN_0 (0x10006000 + 0x870) */ 2654 #define PCM_WDT_LATCH_CONN_0_LSB (1U << 0) /* 32b */ 2655 2656 /* PCM_WDT_LATCH_CONN_1 (0x10006000 + 0x874) */ 2657 #define PCM_WDT_LATCH_CONN_1_LSB (1U << 0) /* 32b */ 2658 2659 /* PCM_WDT_LATCH_CONN_2 (0x10006000 + 0x878) */ 2660 #define PCM_WDT_LATCH_CONN_2_LSB (1U << 0) /* 32b */ 2661 2662 /* DRAMC_GATING_ERR_LATCH_CH0_0 (0x10006000 + 0x8A0) */ 2663 #define DRAMC_GATING_ERR_LATCH_CH0_0_LSB (1U << 0) /* 32b */ 2664 2665 /* DRAMC_GATING_ERR_LATCH_CH0_1 (0x10006000 + 0x8A4) */ 2666 #define DRAMC_GATING_ERR_LATCH_CH0_1_LSB (1U << 0) /* 32b */ 2667 2668 /* DRAMC_GATING_ERR_LATCH_CH0_2 (0x10006000 + 0x8A8) */ 2669 #define DRAMC_GATING_ERR_LATCH_CH0_2_LSB (1U << 0) /* 32b */ 2670 2671 /* DRAMC_GATING_ERR_LATCH_CH0_3 (0x10006000 + 0x8AC) */ 2672 #define DRAMC_GATING_ERR_LATCH_CH0_3_LSB (1U << 0) /* 32b */ 2673 2674 /* DRAMC_GATING_ERR_LATCH_CH0_4 (0x10006000 + 0x8B0) */ 2675 #define DRAMC_GATING_ERR_LATCH_CH0_4_LSB (1U << 0) /* 32b */ 2676 2677 /* DRAMC_GATING_ERR_LATCH_CH0_5 (0x10006000 + 0x8B4) */ 2678 #define DRAMC_GATING_ERR_LATCH_CH0_5_LSB (1U << 0) /* 32b */ 2679 2680 /* DRAMC_GATING_ERR_LATCH_CH0_6 (0x10006000 + 0x8B8) */ 2681 #define DRAMC_GATING_ERR_LATCH_CH0_6_LSB (1U << 0) /* 32b */ 2682 2683 /* DRAMC_GATING_ERR_LATCH_SPARE_0 (0x10006000 + 0x8F4) */ 2684 #define DRAMC_GATING_ERR_LATCH_SPARE_0_LSB (1U << 0) /* 32b */ 2685 2686 /* SPM_ACK_CHK_CON_0 (0x10006000 + 0x900) */ 2687 #define SPM_ACK_CHK_SW_EN_0_LSB (1U << 0) /* 1b */ 2688 #define SPM_ACK_CHK_CLR_ALL_0_LSB (1U << 1) /* 1b */ 2689 #define SPM_ACK_CHK_CLR_TIMER_0_LSB (1U << 2) /* 1b */ 2690 #define SPM_ACK_CHK_CLR_IRQ_0_LSB (1U << 3) /* 1b */ 2691 #define SPM_ACK_CHK_STA_EN_0_LSB (1U << 4) /* 1b */ 2692 #define SPM_ACK_CHK_WAKEUP_EN_0_LSB (1U << 5) /* 1b */ 2693 #define SPM_ACK_CHK_WDT_EN_0_LSB (1U << 6) /* 1b */ 2694 #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_0_LSB (1U << 7) /* 1b */ 2695 #define SPM_ACK_CHK_HW_EN_0_LSB (1U << 8) /* 1b */ 2696 #define SPM_ACK_CHK_HW_MODE_0_LSB (1U << 9) /* 3b */ 2697 #define SPM_ACK_CHK_FAIL_0_LSB (1U << 15) /* 1b */ 2698 2699 /* SPM_ACK_CHK_PC_0 (0x10006000 + 0x904) */ 2700 #define SPM_ACK_CHK_HW_TRIG_PC_VAL_0_LSB (1U << 0) /* 16b */ 2701 #define SPM_ACK_CHK_HW_TARG_PC_VAL_0_LSB (1U << 16) /* 16b */ 2702 2703 /* SPM_ACK_CHK_SEL_0 (0x10006000 + 0x908) */ 2704 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_0_LSB (1U << 0) /* 5b */ 2705 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_0_LSB (1U << 5) /* 3b */ 2706 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_0_LSB (1U << 16) /* 5b */ 2707 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_0_LSB (1U << 21) /* 3b */ 2708 2709 /* SPM_ACK_CHK_TIMER_0 (0x10006000 + 0x90C) */ 2710 #define SPM_ACK_CHK_TIMER_VAL_0_LSB (1U << 0) /* 16b */ 2711 #define SPM_ACK_CHK_TIMER_0_LSB (1U << 16) /* 16b */ 2712 2713 /* SPM_ACK_CHK_STA_0 (0x10006000 + 0x910) */ 2714 #define SPM_ACK_CHK_STA_0_LSB (1U << 0) /* 32b */ 2715 2716 /* SPM_ACK_CHK_SWINT_0 (0x10006000 + 0x914) */ 2717 #define SPM_ACK_CHK_SWINT_EN_0_LSB (1U << 0) /* 32b */ 2718 2719 /* SPM_ACK_CHK_CON_1 (0x10006000 + 0x918) */ 2720 #define SPM_ACK_CHK_SW_EN_1_LSB (1U << 0) /* 1b */ 2721 #define SPM_ACK_CHK_CLR_ALL_1_LSB (1U << 1) /* 1b */ 2722 #define SPM_ACK_CHK_CLR_TIMER_1_LSB (1U << 2) /* 1b */ 2723 #define SPM_ACK_CHK_CLR_IRQ_1_LSB (1U << 3) /* 1b */ 2724 #define SPM_ACK_CHK_STA_EN_1_LSB (1U << 4) /* 1b */ 2725 #define SPM_ACK_CHK_WAKEUP_EN_1_LSB (1U << 5) /* 1b */ 2726 #define SPM_ACK_CHK_WDT_EN_1_LSB (1U << 6) /* 1b */ 2727 #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_1_LSB (1U << 7) /* 1b */ 2728 #define SPM_ACK_CHK_HW_EN_1_LSB (1U << 8) /* 1b */ 2729 #define SPM_ACK_CHK_HW_MODE_1_LSB (1U << 9) /* 3b */ 2730 #define SPM_ACK_CHK_FAIL_1_LSB (1U << 15) /* 1b */ 2731 2732 /* SPM_ACK_CHK_PC_1 (0x10006000 + 0x91C) */ 2733 #define SPM_ACK_CHK_HW_TRIG_PC_VAL_1_LSB (1U << 0) /* 16b */ 2734 #define SPM_ACK_CHK_HW_TARG_PC_VAL_1_LSB (1U << 16) /* 16b */ 2735 2736 /* SPM_ACK_CHK_SEL_1 (0x10006000 + 0x920) */ 2737 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_1_LSB (1U << 0) /* 5b */ 2738 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_1_LSB (1U << 5) /* 3b */ 2739 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_1_LSB (1U << 16) /* 5b */ 2740 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_1_LSB (1U << 21) /* 3b */ 2741 2742 /* SPM_ACK_CHK_TIMER_1 (0x10006000 + 0x924) */ 2743 #define SPM_ACK_CHK_TIMER_VAL_1_LSB (1U << 0) /* 16b */ 2744 #define SPM_ACK_CHK_TIMER_1_LSB (1U << 16) /* 16b */ 2745 2746 /* SPM_ACK_CHK_STA_1 (0x10006000 + 0x928) */ 2747 #define SPM_ACK_CHK_STA_1_LSB (1U << 0) /* 32b */ 2748 2749 /* SPM_ACK_CHK_SWINT_1 (0x10006000 + 0x92C) */ 2750 #define SPM_ACK_CHK_SWINT_EN_1_LSB (1U << 0) /* 32b */ 2751 2752 /* SPM_ACK_CHK_CON_2 (0x10006000 + 0x930) */ 2753 #define SPM_ACK_CHK_SW_EN_2_LSB (1U << 0) /* 1b */ 2754 #define SPM_ACK_CHK_CLR_ALL_2_LSB (1U << 1) /* 1b */ 2755 #define SPM_ACK_CHK_CLR_TIMER_2_LSB (1U << 2) /* 1b */ 2756 #define SPM_ACK_CHK_CLR_IRQ_2_LSB (1U << 3) /* 1b */ 2757 #define SPM_ACK_CHK_STA_EN_2_LSB (1U << 4) /* 1b */ 2758 #define SPM_ACK_CHK_WAKEUP_EN_2_LSB (1U << 5) /* 1b */ 2759 #define SPM_ACK_CHK_WDT_EN_2_LSB (1U << 6) /* 1b */ 2760 #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_2_LSB (1U << 7) /* 1b */ 2761 #define SPM_ACK_CHK_HW_EN_2_LSB (1U << 8) /* 1b */ 2762 #define SPM_ACK_CHK_HW_MODE_2_LSB (1U << 9) /* 3b */ 2763 #define SPM_ACK_CHK_FAIL_2_LSB (1U << 15) /* 1b */ 2764 2765 /* SPM_ACK_CHK_PC_2 (0x10006000 + 0x934) */ 2766 #define SPM_ACK_CHK_HW_TRIG_PC_VAL_2_LSB (1U << 0) /* 16b */ 2767 #define SPM_ACK_CHK_HW_TARG_PC_VAL_2_LSB (1U << 16) /* 16b */ 2768 2769 /* SPM_ACK_CHK_SEL_2 (0x10006000 + 0x938) */ 2770 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_2_LSB (1U << 0) /* 5b */ 2771 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_2_LSB (1U << 5) /* 3b */ 2772 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_2_LSB (1U << 16) /* 5b */ 2773 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_2_LSB (1U << 21) /* 3b */ 2774 2775 /* SPM_ACK_CHK_TIMER_2 (0x10006000 + 0x93C) */ 2776 #define SPM_ACK_CHK_TIMER_VAL_2_LSB (1U << 0) /* 16b */ 2777 #define SPM_ACK_CHK_TIMER_2_LSB (1U << 16) /* 16b */ 2778 2779 /* SPM_ACK_CHK_STA_2 (0x10006000 + 0x940) */ 2780 #define SPM_ACK_CHK_STA_2_LSB (1U << 0) /* 32b */ 2781 2782 /* SPM_ACK_CHK_SWINT_2 (0x10006000 + 0x944) */ 2783 #define SPM_ACK_CHK_SWINT_EN_2_LSB (1U << 0) /* 32b */ 2784 2785 /* SPM_ACK_CHK_CON_3 (0x10006000 + 0x948) */ 2786 #define SPM_ACK_CHK_SW_EN_3_LSB (1U << 0) /* 1b */ 2787 #define SPM_ACK_CHK_CLR_ALL_3_LSB (1U << 1) /* 1b */ 2788 #define SPM_ACK_CHK_CLR_TIMER_3_LSB (1U << 2) /* 1b */ 2789 #define SPM_ACK_CHK_CLR_IRQ_3_LSB (1U << 3) /* 1b */ 2790 #define SPM_ACK_CHK_STA_EN_3_LSB (1U << 4) /* 1b */ 2791 #define SPM_ACK_CHK_WAKEUP_EN_3_LSB (1U << 5) /* 1b */ 2792 #define SPM_ACK_CHK_WDT_EN_3_LSB (1U << 6) /* 1b */ 2793 #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_3_LSB (1U << 7) /* 1b */ 2794 #define SPM_ACK_CHK_HW_EN_3_LSB (1U << 8) /* 1b */ 2795 #define SPM_ACK_CHK_HW_MODE_3_LSB (1U << 9) /* 3b */ 2796 #define SPM_ACK_CHK_FAIL_3_LSB (1U << 15) /* 1b */ 2797 2798 /* SPM_ACK_CHK_PC_3 (0x10006000 + 0x94C) */ 2799 #define SPM_ACK_CHK_HW_TRIG_PC_VAL_3_LSB (1U << 0) /* 16b */ 2800 #define SPM_ACK_CHK_HW_TARG_PC_VAL_3_LSB (1U << 16) /* 16b */ 2801 2802 /* SPM_ACK_CHK_SEL_3 (0x10006000 + 0x950) */ 2803 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_3_LSB (1U << 0) /* 5b */ 2804 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_3_LSB (1U << 5) /* 3b */ 2805 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_3_LSB (1U << 16) /* 5b */ 2806 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_3_LSB (1U << 21) /* 3b */ 2807 2808 /* SPM_ACK_CHK_TIMER_3 (0x10006000 + 0x954) */ 2809 #define SPM_ACK_CHK_TIMER_VAL_3_LSB (1U << 0) /* 16b */ 2810 #define SPM_ACK_CHK_TIMER_3_LSB (1U << 16) /* 16b */ 2811 2812 /* SPM_ACK_CHK_STA_3 (0x10006000 + 0x958) */ 2813 #define SPM_ACK_CHK_STA_3_LSB (1U << 0) /* 32b */ 2814 2815 /* SPM_ACK_CHK_SWINT_3 (0x10006000 + 0x95C) */ 2816 #define SPM_ACK_CHK_SWINT_EN_3_LSB (1U << 0) /* 32b */ 2817 2818 /* SPM_COUNTER_0 (0x10006000 + 0x960) */ 2819 #define SPM_COUNTER_VAL_0_LSB (1U << 0) /* 14b */ 2820 #define SPM_COUNTER_OUT_0_LSB (1U << 14) /* 14b */ 2821 #define SPM_COUNTER_EN_0_LSB (1U << 28) /* 1b */ 2822 #define SPM_COUNTER_CLR_0_LSB (1U << 29) /* 1b */ 2823 #define SPM_COUNTER_TIMEOUT_0_LSB (1U << 30) /* 1b */ 2824 #define SPM_COUNTER_WAKEUP_EN_0_LSB (1U << 31) /* 1b */ 2825 2826 /* SPM_COUNTER_1 (0x10006000 + 0x964) */ 2827 #define SPM_COUNTER_VAL_1_LSB (1U << 0) /* 14b */ 2828 #define SPM_COUNTER_OUT_1_LSB (1U << 14) /* 14b */ 2829 #define SPM_COUNTER_EN_1_LSB (1U << 28) /* 1b */ 2830 #define SPM_COUNTER_CLR_1_LSB (1U << 29) /* 1b */ 2831 #define SPM_COUNTER_TIMEOUT_1_LSB (1U << 30) /* 1b */ 2832 #define SPM_COUNTER_WAKEUP_EN_1_LSB (1U << 31) /* 1b */ 2833 2834 /* SPM_COUNTER_2 (0x10006000 + 0x968) */ 2835 #define SPM_COUNTER_VAL_2_LSB (1U << 0) /* 14b */ 2836 #define SPM_COUNTER_OUT_2_LSB (1U << 14) /* 14b */ 2837 #define SPM_COUNTER_EN_2_LSB (1U << 28) /* 1b */ 2838 #define SPM_COUNTER_CLR_2_LSB (1U << 29) /* 1b */ 2839 #define SPM_COUNTER_TIMEOUT_2_LSB (1U << 30) /* 1b */ 2840 #define SPM_COUNTER_WAKEUP_EN_2_LSB (1U << 31) /* 1b */ 2841 2842 /* SYS_TIMER_CON (0x10006000 + 0x96C) */ 2843 #define SYS_TIMER_START_EN_LSB (1U << 0) /* 1b */ 2844 #define SYS_TIMER_LATCH_EN_LSB (1U << 1) /* 1b */ 2845 #define SYS_TIMER_ID_LSB (1U << 8) /* 8b */ 2846 #define SYS_TIMER_VALID_LSB (1U << 31) /* 1b */ 2847 2848 /* SPM_TWAM_CON (0x10006000 + 0x970) */ 2849 #define REG_TWAM_ENABLE_LSB (1U << 0) /* 1b */ 2850 #define REG_TWAM_SPEED_MODE_EN_LSB (1U << 1) /* 1b */ 2851 #define REG_TWAM_SW_RST_LSB (1U << 2) /* 1b */ 2852 #define REG_TWAM_IRQ_MASK_LSB (1U << 3) /* 1b */ 2853 #define REG_TWAM_MON_TYPE_0_LSB (1U << 4) /* 2b */ 2854 #define REG_TWAM_MON_TYPE_1_LSB (1U << 6) /* 2b */ 2855 #define REG_TWAM_MON_TYPE_2_LSB (1U << 8) /* 2b */ 2856 #define REG_TWAM_MON_TYPE_3_LSB (1U << 10) /* 2b */ 2857 2858 /* SPM_TWAM_WINDOW_LEN (0x10006000 + 0x974) */ 2859 #define REG_TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */ 2860 2861 /* SPM_TWAM_IDLE_SEL (0x10006000 + 0x978) */ 2862 #define REG_TWAM_SIG_SEL_0_LSB (1U << 0) /* 7b */ 2863 #define REG_TWAM_SIG_SEL_1_LSB (1U << 8) /* 7b */ 2864 #define REG_TWAM_SIG_SEL_2_LSB (1U << 16) /* 7b */ 2865 #define REG_TWAM_SIG_SEL_3_LSB (1U << 24) /* 7b */ 2866 2867 /* SPM_TWAM_EVENT_CLEAR (0x10006000 + 0x97C) */ 2868 #define SPM_TWAM_EVENT_CLEAR_LSB (1U << 0) /* 1b */ 2869 2870 /* OPP0_TABLE (0x10006000 + 0x980) */ 2871 #define OPP0_TABLE_LSB (1U << 0) /* 32b */ 2872 2873 /* OPP1_TABLE (0x10006000 + 0x984) */ 2874 #define OPP1_TABLE_LSB (1U << 0) /* 32b */ 2875 2876 /* OPP2_TABLE (0x10006000 + 0x988) */ 2877 #define OPP2_TABLE_LSB (1U << 0) /* 32b */ 2878 2879 /* OPP3_TABLE (0x10006000 + 0x98C) */ 2880 #define OPP3_TABLE_LSB (1U << 0) /* 32b */ 2881 2882 /* OPP4_TABLE (0x10006000 + 0x990) */ 2883 #define OPP4_TABLE_LSB (1U << 0) /* 32b */ 2884 2885 /* OPP5_TABLE (0x10006000 + 0x994) */ 2886 #define OPP5_TABLE_LSB (1U << 0) /* 32b */ 2887 2888 /* OPP6_TABLE (0x10006000 + 0x998) */ 2889 #define OPP6_TABLE_LSB (1U << 0) /* 32b */ 2890 2891 /* OPP7_TABLE (0x10006000 + 0x99C) */ 2892 #define OPP7_TABLE_LSB (1U << 0) /* 32b */ 2893 2894 /* OPP8_TABLE (0x10006000 + 0x9A0) */ 2895 #define OPP8_TABLE_LSB (1U << 0) /* 32b */ 2896 2897 /* OPP9_TABLE (0x10006000 + 0x9A4) */ 2898 #define OPP9_TABLE_LSB (1U << 0) /* 32b */ 2899 2900 /* OPP10_TABLE (0x10006000 + 0x9A8) */ 2901 #define OPP10_TABLE_LSB (1U << 0) /* 32b */ 2902 2903 /* OPP11_TABLE (0x10006000 + 0x9AC) */ 2904 #define OPP11_TABLE_LSB (1U << 0) /* 32b */ 2905 2906 /* OPP12_TABLE (0x10006000 + 0x9B0) */ 2907 #define OPP12_TABLE_LSB (1U << 0) /* 32b */ 2908 2909 /* OPP13_TABLE (0x10006000 + 0x9B4) */ 2910 #define OPP13_TABLE_LSB (1U << 0) /* 32b */ 2911 2912 /* OPP14_TABLE (0x10006000 + 0x9B8) */ 2913 #define OPP14_TABLE_LSB (1U << 0) /* 32b */ 2914 2915 /* OPP15_TABLE (0x10006000 + 0x9BC) */ 2916 #define OPP15_TABLE_LSB (1U << 0) /* 32b */ 2917 2918 /* OPP16_TABLE (0x10006000 + 0x9C0) */ 2919 #define OPP16_TABLE_LSB (1U << 0) /* 32b */ 2920 2921 /* OPP17_TABLE (0x10006000 + 0x9C4) */ 2922 #define OPP17_TABLE_LSB (1U << 0) /* 32b */ 2923 2924 /* SHU0_ARRAY (0x10006000 + 0x9C8) */ 2925 #define SHU0_ARRAY_LSB (1U << 0) /* 32b */ 2926 2927 /* SHU1_ARRAY (0x10006000 + 0x9CC) */ 2928 #define SHU1_ARRAY_LSB (1U << 0) /* 32b */ 2929 2930 /* SHU2_ARRAY (0x10006000 + 0x9D0) */ 2931 #define SHU2_ARRAY_LSB (1U << 0) /* 32b */ 2932 2933 /* SHU3_ARRAY (0x10006000 + 0x9D4) */ 2934 #define SHU3_ARRAY_LSB (1U << 0) /* 32b */ 2935 2936 /* SHU4_ARRAY (0x10006000 + 0x9D8) */ 2937 #define SHU4_ARRAY_LSB (1U << 0) /* 32b */ 2938 2939 /* SHU5_ARRAY (0x10006000 + 0x9DC) */ 2940 #define SHU5_ARRAY_LSB (1U << 0) /* 32b */ 2941 2942 /* SHU6_ARRAY (0x10006000 + 0x9E0) */ 2943 #define SHU6_ARRAY_LSB (1U << 0) /* 32b */ 2944 2945 /* SHU7_ARRAY (0x10006000 + 0x9E4) */ 2946 #define SHU7_ARRAY_LSB (1U << 0) /* 32b */ 2947 2948 /* SHU8_ARRAY (0x10006000 + 0x9E8) */ 2949 #define SHU8_ARRAY_LSB (1U << 0) /* 32b */ 2950 2951 /* SHU9_ARRAY (0x10006000 + 0x9EC) */ 2952 #define SHU9_ARRAY_LSB (1U << 0) /* 32b */ 2953 2954 #define SPM_PROJECT_CODE (0xb16) 2955 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) 2956 2957 #endif /* MT_SPM_REG */ 2958
