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Searched refs:PLAT_MAX_RET_STATE (Results 1 – 25 of 83) sorted by relevance

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/trusted-firmware-a-3.6.0-3.5.0/plat/nxp/common/psci/
Dplat_psci.c151 if (cpu_state == PLAT_MAX_RET_STATE) { in _pwr_cpu_standby()
184 == PLAT_MAX_RET_STATE) { in _pwr_suspend()
206 PLAT_MAX_RET_STATE) { in _pwr_suspend()
227 else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_RET_STATE) { in _pwr_suspend()
259 == PLAT_MAX_RET_STATE) { in _pwr_suspend_finish()
285 PLAT_MAX_RET_STATE) { in _pwr_suspend_finish()
309 else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_RET_STATE) { in _pwr_suspend_finish()
352 PLAT_MAX_RET_STATE; in _pwr_state_validate()
360 PLAT_MAX_RET_STATE; in _pwr_state_validate()
368 PLAT_MAX_RET_STATE; in _pwr_state_validate()
[all …]
/trusted-firmware-a-3.6.0-3.5.0/plat/nxp/soc-ls1028a/include/
Dsoc.h128 #define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1) macro
129 #define LS_LOCAL_STATE_RET PLAT_MAX_RET_STATE
132 #define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
/trusted-firmware-a-3.6.0-3.5.0/plat/xilinx/versal/
Dplat_psci.c64 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_pwr_domain_suspend()
68 state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ? in versal_pwr_domain_suspend()
76 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_pwr_domain_suspend()
106 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_pwr_domain_suspend_finish()
202 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in versal_validate_power_state()
/trusted-firmware-a-3.6.0-3.5.0/plat/imx/imx8m/imx8mq/
Dimx8mq_psci.c32 CORE_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; in imx_validate_power_state()
33 CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; in imx_validate_power_state()
38 CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; in imx_validate_power_state()
128 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE; in imx_get_sys_suspend_power_state()
/trusted-firmware-a-3.6.0-3.5.0/plat/imx/common/
Dimx8_psci.c45 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_RET_STATE; in imx_validate_power_state()
60 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE; in imx_get_sys_suspend_power_state()
/trusted-firmware-a-3.6.0-3.5.0/plat/nxp/soc-ls1046a/include/
Dsoc.h98 #define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1) macro
101 #define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
/trusted-firmware-a-3.6.0-3.5.0/plat/nxp/soc-ls1088a/include/
Dsoc.h210 #define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1) macro
211 #define LS_LOCAL_STATE_RET PLAT_MAX_RET_STATE
214 #define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
/trusted-firmware-a-3.6.0-3.5.0/plat/nxp/soc-ls1043a/include/
Dsoc.h206 #define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1) macro
207 #define LS_LOCAL_STATE_RET PLAT_MAX_RET_STATE
210 #define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
/trusted-firmware-a-3.6.0-3.5.0/plat/xilinx/zynqmp/
Dplat_psci.c96 state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ? in zynqmp_pwr_domain_suspend()
103 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in zynqmp_pwr_domain_suspend()
135 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in zynqmp_pwr_domain_suspend_finish()
186 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in zynqmp_validate_power_state()
/trusted-firmware-a-3.6.0-3.5.0/plat/xilinx/versal_net/
Dplat_psci_pm.c116 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_net_pwr_domain_suspend()
120 state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ? in versal_net_pwr_domain_suspend()
162 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_net_pwr_domain_suspend_finish()
204 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in versal_net_validate_power_state()
/trusted-firmware-a-3.6.0-3.5.0/plat/nxp/soc-lx2160a/include/
Dsoc.h129 #define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1) macro
132 #define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
/trusted-firmware-a-3.6.0-3.5.0/plat/mediatek/include/armv8_2/
Darch_def.h12 #define PLAT_MAX_RET_STATE (1) macro
/trusted-firmware-a-3.6.0-3.5.0/plat/mediatek/mt8186/include/
Dplat_pm.h116 #define PLAT_MT_CPU_SUSPEND_CLUSTER PLAT_MAX_RET_STATE
119 #define IS_PLAT_SYSTEM_RETENTION(aff) (aff >= PLAT_MAX_RET_STATE)
/trusted-firmware-a-3.6.0-3.5.0/plat/mediatek/lib/pm/
Dmtk_pm.h208 #define PLAT_MT_CPU_SUSPEND_CLUSTER PLAT_MAX_RET_STATE
209 #define PLAT_MT_CPU_SUSPEND_MCUSYS PLAT_MAX_RET_STATE
212 #define IS_PLAT_SYSTEM_RETENTION(aff) (aff >= PLAT_MAX_RET_STATE)
/trusted-firmware-a-3.6.0-3.5.0/plat/qti/msm8916/include/
Dplatform_def.h37 #define PLAT_MAX_RET_STATE U(2) macro
/trusted-firmware-a-3.6.0-3.5.0/plat/hisilicon/hikey/include/
Dplatform_def.h39 #define PLAT_MAX_RET_STATE U(1) macro
/trusted-firmware-a-3.6.0-3.5.0/plat/amlogic/gxl/include/
Dplatform_def.h31 #define PLAT_MAX_RET_STATE U(1) macro
/trusted-firmware-a-3.6.0-3.5.0/plat/amlogic/g12a/include/
Dplatform_def.h31 #define PLAT_MAX_RET_STATE U(1) macro
/trusted-firmware-a-3.6.0-3.5.0/plat/amlogic/gxbb/include/
Dplatform_def.h34 #define PLAT_MAX_RET_STATE U(1) macro
/trusted-firmware-a-3.6.0-3.5.0/plat/imx/imx8m/imx8mq/include/
Dplatform_def.h30 #define PLAT_MAX_RET_STATE U(1) macro
32 #define PLAT_WAIT_RET_STATE PLAT_MAX_RET_STATE
/trusted-firmware-a-3.6.0-3.5.0/plat/amlogic/axg/include/
Dplatform_def.h31 #define PLAT_MAX_RET_STATE U(1) macro
/trusted-firmware-a-3.6.0-3.5.0/plat/rockchip/rk3288/include/
Dplatform_def.h56 #define PLAT_MAX_RET_STATE U(1) macro
/trusted-firmware-a-3.6.0-3.5.0/plat/imx/imx8qx/include/
Dplatform_def.h28 #define PLAT_MAX_RET_STATE U(1) macro
/trusted-firmware-a-3.6.0-3.5.0/plat/imx/imx8qm/include/
Dplatform_def.h33 #define PLAT_MAX_RET_STATE U(1) macro
/trusted-firmware-a-3.6.0-3.5.0/plat/socionext/uniphier/include/
Dplatform_def.h29 #define PLAT_MAX_RET_STATE U(1) macro

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