Searched refs:PLAT_CORE_LVL (Results 1 – 2 of 2) sorted by relevance
216 else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_OFF_STATE) { in _pwr_suspend()227 else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_RET_STATE) { in _pwr_suspend()297 else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_OFF_STATE) { in _pwr_suspend_finish()309 else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_RET_STATE) { in _pwr_suspend_finish()374 state->pwr_domain_state[PLAT_CORE_LVL] = in _pwr_state_validate()377 state->pwr_domain_state[PLAT_CORE_LVL] = in _pwr_state_validate()398 req_state->pwr_domain_state[PLAT_CORE_LVL] = PLAT_MAX_OFF_STATE; in _pwr_state_sys_suspend()
19 #define PLAT_CORE_LVL PSCI_CPU_PWR_LVL macro
