Searched refs:MPIDR_AFFLVL1 (Results 1 – 25 of 52) sorted by relevance
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45 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_RET_STATE; in imx_validate_power_state()47 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_OFF_STATE; in imx_validate_power_state()
24 ((state)->pwr_domain_state[MPIDR_AFFLVL1])231 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_off()267 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_suspend()288 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_on_finish()332 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_suspend_finish()
65 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; in tegra_soc_validate_power_state()112 if (lvl == MPIDR_AFFLVL1) in tegra_soc_get_target_pwr_state()117 if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_IDLE)) { in tegra_soc_get_target_pwr_state()175 } else if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) && in tegra_soc_get_target_pwr_state()200 unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1]; in tegra_soc_pwr_domain_suspend()507 if (target_state->pwr_domain_state[MPIDR_AFFLVL1] == in tegra_soc_pwr_domain_on_finish()
11 #define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1])
45 MPIDR_AFFLVL1]); in mss_pm_ipc_msg_send()
27 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
30 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
27 #define IMX_PWR_LVL1 MPIDR_AFFLVL1
32 #define QTI_PWR_LVL1 MPIDR_AFFLVL1
66 if (target_state->pwr_domain_state[MPIDR_AFFLVL1] == in brcm_pwr_domain_on_finish()
29 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
178 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
36 #define MARVELL_PWR_LVL1 MPIDR_AFFLVL1
26 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
28 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
33 #define MARVELL_PWR_LVL1 MPIDR_AFFLVL1
127 if (is_local_state_off(target_state->pwr_domain_state[MPIDR_AFFLVL1])) in imx_domain_suspend()203 if (is_local_state_off(target_state->pwr_domain_state[MPIDR_AFFLVL1])) in imx_domain_suspend_finish()
169 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
332 bool afflvl1 = (pds[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF); in plat_mtk_power_domain_off()351 bool afflvl1 = (pds[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF); in plat_mtk_power_domain_on_finish()367 bool afflvl1 = (pds[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF); in plat_mtk_power_domain_suspend()
133 #define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL1)
128 if (target_state->pwr_domain_state[MPIDR_AFFLVL1] == in axg_pwr_domain_off()
24 #define IMX_PWR_LVL1 MPIDR_AFFLVL1
55 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1
