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Searched refs:MAP_REGION_FLAT (Results 1 – 25 of 106) sorted by relevance

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/trusted-firmware-a-3.6.0-3.5.0/plat/rockchip/rk3328/drivers/soc/
Dsoc.c22 MAP_REGION_FLAT(UART0_BASE, UART0_SIZE,
24 MAP_REGION_FLAT(UART1_BASE, UART1_SIZE,
26 MAP_REGION_FLAT(UART2_BASE, UART2_SIZE,
28 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE,
30 MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE,
32 MAP_REGION_FLAT(GPIO0_BASE, GPIO0_SIZE,
34 MAP_REGION_FLAT(GPIO1_BASE, GPIO1_SIZE,
36 MAP_REGION_FLAT(GPIO2_BASE, GPIO2_SIZE,
38 MAP_REGION_FLAT(GPIO3_BASE, GPIO3_SIZE,
40 MAP_REGION_FLAT(CRU_BASE, CRU_SIZE,
[all …]
/trusted-firmware-a-3.6.0-3.5.0/include/plat/brcm/common/
Dbrcm_def.h55 #define BRCM_MAP_SHARED_RAM MAP_REGION_FLAT( \
60 #define BRCM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
66 #define BRCM_MAP_NS_SHARED_DRAM MAP_REGION_FLAT( \
73 #define BRCM_MAP_EXT_SRAM MAP_REGION_FLAT( \
79 #define BRCM_MAP_NAND_RO MAP_REGION_FLAT(NAND_BASE_ADDR,\
83 #define BRCM_MAP_QSPI_RO MAP_REGION_FLAT(QSPI_BASE_ADDR,\
87 #define HSLS_REGION MAP_REGION_FLAT(HSLS_BASE_ADDR, \
91 #define CCN_REGION MAP_REGION_FLAT(PLAT_BRCM_CCN_BASE, \
95 #define GIC500_REGION MAP_REGION_FLAT(GIC500_BASE, \
99 #define PERIPH0_REGION MAP_REGION_FLAT(PERIPH0_BASE, \
[all …]
/trusted-firmware-a-3.6.0-3.5.0/plat/amlogic/g12a/
Dg12a_common.c19 #define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \
23 #define MAP_NS_SHARE_MEM MAP_REGION_FLAT(AML_NS_SHARE_MEM_BASE, \
27 #define MAP_SEC_SHARE_MEM MAP_REGION_FLAT(AML_SEC_SHARE_MEM_BASE, \
31 #define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \
35 #define MAP_HDCP_RX MAP_REGION_FLAT(AML_HDCP_RX_BASE, \
39 #define MAP_HDCP_TX MAP_REGION_FLAT(AML_HDCP_TX_BASE, \
43 #define MAP_GIC_DEVICE MAP_REGION_FLAT(AML_GIC_DEVICE_BASE, \
47 #define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \
51 #define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \
55 #define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \
[all …]
/trusted-firmware-a-3.6.0-3.5.0/plat/amlogic/axg/
Daxg_common.c19 #define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \
23 #define MAP_NS_SHARE_MEM MAP_REGION_FLAT(AML_NS_SHARE_MEM_BASE, \
27 #define MAP_SEC_SHARE_MEM MAP_REGION_FLAT(AML_SEC_SHARE_MEM_BASE, \
31 #define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \
35 #define MAP_GIC_DEVICE MAP_REGION_FLAT(AML_GIC_DEVICE_BASE, \
39 #define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \
43 #define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \
47 #define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \
66 #define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \
70 #define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \
[all …]
/trusted-firmware-a-3.6.0-3.5.0/plat/amlogic/gxbb/
Dgxbb_common.c19 #define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \
23 #define MAP_NSDRAM1 MAP_REGION_FLAT(AML_NSDRAM1_BASE, \
27 #define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \
31 #define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \
35 #define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \
39 #define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \
43 #define MAP_SEC_DEVICE3 MAP_REGION_FLAT(AML_SEC_DEVICE3_BASE, \
61 #define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \
65 #define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \
69 #define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \
[all …]
/trusted-firmware-a-3.6.0-3.5.0/plat/amlogic/gxl/
Dgxl_common.c19 #define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \
23 #define MAP_NSDRAM1 MAP_REGION_FLAT(AML_NSDRAM1_BASE, \
27 #define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \
31 #define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \
35 #define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \
39 #define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \
43 #define MAP_SEC_DEVICE3 MAP_REGION_FLAT(AML_SEC_DEVICE3_BASE, \
61 #define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \
65 #define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \
69 #define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \
[all …]
/trusted-firmware-a-3.6.0-3.5.0/plat/mediatek/mt8195/aarch64/
Dplatform_common.c14 MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE,
16 MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE,
18 MAP_REGION_FLAT(MTK_MCDI_SRAM_BASE, MTK_MCDI_SRAM_MAP_SIZE,
20 MAP_REGION_FLAT(DP_SEC_BASE, DP_SEC_SIZE,
22 MAP_REGION_FLAT(EDP_SEC_BASE, EDP_SEC_SIZE,
24 MAP_REGION_FLAT(APUSYS_SCTRL_REVISER_BASE, APUSYS_SCTRL_REVISER_SIZE,
26 MAP_REGION_FLAT(APUSYS_APU_S_S_4_BASE, APUSYS_APU_S_S_4_SIZE,
28 MAP_REGION_FLAT(APUSYS_APU_PLL_BASE, APUSYS_APU_PLL_SIZE,
30 MAP_REGION_FLAT(APUSYS_APU_ACC_BASE, APUSYS_APU_ACC_SIZE,
/trusted-firmware-a-3.6.0-3.5.0/plat/nvidia/tegra/soc/t186/
Dplat_setup.c73 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */
75 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */
77 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */
79 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */
81 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/
83 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */
85 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */
87 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */
89 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */
91 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */
[all …]
/trusted-firmware-a-3.6.0-3.5.0/plat/rockchip/rk3288/drivers/soc/
Dsoc.c23 MAP_REGION_FLAT(GIC400_BASE, GIC400_SIZE,
25 MAP_REGION_FLAT(STIME_BASE, STIME_SIZE,
27 MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE,
29 MAP_REGION_FLAT(TZPC_BASE, TZPC_SIZE,
31 MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE,
33 MAP_REGION_FLAT(SRAM_BASE, SRAM_SIZE,
35 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE,
37 MAP_REGION_FLAT(UART0_BASE, UART0_SIZE,
39 MAP_REGION_FLAT(UART1_BASE, UART1_SIZE,
41 MAP_REGION_FLAT(UART2_BASE, UART2_SIZE,
[all …]
/trusted-firmware-a-3.6.0-3.5.0/plat/mediatek/mt8192/aarch64/
Dplatform_common.c16 MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE,
18 MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE,
20 MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE,
22 MAP_REGION_FLAT(MTK_MCDI_SRAM_BASE, MTK_MCDI_SRAM_MAP_SIZE,
24 MAP_REGION_FLAT(APUSYS_SCTRL_REVISER_BASE, APUSYS_SCTRL_REVISER_SIZE,
26 MAP_REGION_FLAT(APUSYS_APU_S_S_4_BASE, APUSYS_APU_S_S_4_SIZE,
28 MAP_REGION_FLAT(APUSYS_APC_AO_WRAPPER_BASE, APUSYS_APC_AO_WRAPPER_SIZE,
30 MAP_REGION_FLAT(APUSYS_NOC_DAPC_AO_BASE, APUSYS_NOC_DAPC_AO_SIZE,
/trusted-firmware-a-3.6.0-3.5.0/plat/intel/soc/stratix10/
Dbl2_plat_setup.c36 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
38 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
40 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE,
42 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
44 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
46 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
48 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE,
95 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, in bl2_el3_plat_arch_setup()
97 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, in bl2_el3_plat_arch_setup()
99 MAP_REGION_FLAT(BL_RO_DATA_BASE, in bl2_el3_plat_arch_setup()
[all …]
Dbl31_plat_setup.c131 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
133 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
135 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE,
137 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
139 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
141 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
143 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE,
155 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, in bl31_plat_arch_setup()
157 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, in bl31_plat_arch_setup()
159 MAP_REGION_FLAT(BL_RO_DATA_BASE, in bl31_plat_arch_setup()
[all …]
/trusted-firmware-a-3.6.0-3.5.0/plat/intel/soc/agilex/
Dbl2_plat_setup.c37 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
39 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
41 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE,
43 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
45 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
47 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
49 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE,
96 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, in bl2_el3_plat_arch_setup()
98 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, in bl2_el3_plat_arch_setup()
100 MAP_REGION_FLAT(BL_RO_DATA_BASE, in bl2_el3_plat_arch_setup()
[all …]
Dbl31_plat_setup.c144 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
145 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS),
146 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
147 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
149 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
151 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS),
152 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS),
163 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, in bl31_plat_arch_setup()
165 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, in bl31_plat_arch_setup()
167 MAP_REGION_FLAT(BL_RO_DATA_BASE, in bl31_plat_arch_setup()
[all …]
/trusted-firmware-a-3.6.0-3.5.0/plat/renesas/common/aarch64/
Dplatform_common.c33 #define MAP_SHARED_RAM MAP_REGION_FLAT(RCAR_SHARED_MEM_BASE, \
37 #define MAP_FLASH0 MAP_REGION_FLAT(FLASH0_BASE, \
41 #define MAP_DRAM1_NS MAP_REGION_FLAT(DRAM1_NS_BASE, \
45 #define MAP_DEVICE_RCAR MAP_REGION_FLAT(DEVICE_RCAR_BASE, \
49 #define MAP_DEVICE_RCAR2 MAP_REGION_FLAT(DEVICE_RCAR_BASE2, \
53 #define MAP_SRAM MAP_REGION_FLAT(DEVICE_SRAM_BASE, \
57 #define MAP_SRAM_STACK MAP_REGION_FLAT(DEVICE_SRAM_STACK_BASE, \
61 #define MAP_ATFW_CRASH MAP_REGION_FLAT(RCAR_BL31_CRASH_BASE, \
65 #define MAP_ATFW_LOG MAP_REGION_FLAT(RCAR_BL31_LOG_BASE, \
69 #define MAP_DRAM0 MAP_REGION_FLAT(DRAM1_BASE, \
[all …]
/trusted-firmware-a-3.6.0-3.5.0/plat/nvidia/tegra/soc/t194/
Dplat_setup.c89 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x4000U, /* 16KB */
91 MAP_REGION_FLAT(TEGRA_GPCDMA_BASE, 0x10000U, /* 64KB */
93 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x8000U, /* 32KB */
95 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x8000U, /* 32KB */
98 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/
100 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */
102 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */
105 MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x2000U, /* 8KB */
107 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x1000, /* 4KB */
109 MAP_REGION_FLAT(TEGRA_GICC_BASE, 0x1000, /* 4KB */
[all …]
/trusted-firmware-a-3.6.0-3.5.0/plat/intel/soc/n5x/
Dbl31_plat_setup.c124 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
126 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
128 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE,
130 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
132 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
134 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
136 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE,
148 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, in bl31_plat_arch_setup()
150 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, in bl31_plat_arch_setup()
152 MAP_REGION_FLAT(BL_RO_DATA_BASE, in bl31_plat_arch_setup()
[all …]
/trusted-firmware-a-3.6.0-3.5.0/plat/rockchip/rk3368/drivers/soc/
Dsoc.c21 MAP_REGION_FLAT(CCI400_BASE, CCI400_SIZE,
23 MAP_REGION_FLAT(GIC400_BASE, GIC400_SIZE,
25 MAP_REGION_FLAT(STIME_BASE, STIME_SIZE,
27 MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE,
29 MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE,
31 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE,
33 MAP_REGION_FLAT(UART0_BASE, UART0_SIZE,
35 MAP_REGION_FLAT(UART1_BASE, UART1_SIZE,
37 MAP_REGION_FLAT(UART2_BASE, UART2_SIZE,
39 MAP_REGION_FLAT(UART3_BASE, UART3_SIZE,
[all …]
/trusted-firmware-a-3.6.0-3.5.0/plat/imx/imx8m/imx8mm/
Dimx8mm_bl31_setup.c42 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW),
43 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */
44 MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_DEVICE | MT_RW), /* OCRAM_S */
45 MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW), /* DDRMIX */
46 MAP_REGION_FLAT(IMX_VPUMIX_BASE, IMX_VPUMIX_SIZE, MT_DEVICE | MT_RW), /* VPUMIX */
47 MAP_REGION_FLAT(IMX_CAAM_RAM_BASE, IMX_CAAM_RAM_SIZE, MT_MEMORY | MT_RW), /* CAMM RAM */
48 MAP_REGION_FLAT(IMX_NS_OCRAM_BASE, IMX_NS_OCRAM_SIZE, MT_MEMORY | MT_RW), /* NS OCRAM */
49 MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM code */
50 MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), /* DRAM */
188 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE)
[all …]
/trusted-firmware-a-3.6.0-3.5.0/plat/qemu/common/
Dqemu_common.c18 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
23 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
29 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \
34 #define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \
38 #define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \
41 #define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \
44 #define MAP_FLASH0 MAP_REGION_FLAT(QEMU_FLASH0_BASE, QEMU_FLASH0_SIZE, \
47 #define MAP_FLASH1 MAP_REGION_FLAT(QEMU_FLASH1_BASE, QEMU_FLASH1_SIZE, \
/trusted-firmware-a-3.6.0-3.5.0/plat/nxp/common/setup/include/
Dmmu_def.h16 #define LS_MAP_CCSR MAP_REGION_FLAT(NXP_CCSR_ADDR, \
21 #define LS_MAP_DCSR MAP_REGION_FLAT(NXP_DCSR_ADDR, \
26 #define LS_MAP_CONSOLE MAP_REGION_FLAT(NXP_DUART1_ADDR, \
30 #define LS_MAP_OCRAM MAP_REGION_FLAT(NXP_OCRAM_ADDR, \
/trusted-firmware-a-3.6.0-3.5.0/plat/ti/k3/common/
Dk3_bl31_setup.c25 MAP_REGION_FLAT(K3_USART_BASE, K3_USART_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
26 MAP_REGION_FLAT(K3_GIC_BASE, K3_GIC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
27 MAP_REGION_FLAT(K3_GTC_BASE, K3_GTC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
28 MAP_REGION_FLAT(SEC_PROXY_RT_BASE, SEC_PROXY_RT_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
29 MAP_REGION_FLAT(SEC_PROXY_SCFG_BASE, SEC_PROXY_SCFG_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
30 MAP_REGION_FLAT(SEC_PROXY_DATA_BASE, SEC_PROXY_DATA_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
105 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE), in bl31_plat_arch_setup()
106 …MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_CODE | MT_… in bl31_plat_arch_setup()
107 …MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, MT_RO_DATA | MT_… in bl31_plat_arch_setup()
109 …MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, MT_DEVICE | MT_… in bl31_plat_arch_setup()
/trusted-firmware-a-3.6.0-3.5.0/plat/xilinx/versal/aarch64/
Dversal_common.c23 MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
24 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
25 MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
26 MAP_REGION_FLAT(PLAT_ARM_CCI_BASE, PLAT_ARM_CCI_SIZE, MT_DEVICE | MT_RW |
/trusted-firmware-a-3.6.0-3.5.0/plat/hisilicon/hikey/aarch64/
Dhikey_common.c19 #define MAP_DDR MAP_REGION_FLAT(DDR_BASE, \
23 #define MAP_DEVICE MAP_REGION_FLAT(DEVICE_BASE, \
27 #define MAP_TSP_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \
31 #define MAP_ROM_PARAM MAP_REGION_FLAT(XG2RAM0_BASE, \
35 #define MAP_SRAM MAP_REGION_FLAT(SRAM_BASE, \
43 #define MAP_MMC_SRAM MAP_REGION_FLAT(HIKEY_BL1_MMC_DESC_BASE, \
/trusted-firmware-a-3.6.0-3.5.0/plat/hisilicon/hikey960/aarch64/
Dhikey960_common.c21 #define MAP_DDR MAP_REGION_FLAT(DDR_BASE, \
25 #define MAP_DEVICE MAP_REGION_FLAT(DEVICE_BASE, \
29 #define MAP_BL1_RW MAP_REGION_FLAT(BL1_RW_BASE, \
33 #define MAP_UFS_DATA MAP_REGION_FLAT(HIKEY960_UFS_DATA_BASE, \
37 #define MAP_UFS_DESC MAP_REGION_FLAT(HIKEY960_UFS_DESC_BASE, \
41 #define MAP_TSP_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \

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