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Searched refs:tWR_IN_NS (Results 1 – 2 of 2) sorted by relevance

/trusted-firmware-a-3.4.0/plat/intel/soc/agilex/soc/
Dagilex_memory_controller.c30 #define tWR_IN_NS 15 macro
244 tw_rin_clk_cycles = (((tWR_IN_NS * 1333) % 1000) >= 500) ? in configure_ddr_sched_ctrl_regs()
245 ((tWR_IN_NS * 1333) / 1000) + 1 : in configure_ddr_sched_ctrl_regs()
246 ((tWR_IN_NS * 1333) / 1000); in configure_ddr_sched_ctrl_regs()
252 tw_rin_clk_cycles = (((tWR_IN_NS * 1066) % 1000) >= 500) ? in configure_ddr_sched_ctrl_regs()
253 ((tWR_IN_NS * 1066) / 1000) + 1 : in configure_ddr_sched_ctrl_regs()
254 ((tWR_IN_NS * 1066) / 1000); in configure_ddr_sched_ctrl_regs()
/trusted-firmware-a-3.4.0/plat/intel/soc/stratix10/soc/
Ds10_memory_controller.c34 #define tWR_IN_NS 15 macro
273 tw_rin_clk_cycles = (((tWR_IN_NS * 1333) % 1000) >= 500) ? in configure_ddr_sched_ctrl_regs()
274 ((tWR_IN_NS * 1333) / 1000) + 1 : in configure_ddr_sched_ctrl_regs()
275 ((tWR_IN_NS * 1333) / 1000); in configure_ddr_sched_ctrl_regs()
281 tw_rin_clk_cycles = (((tWR_IN_NS * 1066) % 1000) >= 500) ? in configure_ddr_sched_ctrl_regs()
282 ((tWR_IN_NS * 1066) / 1000) + 1 : in configure_ddr_sched_ctrl_regs()
283 ((tWR_IN_NS * 1066) / 1000); in configure_ddr_sched_ctrl_regs()