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/trusted-firmware-a-3.4.0/plat/nxp/common/sip_svc/include/
Dsipsvc.h60 #define SIP_PARAM_TYPE_GET(t, i) ((((uint32_t)(t)) >> ((i) * 4)) & 0xF) argument
66 #define SIP_PARAM_TYPE_SET(t, i) (((uint32_t)(t) & 0xF) << ((i) * 4)) argument
/trusted-firmware-a-3.4.0/include/lib/
Dbakery_lock.h26 static inline unsigned int bakery_get_priority(unsigned int t, unsigned int pos) in bakery_get_priority() argument
28 return (t << 8) | pos; in bakery_get_priority()
/trusted-firmware-a-3.4.0/plat/mediatek/mt8183/drivers/mcdi/
Dmtk_mcdi.c90 uint32_t t = 0; in target_mask() local
94 t |= BIT(cluster + CLUSTER_ON_OFS); in target_mask()
97 t |= BIT(cpu_idx + CPU_ON_OFS); in target_mask()
100 t |= BIT(cluster + CLUSTER_OFF_OFS); in target_mask()
103 t |= BIT(cpu_idx + CPU_OFF_OFS); in target_mask()
106 return t; in target_mask()
/trusted-firmware-a-3.4.0/lib/gpt_rme/
Dgpt_rme.c65 gpt_t_val_e t; member
187 GPT_PPS_ACTUAL_SIZE(gpt_config.t)) || in gpt_validate_pas_mappings()
330 gpt_config.t = gpt_t_lookup[pps]; in gpt_validate_l0_params()
334 if (l0_alignment < GPT_L0_TABLE_SIZE(gpt_config.t)) { in gpt_validate_l0_params()
335 l0_alignment = GPT_L0_TABLE_SIZE(gpt_config.t); in gpt_validate_l0_params()
345 if (l0_mem_size < GPT_L0_TABLE_SIZE(gpt_config.t)) { in gpt_validate_l0_params()
347 GPT_L0_TABLE_SIZE(gpt_config.t), in gpt_validate_l0_params()
779 for (unsigned int i = 0U; i < GPT_L0_REGION_COUNT(gpt_config.t); i++) { in gpt_init_l0_tables()
785 (size_t)GPT_L0_TABLE_SIZE(gpt_config.t)); in gpt_init_l0_tables()
860 INFO(" PPS/T: 0x%x/%u\n", gpt_config.pps, gpt_config.t); in gpt_init_pas_l1_tables()
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/trusted-firmware-a-3.4.0/docs/resources/diagrams/plantuml/
Dfconf_bl2_populate.puml22 bl2_main -> arm_bl2_setup : bl2_early_platform_setup2(\n\t arg0, arg1, arg2, arg3)
27 arm_bl2_setup -> arm_bl2_setup : arm_bl2_early_platform_setup(\n\t fw_config, mem_layout)
/trusted-firmware-a-3.4.0/lib/debugfs/
Ddevfip.c246 int r, n, t; in fipmount() local
283 t = cspec->index; in fipmount()
284 if (devtab[t]->seek(cspec, STOC_HEADER, KSEEK_SET) < 0) { in fipmount()
/trusted-firmware-a-3.4.0/plat/arm/board/common/swd_rotpk/
Darm_swd_rotprivk_rsa.pem6 pmgS7XJKhCQYxdDSzxi/0t/qXAwWuME4jv2HbNxsUZjahiBYpA0BafXanSuxVHly
/trusted-firmware-a-3.4.0/tools/marvell/doimage/secure/
Dcsk_priv_pem3.key19 t/pXCienrcUNfgIxwSSnNwj2DdjejzI+4VNfPbW6y16BLPCp1CbUOGOwNXTj4R9H
/trusted-firmware-a-3.4.0/docs/plat/
Drpi3.rst10 officially supported kernel is a AArch32 kernel. This doesn't mean that this
11 port of TF-A can't boot a AArch64 kernel. The `Linux tree fork`_ maintained by
15 **IMPORTANT NOTE**: This port isn't secure. All of the memory used is DRAM,
17 shouldn't be considered more than a prototype to play with and implement
54 in AArch32. This means that BL33 can't be in EL2 in AArch64 mode. The
55 architecture specifies that AArch32 Hypervisor mode isn't present when AArch64
131 so that the kernel doesn't use it. The current port tries to modify the live DTB
139 different mappings than the Arm cores in which the I/O addresses don't overlap
141 the end of the DRAM, so this space isn't wasted.
166 ``PSCI_SYSTEM_RESET`` and ``PSCI_SYSTEM_OFF``. The last one doesn't really turn
[all …]
Dmeson-axg.rst12 can't be turned off, so there is a workaround to hide this from the caller.
Dmeson-g12a.rst12 can't be turned off, so there is a workaround to hide this from the caller.
Dmeson-gxbb.rst12 can't be turned off, so there is a workaround to hide this from the caller.
Dmeson-gxl.rst12 can't be turned off, so there is a workaround to hide this from the caller.
/trusted-firmware-a-3.4.0/plat/arm/board/juno/fdts/
Djuno_tb_fw_config.dts16 * heap information. The default values don't matter since
/trusted-firmware-a-3.4.0/plat/arm/board/morello/fdts/
Dmorello_tb_fw_config.dts17 * heap information. The default values don't matter since
/trusted-firmware-a-3.4.0/plat/arm/board/n1sdp/fdts/
Dn1sdp_tb_fw_config.dts17 * heap information. The default values don't matter since
/trusted-firmware-a-3.4.0/plat/arm/board/rde1edge/fdts/
Drde1edge_tb_fw_config.dts18 * heap information. The default values don't matter since
/trusted-firmware-a-3.4.0/plat/arm/board/rdn1edge/fdts/
Drdn1edge_tb_fw_config.dts17 * heap information. The default values don't matter since
/trusted-firmware-a-3.4.0/plat/arm/board/rdn2/fdts/
Drdn2_tb_fw_config.dts18 * heap information. The default values don't matter since
/trusted-firmware-a-3.4.0/plat/arm/board/rdv1/fdts/
Drdv1_tb_fw_config.dts18 * heap information. The default values don't matter since
/trusted-firmware-a-3.4.0/plat/arm/board/rdv1mc/fdts/
Drdv1mc_tb_fw_config.dts18 * heap information. The default values don't matter since
/trusted-firmware-a-3.4.0/plat/arm/board/sgi575/fdts/
Dsgi575_tb_fw_config.dts18 * heap information. The default values don't matter since
/trusted-firmware-a-3.4.0/plat/arm/board/fvp/fdts/
Dfvp_fw_config.dts30 * non shared SRAM. The runtime checks ensure we don't
/trusted-firmware-a-3.4.0/drivers/rpi3/sdhost/
Drpi3_sdhost.c485 volatile int t = timeout; in rpi3_sdhost_read() local
490 if (t == 0) { in rpi3_sdhost_read()
496 t--; in rpi3_sdhost_read()
499 if (t == 0) in rpi3_sdhost_read()
/trusted-firmware-a-3.4.0/include/drivers/nxp/sd/
Dsd_mmc.h26 #define ESDHC_SYSCTL_DTOCV(t) (((t) & 0xF) << 16) argument

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