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/trusted-firmware-a-3.4.0/lib/coreboot/
Dcoreboot_table.c97 coreboot_memrange_t *range = &coreboot_memranges[i]; in coreboot_get_memory_type() local
99 if (range->type == CB_MEM_NONE) in coreboot_get_memory_type()
101 if ((start >= range->start) && in coreboot_get_memory_type()
102 (start - range->start < range->size) && in coreboot_get_memory_type()
103 (size <= range->size - (start - range->start))) { in coreboot_get_memory_type()
104 return range->type; in coreboot_get_memory_type()
/trusted-firmware-a-3.4.0/fdts/
Dfvp-ve-Cortex-A5x1.dts69 freq-range = <50000000 100000000>;
78 freq-range = <5000000 50000000>;
87 freq-range = <80000000 120000000>;
96 freq-range = <23750000 165000000>;
105 freq-range = <80000000 80000000>;
114 freq-range = <25000000 60000000>;
Dn1sdp.dtsi159 bus-range = <0 17>;
182 bus-range = <0 17>;
Dmorello-soc.dts94 bus-range = <0 255>;
130 bus-range = <0 255>;
Dn1sdp-multi-chip.dts73 bus-range = <0 0xff>;
Drtsm_ve-motherboard.dtsi209 freq-range = <23750000 63500000>;
Drtsm_ve-motherboard-aarch32.dtsi210 freq-range = <23750000 63500000>;
/trusted-firmware-a-3.4.0/plat/renesas/common/
Dplat_pm.c49 unsigned long range; in rcar_program_mailbox() local
52 range = (unsigned long)&rcar_mboxes[linear_id]; in rcar_program_mailbox()
54 flush_dcache_range(range, sizeof(range)); in rcar_program_mailbox()
/trusted-firmware-a-3.4.0/tools/marvell/doimage/secure/
Dsec_img_7K.cfg14 # index of CSK key in the array. Valid range is 0 to 15
Dsec_img_8K.cfg14 # index of CSK key in the array. Valid range is 0 to 15
/trusted-firmware-a-3.4.0/docs/getting_started/
Drt-svc-writers-guide.rst38 are allocated a range of of OENs. The OEN must be interpreted in conjunction
63 range as they need - it is not necessary to coordinate with other entities of
65 within the SiP Service calls OEN range to mean different things - as these
92 the name of the service, the range of OENs covered, the type of service and
290 ``0xC4000000``-``0xC400FFFF`` functions. Within that range, the `PSCI`_ service
Dpsci-lib-integration-guide.rst253 PSCI service range specified in `SMCCC`_. The function ID ``smc_fid`` (first
/trusted-firmware-a-3.4.0/docs/design/
Dpsci-pd-tree.rst157 MPIDRs have been sparsely allocated, that is, the size of the range of MPIDRs
171 is equal to the size of the range of MPIDRs allocated. This approach will
199 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx
Dfirmware-design.rst894 Each implemented service handles a range of SMC function identifiers as
901 the name of the service, the range of OENs covered, the type of service and
943 #. Multiple descriptors for the same range of OENs and ``call_type``
944 #. Incorrect range of owning entity numbers for a given ``call_type``
955 128 distinct services, but in practice a single descriptor can cover a range of
2096 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx
/trusted-firmware-a-3.4.0/plat/rockchip/rk3399/drivers/dram/
Ddram_spec_timing.h59 #define range(mi, val, ma) (((ma) > (val)) ? (max(mi, val)) : (ma)) macro
/trusted-firmware-a-3.4.0/lib/romlib/
Dromlib_generator.py211 for item_index in range(0, len(index_file_parser.items)):
/trusted-firmware-a-3.4.0/docs/security_advisories/
Dsecurity-advisory-tfv-7.rst77 ``SMCCC_ARCH_WORKAROUND_2`` in the Arm architectural range to allow callers at
Dsecurity-advisory-tfv-4.rst48 range. Therefore, any AArch32 code relying on this macro to detect such integer
/trusted-firmware-a-3.4.0/docs/plat/
Dqti-msm8916.rst8 various mid-range smartphones/tablets.
Drz-g2.rst12 cover the full product range, from the premium class to the entry
Drcar-gen3.rst9 cover the full product range, from the premium class to the entry
/trusted-firmware-a-3.4.0/docs/components/
Darm-sip-service.rst12 - Use SMC function IDs that fall in the SiP range, which are ``0xc2000000`` -
Dsecure-partition-manager-mm.rst62 - A range of synchronous exceptions (e.g. SMC function identifiers).
307 Secure Service calls range (see `SMC Calling Convention`_ (*Arm DEN 0028B*)
/trusted-firmware-a-3.4.0/docs/plat/marvell/armada/
Dbuild.rst99 for SRAM address range at BL31 execution stage with window target set to DRAM-0.
131 values with CP_NUM are in a range of 1 to 3.
/trusted-firmware-a-3.4.0/docs/plat/arm/
Darm-build-options.rst152 to select the appropriate platform variant for the build. The range of

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