| /trusted-firmware-a-3.4.0/plat/rockchip/rk3399/drivers/soc/ |
| D | soc.c | 53 static void set_pll_slow_mode(uint32_t pll_id) in set_pll_slow_mode() argument
55 if (pll_id == PPLL_ID) in set_pll_slow_mode()
59 CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in set_pll_slow_mode()
62 static void set_pll_normal_mode(uint32_t pll_id) in set_pll_normal_mode() argument
64 if (pll_id == PPLL_ID) in set_pll_normal_mode()
68 CRU_PLL_CON(pll_id, 3), PLL_NOMAL_MODE); in set_pll_normal_mode()
71 static void set_pll_bypass(uint32_t pll_id) in set_pll_bypass() argument
73 if (pll_id == PPLL_ID) in set_pll_bypass()
78 CRU_PLL_CON(pll_id, 3), PLL_BYPASS_MODE); in set_pll_bypass()
81 static void _pll_suspend(uint32_t pll_id) in _pll_suspend() argument
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| D | soc.h | 16 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) argument
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| /trusted-firmware-a-3.4.0/plat/rockchip/rk3368/drivers/soc/ |
| D | soc.c | 125 static void plls_suspend(uint32_t pll_id) in plls_suspend() argument
127 plls_con[pll_id][0] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 0)); in plls_suspend()
128 plls_con[pll_id][1] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 1)); in plls_suspend()
129 plls_con[pll_id][2] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 2)); in plls_suspend()
130 plls_con[pll_id][3] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 3)); in plls_suspend()
132 mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_SLOW_BITS); in plls_suspend()
133 mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_BYPASS); in plls_suspend()
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| /trusted-firmware-a-3.4.0/plat/rockchip/rk3328/drivers/pmu/ |
| D | pmu.c | 270 static inline void pm_pll_wait_lock(uint32_t pll_id) in pm_pll_wait_lock() argument
275 if (mmio_read_32(CRU_BASE + PLL_CONS(pll_id, 1)) & in pm_pll_wait_lock()
281 ERROR("lock-pll: %d\n", pll_id); in pm_pll_wait_lock()
284 static inline void pll_pwr_dwn(uint32_t pll_id, uint32_t pd) in pll_pwr_dwn() argument
286 mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), in pll_pwr_dwn()
289 mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), in pll_pwr_dwn()
292 mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), in pll_pwr_dwn()
340 static inline void pll_suspend(uint32_t pll_id) in pll_suspend() argument
345 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(pll_id)); in pll_suspend()
349 ddr_data.cru_plls_con_save[pll_id][i] = in pll_suspend()
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| D | pmu.h | 116 #define PLL_IS_NORM_MODE(mode, pll_id) \ argument
117 ((mode & (PLL_NORM_MODE(pll_id)) & 0xffff) != 0)
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| /trusted-firmware-a-3.4.0/plat/rockchip/rk3288/drivers/soc/ |
| D | soc.c | 105 static void pll_save(uint32_t pll_id) in pll_save() argument
107 uint32_t *pll = slp_data.pll_con[pll_id]; in pll_save()
109 pll[0] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 0)); in pll_save()
110 pll[1] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 1)); in pll_save()
111 pll[2] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 2)); in pll_save()
112 pll[3] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 3)); in pll_save()
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| /trusted-firmware-a-3.4.0/plat/rockchip/px30/drivers/pmu/ |
| D | pmu.c | 855 static inline void pm_pll_wait_lock(uint32_t pll_base, uint32_t pll_id) in pm_pll_wait_lock() argument
867 ERROR("Can't wait pll:%d lock\n", pll_id); in pm_pll_wait_lock()
870 static inline void pll_pwr_ctr(uint32_t pll_base, uint32_t pll_id, uint32_t pd) in pll_pwr_ctr() argument
882 static inline void pll_set_mode(uint32_t pll_id, uint32_t mode) in pll_set_mode() argument
884 uint32_t val = BITS_WITH_WMASK(mode, 0x3, PLL_MODE_SHIFT(pll_id)); in pll_set_mode()
886 if (pll_id != GPLL_ID) in pll_set_mode()
893 static inline void pll_suspend(uint32_t pll_id) in pll_suspend() argument
898 if (pll_id != GPLL_ID) in pll_suspend()
899 pll_base = CRU_BASE + CRU_PLL_CONS(pll_id, 0); in pll_suspend()
905 ddr_data.cru_plls_con_save[pll_id][i] = in pll_suspend()
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| /trusted-firmware-a-3.4.0/plat/rockchip/rk3399/drivers/dram/ |
| D | suspend.c | 653 __pmusramfunc static void pmusram_restore_pll(int pll_id, uint32_t *src) in pmusram_restore_pll() argument
655 mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in pmusram_restore_pll()
657 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK); in pmusram_restore_pll()
658 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK); in pmusram_restore_pll()
659 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2]); in pmusram_restore_pll()
660 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 4), src[4] | REG_SOC_WMSK); in pmusram_restore_pll()
661 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 5), src[5] | REG_SOC_WMSK); in pmusram_restore_pll()
663 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK); in pmusram_restore_pll()
665 while ((mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 2)) & in pmusram_restore_pll()
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| /trusted-firmware-a-3.4.0/drivers/st/clk/ |
| D | stm32mp1_clk.c | 833 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, in stm32mp1_read_pll_freq() argument
836 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); in stm32mp1_read_pll_freq()
1471 static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id, in stm32mp1_check_pll_conf() argument
1475 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); in stm32mp1_check_pll_conf()
1546 static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id) in stm32mp1_pll_start() argument
1548 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); in stm32mp1_pll_start()
1558 static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output) in stm32mp1_pll_output() argument
1560 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); in stm32mp1_pll_output()
1568 pll_id, pllxcr, mmio_read_32(pllxcr)); in stm32mp1_pll_output()
1579 static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id) in stm32mp1_pll_stop() argument
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| D | clk-stm32mp13.c | 1632 int pll_id; member
1640 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id); in clk_stm32_pll_recalc_rate()
1677 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id); in clk_stm32_pll_is_enabled()
1686 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id); in clk_stm32_pll_enable()
1695 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id); in clk_stm32_pll_disable()
1713 .pll_id = _pll_id,\
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| /trusted-firmware-a-3.4.0/plat/rockchip/rk3399/drivers/pmu/ |
| D | pmu.c | 565 uint32_t pll_id, clst_st_msk, clst_st_chk_msk, pmu_st; in clst_pwr_domain_suspend() local
571 pll_id = ALPLL_ID; in clst_pwr_domain_suspend()
574 pll_id = ABPLL_ID; in clst_pwr_domain_suspend()
586 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), in clst_pwr_domain_suspend()
589 clst_warmboot_data[pll_id] = PMU_CLST_RET; in clst_pwr_domain_suspend()
599 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), in clst_pwr_domain_suspend()
601 clst_warmboot_data[pll_id] = 0; in clst_pwr_domain_suspend()
609 uint32_t pll_id, pll_st; in clst_pwr_domain_resume() local
615 pll_id = ALPLL_ID; in clst_pwr_domain_resume()
617 pll_id = ABPLL_ID; in clst_pwr_domain_resume()
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