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Searched refs:core (Results 1 – 25 of 87) sorted by relevance

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/trusted-firmware-a-3.4.0/plat/allwinner/common/
Dsunxi_cpu_ops.c22 static void sunxi_cpu_disable_power(unsigned int cluster, unsigned int core) in sunxi_cpu_disable_power() argument
24 if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0xff) in sunxi_cpu_disable_power()
27 VERBOSE("PSCI: Disabling power to cluster %d core %d\n", cluster, core); in sunxi_cpu_disable_power()
29 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xff); in sunxi_cpu_disable_power()
32 static void sunxi_cpu_enable_power(unsigned int cluster, unsigned int core) in sunxi_cpu_enable_power() argument
34 if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0) in sunxi_cpu_enable_power()
37 VERBOSE("PSCI: Enabling power to cluster %d core %d\n", cluster, core); in sunxi_cpu_enable_power()
40 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xfe); in sunxi_cpu_enable_power()
41 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xf8); in sunxi_cpu_enable_power()
42 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xe0); in sunxi_cpu_enable_power()
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Darisc_off.S6 # OpenRISC assembly to turn off an ARM core on an Allwinner SoC from
18 # very ARM core to be turned off.
19 # It expects the core number presented as a mask in the upper half of
25 # - Loop until the core in question reaches WFI.
26 # - Using that mask, activate the core output clamps by setting the
27 # respective core bit in CPUX_PWROFF_GATING_REG (0x1f01500).
28 # Note that the clamp for core 0 covers more than just the core, activating
29 # it hangs the whole system. So we skip this step for core 0.
30 # - Using the negated mask, assert the core's reset line by clearing the
58 l.bf 1f # don't touch the bit for core 0
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Dsunxi_topology.c24 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); in plat_core_pos_by_mpidr() local
29 core >= PLATFORM_MAX_CPUS_PER_CLUSTER) { in plat_core_pos_by_mpidr()
33 return cluster * PLATFORM_MAX_CPUS_PER_CLUSTER + core; in plat_core_pos_by_mpidr()
/trusted-firmware-a-3.4.0/plat/hisilicon/hikey960/drivers/pwrc/
Dhisi_pwrc.c27 #define CPUIDLE_LOCK_ID(core) (0x6 - (core)) argument
95 static void hisi_cpuhotplug_lock(unsigned int cluster, unsigned int core) in hisi_cpuhotplug_lock() argument
99 lock_id = (cluster << 2) + core; in hisi_cpuhotplug_lock()
104 static void hisi_cpuhotplug_unlock(unsigned int cluster, unsigned int core) in hisi_cpuhotplug_unlock() argument
108 lock_id = (cluster << 2) + core; in hisi_cpuhotplug_unlock()
114 void hisi_cpuidle_lock(unsigned int cluster, unsigned int core) in hisi_cpuidle_lock() argument
118 hisi_resource_lock(CPUIDLE_LOCK_ID(core), offset); in hisi_cpuidle_lock()
122 void hisi_cpuidle_unlock(unsigned int cluster, unsigned int core) in hisi_cpuidle_unlock() argument
126 hisi_resource_unlock(CPUIDLE_LOCK_ID(core), offset); in hisi_cpuidle_unlock()
139 void hisi_set_cpuidle_flag(unsigned int cluster, unsigned int core) in hisi_set_cpuidle_flag() argument
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Dhisi_pwrc.h33 void hisi_cpuidle_lock(unsigned int cluster, unsigned int core);
34 void hisi_cpuidle_unlock(unsigned int cluster, unsigned int core);
35 void hisi_set_cpuidle_flag(unsigned int cluster, unsigned int core);
36 void hisi_clear_cpuidle_flag(unsigned int cluster, unsigned int core);
37 void hisi_set_cpu_boot_flag(unsigned int cluster, unsigned int core);
38 void hisi_clear_cpu_boot_flag(unsigned int cluster, unsigned int core);
40 void hisi_enter_core_idle(unsigned int cluster, unsigned int core);
41 void hisi_enter_cluster_idle(unsigned int cluster, unsigned int core);
43 void hisi_enter_ap_suspend(unsigned int cluster, unsigned int core);
48 int hisi_test_pwrdn_allcores(unsigned int cluster, unsigned int core);
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/trusted-firmware-a-3.4.0/plat/mediatek/mt8192/drivers/ptp3/
Dmtk_ptp3_main.c38 void ptp3_init(unsigned int core) in ptp3_init() argument
43 if (core < NR_PTP3_CFG1_CPU) { in ptp3_init()
46 ptp3_cfg1[core][PTP3_CFG_ADDR], in ptp3_init()
47 ptp3_cfg1[core][PTP3_CFG_VALUE]); in ptp3_init()
51 if (core >= PTP3_CFG2_CPU_START_ID) { in ptp3_init()
52 _core = core - PTP3_CFG2_CPU_START_ID; in ptp3_init()
63 if (core >= PTP3_CFG3_CPU_START_ID) { in ptp3_init()
64 _core = core - PTP3_CFG3_CPU_START_ID; in ptp3_init()
75 void ptp3_deinit(unsigned int core) in ptp3_deinit() argument
77 if (core < NR_PTP3_CFG1_CPU) { in ptp3_deinit()
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Dmtk_ptp3_common.h45 extern void ptp3_init(unsigned int core);
46 extern void ptp3_deinit(unsigned int core);
/trusted-firmware-a-3.4.0/plat/hisilicon/hikey960/
Dhikey960_pm.c64 unsigned int core = mpidr & MPIDR_CPU_MASK; in hikey960_pwr_domain_on() local
69 hisi_set_cpu_boot_flag(cluster, core); in hikey960_pwr_domain_on()
71 mmio_write_32(CRG_REG_BASE + CRG_RVBAR(cluster, core), in hikey960_pwr_domain_on()
75 hisi_powerup_core(cluster, core); in hikey960_pwr_domain_on()
77 hisi_powerup_cluster(cluster, core); in hikey960_pwr_domain_on()
95 unsigned int core = mpidr & MPIDR_CPU_MASK; in hikey960_pwr_domain_off() local
105 hisi_clear_cpu_boot_flag(cluster, core); in hikey960_pwr_domain_off()
106 hisi_powerdn_core(cluster, core); in hikey960_pwr_domain_off()
109 if (hisi_test_cpu_down(cluster, core)) { in hikey960_pwr_domain_off()
116 hisi_powerdn_cluster(cluster, core); in hikey960_pwr_domain_off()
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/trusted-firmware-a-3.4.0/plat/mediatek/mt8195/drivers/ptp3/
Dmtk_ptp3_main.c10 #define PTP3_CORE_OFT(core) (0x800 * (core)) argument
31 static void ptp3_init(unsigned int core) in ptp3_init() argument
35 if (core < PTP3_CFG_CPU_START_ID_B) { in ptp3_init()
43 if (core < PTP3_CFG_CPU_START_ID_B) { in ptp3_init()
46 PTP3_CORE_OFT(core); in ptp3_init()
54 PTP3_CORE_OFT(core); in ptp3_init()
65 if (core < PTP3_CFG_CPU_START_ID_B) { in ptp3_init()
66 addr = ptp3_cfg3[PTP3_CFG_ADDR] + PTP3_CORE_OFT(core); in ptp3_init()
73 addr = ptp3_cfg3_ext[PTP3_CFG_ADDR] + PTP3_CORE_OFT(core); in ptp3_init()
124 void ptp3_core_init(unsigned int core) in ptp3_core_init() argument
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Dmtk_ptp3_common.h49 extern void ptp3_core_init(unsigned int core);
50 extern void ptp3_core_unInit(unsigned int core);
/trusted-firmware-a-3.4.0/plat/ti/k3/common/
Dk3_topology.c29 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); in plat_core_pos_by_mpidr() local
37 core += K3_CLUSTER0_CORE_COUNT; in plat_core_pos_by_mpidr()
39 core += K3_CLUSTER1_CORE_COUNT; in plat_core_pos_by_mpidr()
41 core += K3_CLUSTER2_CORE_COUNT; in plat_core_pos_by_mpidr()
45 return core; in plat_core_pos_by_mpidr()
Dk3_psci.c44 int core, proc_id, device_id, ret; in k3_pwr_domain_on() local
46 core = plat_core_pos_by_mpidr(mpidr); in k3_pwr_domain_on()
47 if (core < 0) { in k3_pwr_domain_on()
48 ERROR("Could not get target core id: %d\n", core); in k3_pwr_domain_on()
52 proc_id = PLAT_PROC_START_ID + core; in k3_pwr_domain_on()
53 device_id = PLAT_PROC_DEVICE_START_ID + core; in k3_pwr_domain_on()
88 int core, cluster, proc_id, device_id, cluster_id, ret; in k3_pwr_domain_off() local
96 core = plat_my_core_pos(); in k3_pwr_domain_off()
98 proc_id = PLAT_PROC_START_ID + core; in k3_pwr_domain_off()
99 device_id = PLAT_PROC_DEVICE_START_ID + core; in k3_pwr_domain_off()
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/trusted-firmware-a-3.4.0/plat/amlogic/g12a/
Dg12a_pm.c32 unsigned int core = plat_calc_core_pos(mpidr); in g12a_pm_set_reset_addr() local
33 uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4); in g12a_pm_set_reset_addr()
40 unsigned int core = plat_calc_core_pos(mpidr); in g12a_pm_reset() local
41 uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4) + 8; in g12a_pm_reset()
102 unsigned int core = plat_calc_core_pos(mpidr); in g12a_pwr_domain_on() local
105 if (core == AML_PRIMARY_CPU) { in g12a_pwr_domain_on()
130 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in g12a_pwr_domain_on_finish() local
135 if (core == AML_PRIMARY_CPU) { in g12a_pwr_domain_on_finish()
150 unsigned int core = plat_calc_core_pos(mpidr); in g12a_pwr_domain_off() local
155 if (core == AML_PRIMARY_CPU) in g12a_pwr_domain_off()
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/trusted-firmware-a-3.4.0/plat/amlogic/gxl/
Dgxl_pm.c32 unsigned int core = plat_calc_core_pos(mpidr); in gxl_pm_set_reset_addr() local
33 uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4); in gxl_pm_set_reset_addr()
40 unsigned int core = plat_calc_core_pos(mpidr); in gxl_pm_reset() local
41 uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4) + 8; in gxl_pm_reset()
102 unsigned int core = plat_calc_core_pos(mpidr); in gxl_pwr_domain_on() local
105 if (core == AML_PRIMARY_CPU) { in gxl_pwr_domain_on()
130 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in gxl_pwr_domain_on_finish() local
135 if (core == AML_PRIMARY_CPU) { in gxl_pwr_domain_on_finish()
150 unsigned int core = plat_calc_core_pos(mpidr); in gxl_pwr_domain_off() local
155 if (core == AML_PRIMARY_CPU) in gxl_pwr_domain_off()
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/trusted-firmware-a-3.4.0/plat/amlogic/gxbb/
Dgxbb_pm.c32 unsigned int core = plat_calc_core_pos(mpidr); in gxbb_program_mailbox() local
33 uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4); in gxbb_program_mailbox()
87 unsigned int core = plat_calc_core_pos(mpidr); in gxbb_pwr_domain_on() local
90 if (core == AML_PRIMARY_CPU) { in gxbb_pwr_domain_on()
114 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in gxbb_pwr_domain_on_finish() local
119 if (core == AML_PRIMARY_CPU) { in gxbb_pwr_domain_on_finish()
133 unsigned int core = plat_calc_core_pos(mpidr); in gxbb_pwr_domain_off() local
134 uintptr_t addr = AML_PSCI_MAILBOX_BASE + 8 + (core << 4); in gxbb_pwr_domain_off()
142 if (core == AML_PRIMARY_CPU) in gxbb_pwr_domain_off()
152 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in gxbb_pwr_domain_pwr_down_wfi() local
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/trusted-firmware-a-3.4.0/plat/hisilicon/hikey960/include/
Dhisi_ipc.h15 void hisi_ipc_pm_on_off(unsigned int core, unsigned int cluster,
17 void hisi_ipc_pm_suspend(unsigned int core, unsigned int cluster,
19 void hisi_ipc_psci_system_off(unsigned int core, unsigned int cluster);
20 void hisi_ipc_psci_system_reset(unsigned int core, unsigned int cluster,
/trusted-firmware-a-3.4.0/lib/fconf/
Dfconf_mpmm_getter.c32 struct mpmm_core *core; in fconf_populate_mpmm_cpu() local
39 core = &fconf_mpmm_topology.cores[core_pos]; in fconf_populate_mpmm_cpu()
43 core->supported = true; in fconf_populate_mpmm_cpu()
46 core->supported = false; in fconf_populate_mpmm_cpu()
/trusted-firmware-a-3.4.0/plat/qti/msm8916/
Dmsm8916_topology.c20 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); in plat_core_pos_by_mpidr() local
25 core >= PLATFORM_MAX_CPUS_PER_CLUSTER) { in plat_core_pos_by_mpidr()
29 return core; in plat_core_pos_by_mpidr()
Dmsm8916_pm.c20 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); in msm8916_pwr_domain_on() local
22 VERBOSE("PSCI: Booting CPU %d\n", core); in msm8916_pwr_domain_on()
23 msm8916_cpu_boot(core); in msm8916_pwr_domain_on()
/trusted-firmware-a-3.4.0/plat/hisilicon/hikey960/drivers/ipc/
Dhisi_ipc.c133 void hisi_ipc_pm_on_off(unsigned int core, unsigned int cluster, in hisi_ipc_pm_on_off() argument
139 enum lpm3_mbox_id mailbox = (enum lpm3_mbox_id)(LPM3_MBX0 + core); in hisi_ipc_pm_on_off()
142 cmdpara = IPC_CMD_PARA(0, core); in hisi_ipc_pm_on_off()
147 void hisi_ipc_pm_suspend(unsigned int core, unsigned int cluster, in hisi_ipc_pm_suspend() argument
153 enum lpm3_mbox_id mailbox = (enum lpm3_mbox_id)(LPM3_MBX0 + core); in hisi_ipc_pm_suspend()
160 cmdpara = IPC_CMD_PARA(1, core); in hisi_ipc_pm_suspend()
165 void hisi_ipc_psci_system_off(unsigned int core, unsigned int cluster) in hisi_ipc_psci_system_off() argument
170 enum lpm3_mbox_id mailbox = (enum lpm3_mbox_id)(LPM3_MBX0 + core); in hisi_ipc_psci_system_off()
178 void hisi_ipc_psci_system_reset(unsigned int core, unsigned int cluster, in hisi_ipc_psci_system_reset() argument
184 enum lpm3_mbox_id mailbox = (enum lpm3_mbox_id)(LPM3_MBX0 + core); in hisi_ipc_psci_system_reset()
/trusted-firmware-a-3.4.0/plat/nvidia/tegra/soc/t186/drivers/mce/
Dnvg.c204 int32_t nvg_online_core(uint32_t ari_base, uint32_t core) in nvg_online_core() argument
213 if ((core >= MCE_CORE_ID_MAX) || (cpu == core)) { in nvg_online_core()
214 ERROR("%s: unsupported core id (%d)\n", __func__, core); in nvg_online_core()
220 if ((impl == DENVER_IMPL) && ((core == 2U) || (core == 3U))) { in nvg_online_core()
221 ERROR("%s: unknown core id (%d)\n", __func__, core); in nvg_online_core()
226 ((uint64_t)core & MCE_CORE_ID_MASK)); in nvg_online_core()
/trusted-firmware-a-3.4.0/plat/hisilicon/hikey/include/
Dhisi_pwrc.h13 void hisi_pwrc_set_core_bx_addr(unsigned int core,
16 void hisi_pwrc_enable_debug(unsigned int core,
/trusted-firmware-a-3.4.0/plat/hisilicon/hikey/
Dhisi_pwrc.c25 void hisi_pwrc_set_core_bx_addr(unsigned int core, unsigned int cluster, in hisi_pwrc_set_core_bx_addr() argument
36 i = cluster * CLUSTER_CORE_COUNT + core; in hisi_pwrc_set_core_bx_addr()
55 void hisi_pwrc_enable_debug(unsigned int core, unsigned int cluster) in hisi_pwrc_enable_debug() argument
59 enable = 1U << (core + PDBGUP_CLUSTER1_SHIFT * cluster); in hisi_pwrc_enable_debug()
/trusted-firmware-a-3.4.0/docs/design/
Dpsci-pd-tree.rst36 #. The attributes of a core power domain differ from the attributes of power
37 domains at higher levels. For example, only a core power domain can be identified
39 performing a power management operation on the core power domain.
125 unique number (core index) between ``0`` and ``PLAT_CORE_COUNT - 1`` to each core
129 ``plat_core_pos_by_mpidr(mpidr)`` will return the core index for the core
131 which is not allocated or corresponds to an absent core. The semantics of this
135 Another mandatory API, ``plat_my_core_pos()`` has been added to return the core
136 index for the calling core. This API provides a more lightweight mechanism to get
137 the index since there is no need to validate the MPIDR of the calling core.
139 The platform should assign the core indices (as illustrated in the diagram above)
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/trusted-firmware-a-3.4.0/include/plat/arm/common/
Dfconf_ethosn_getter.h17 ethosn_config.core[idx].addr; \
31 struct ethosn_core_t core[ETHOSN_CORE_NUM_MAX]; member

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