Home
last modified time | relevance | path

Searched refs:base (Results 1 – 25 of 263) sorted by relevance

1234567891011

/trusted-firmware-a-3.4.0/drivers/arm/gic/v3/
Dgicdv3_helpers.c22 void gicd_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg) in gicd_set_icfgr() argument
28 mmio_clrsetbits_32(base + GICD_OFFSET(ICFG, id), in gicd_set_icfgr()
37 unsigned int gicd_get_igroupr(uintptr_t base, unsigned int id) in gicd_get_igroupr() argument
39 return GICD_GET_BIT(IGROUP, base, id); in gicd_get_igroupr()
42 void gicd_set_igroupr(uintptr_t base, unsigned int id) in gicd_set_igroupr() argument
44 GICD_SET_BIT(IGROUP, base, id); in gicd_set_igroupr()
47 void gicd_clr_igroupr(uintptr_t base, unsigned int id) in gicd_clr_igroupr() argument
49 GICD_CLR_BIT(IGROUP, base, id); in gicd_clr_igroupr()
56 unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id) in gicd_get_igrpmodr() argument
58 return GICD_GET_BIT(IGRPMOD, base, id); in gicd_get_igrpmodr()
[all …]
Dgicv3_private.h69 #define GICD_READ(REG, base, id) \ argument
70 mmio_read_32((base) + GICD_OFFSET(REG, (id)))
72 #define GICD_READ_64(REG, base, id) \ argument
73 mmio_read_64((base) + GICD_OFFSET_64(REG, (id)))
75 #define GICD_WRITE_8(REG, base, id, val) \ argument
76 mmio_write_8((base) + GICD_OFFSET_8(REG, (id)), (val))
78 #define GICD_WRITE(REG, base, id, val) \ argument
79 mmio_write_32((base) + GICD_OFFSET(REG, (id)), (val))
81 #define GICD_WRITE_64(REG, base, id, val) \ argument
82 mmio_write_64((base) + GICD_OFFSET_64(REG, (id)), (val))
[all …]
Dgic600ae_fmu_helpers.c19 #define GIC_FMU_WRITE_32(base, reg, val) \ argument
25 mmio_write_32(base + GICFMU_KEY, 0xBE); \
27 mmio_write_32((base) + (reg), (val)); \
31 #define GIC_FMU_WRITE_64(base, reg, n, val) \ argument
37 mmio_write_32(base + GICFMU_KEY, 0xBE); \
42 mmio_write_32((base) + reg##_LO + (n * 64), (val)); \
43 mmio_write_32((base) + reg##_HI + (n * 64), (val)); \
47 static void wait_until_fmu_is_idle(uintptr_t base) in wait_until_fmu_is_idle() argument
54 status = (gic_fmu_read_status(base) & BIT(0)); in wait_until_fmu_is_idle()
66 #define GIC_FMU_WRITE_ON_IDLE_32(base, reg, val) \ argument
[all …]
Dgicrv3_helpers.c24 unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id) in gicr_read_ipriorityr() argument
26 return GICR_READ(IPRIORITY, base, id); in gicr_read_ipriorityr()
29 void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val) in gicr_write_ipriorityr() argument
31 GICR_WRITE(IPRIORITY, base, id, val); in gicr_write_ipriorityr()
38 void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri) in gicr_set_ipriorityr() argument
40 GICR_WRITE_8(IPRIORITY, base, id, (uint8_t)(pri & GIC_PRI_MASK)); in gicr_set_ipriorityr()
47 unsigned int gicr_get_igroupr(uintptr_t base, unsigned int id) in gicr_get_igroupr() argument
49 return GICR_GET_BIT(IGROUP, base, id); in gicr_get_igroupr()
52 void gicr_set_igroupr(uintptr_t base, unsigned int id) in gicr_set_igroupr() argument
54 GICR_SET_BIT(IGROUP, base, id); in gicr_set_igroupr()
[all …]
/trusted-firmware-a-3.4.0/drivers/arm/gic/common/
Dgic_common_private.h18 static inline unsigned int gicd_read_ctlr(uintptr_t base) in gicd_read_ctlr() argument
20 return mmio_read_32(base + GICD_CTLR); in gicd_read_ctlr()
23 static inline unsigned int gicd_read_typer(uintptr_t base) in gicd_read_typer() argument
25 return mmio_read_32(base + GICD_TYPER); in gicd_read_typer()
28 static inline unsigned int gicd_read_iidr(uintptr_t base) in gicd_read_iidr() argument
30 return mmio_read_32(base + GICD_IIDR); in gicd_read_iidr()
33 static inline void gicd_write_ctlr(uintptr_t base, unsigned int val) in gicd_write_ctlr() argument
35 mmio_write_32(base + GICD_CTLR, val); in gicd_write_ctlr()
43 unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id);
44 unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id);
[all …]
Dgic_common.c23 unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id) in gicd_read_igroupr() argument
27 return mmio_read_32(base + GICD_IGROUPR + (n << 2)); in gicd_read_igroupr()
34 unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id) in gicd_read_isenabler() argument
38 return mmio_read_32(base + GICD_ISENABLER + (n << 2)); in gicd_read_isenabler()
45 unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id) in gicd_read_icenabler() argument
49 return mmio_read_32(base + GICD_ICENABLER + (n << 2)); in gicd_read_icenabler()
56 unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id) in gicd_read_ispendr() argument
60 return mmio_read_32(base + GICD_ISPENDR + (n << 2)); in gicd_read_ispendr()
67 unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id) in gicd_read_icpendr() argument
71 return mmio_read_32(base + GICD_ICPENDR + (n << 2)); in gicd_read_icpendr()
[all …]
/trusted-firmware-a-3.4.0/drivers/arm/gic/v2/
Dgicv2_private.h25 unsigned int gicv2_get_cpuif_id(uintptr_t base);
30 static inline unsigned int gicd_read_pidr2(uintptr_t base) in gicd_read_pidr2() argument
32 return mmio_read_32(base + GICD_PIDR2_GICV2); in gicd_read_pidr2()
38 static inline unsigned int gicd_get_itargetsr(uintptr_t base, unsigned int id) in gicd_get_itargetsr() argument
40 return mmio_read_8(base + GICD_ITARGETSR + id); in gicd_get_itargetsr()
43 static inline void gicd_set_itargetsr(uintptr_t base, unsigned int id, in gicd_set_itargetsr() argument
48 mmio_write_8(base + GICD_ITARGETSR + id, val); in gicd_set_itargetsr()
51 static inline void gicd_write_sgir(uintptr_t base, unsigned int val) in gicd_write_sgir() argument
53 mmio_write_32(base + GICD_SGIR, val); in gicd_write_sgir()
60 static inline unsigned int gicc_read_ctlr(uintptr_t base) in gicc_read_ctlr() argument
[all …]
Dgicdv2_helpers.c21 unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id) in gicd_read_igroupr() argument
25 return mmio_read_32(base + GICD_IGROUPR + (n << 2)); in gicd_read_igroupr()
32 unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id) in gicd_read_isenabler() argument
36 return mmio_read_32(base + GICD_ISENABLER + (n << 2)); in gicd_read_isenabler()
43 unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id) in gicd_read_icenabler() argument
47 return mmio_read_32(base + GICD_ICENABLER + (n << 2)); in gicd_read_icenabler()
54 unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id) in gicd_read_ispendr() argument
58 return mmio_read_32(base + GICD_ISPENDR + (n << 2)); in gicd_read_ispendr()
65 unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id) in gicd_read_icpendr() argument
69 return mmio_read_32(base + GICD_ICPENDR + (n << 2)); in gicd_read_icpendr()
[all …]
/trusted-firmware-a-3.4.0/plat/hisilicon/hikey960/drivers/pwrc/
Dhisi_pwrc.h16 #define SOC_CRGPERIPH_A53_PDCEN_ADDR(base) ((base) + (0x260)) argument
17 #define SOC_CRGPERIPH_MAIA_PDCEN_ADDR(base) ((base) + (0x300)) argument
19 #define SOC_PCTRL_RESOURCE0_LOCK_ADDR(base) ((base) + (0x400)) argument
20 #define SOC_PCTRL_RESOURCE0_UNLOCK_ADDR(base) ((base) + (0x404)) argument
21 #define SOC_PCTRL_RESOURCE0_LOCK_ST_ADDR(base) ((base) + (0x408)) argument
22 #define SOC_PCTRL_RESOURCE1_LOCK_ADDR(base) ((base) + (0x40C)) argument
23 #define SOC_PCTRL_RESOURCE1_UNLOCK_ADDR(base) ((base) + (0x410)) argument
24 #define SOC_PCTRL_RESOURCE1_LOCK_ST_ADDR(base) ((base) + (0x414)) argument
25 #define SOC_PCTRL_RESOURCE2_LOCK_ADDR(base) ((base) + (0x418)) argument
27 #define SOC_SCTRL_SCBAKDATA3_ADDR(base) ((base) + (0x418)) argument
[all …]
/trusted-firmware-a-3.4.0/drivers/arm/sp805/
Dsp805.c14 static inline void sp805_write_wdog_load(uintptr_t base, uint32_t value) in sp805_write_wdog_load() argument
16 mmio_write_32(base + SP805_WDOG_LOAD_OFF, value); in sp805_write_wdog_load()
19 static inline void sp805_write_wdog_ctrl(uintptr_t base, uint32_t value) in sp805_write_wdog_ctrl() argument
21 mmio_write_32(base + SP805_WDOG_CTR_OFF, value); in sp805_write_wdog_ctrl()
24 static inline void sp805_write_wdog_lock(uintptr_t base, uint32_t value) in sp805_write_wdog_lock() argument
26 mmio_write_32(base + SP805_WDOG_LOCK_OFF, value); in sp805_write_wdog_lock()
32 void sp805_start(uintptr_t base, unsigned int ticks) in sp805_start() argument
34 sp805_write_wdog_load(base, ticks); in sp805_start()
35 sp805_write_wdog_ctrl(base, SP805_CTR_RESEN | SP805_CTR_INTEN); in sp805_start()
37 sp805_write_wdog_lock(base, 0U); in sp805_start()
[all …]
/trusted-firmware-a-3.4.0/plat/mediatek/common/drivers/uart/
Duart.c21 unsigned long base; in mt_uart_restore() local
28 base = uart->base; in mt_uart_restore()
30 mmio_write_32(UART_LCR(base), UART_LCR_MODE_B); in mt_uart_restore()
31 mmio_write_32(UART_EFR(base), uart->registers.efr); in mt_uart_restore()
32 mmio_write_32(UART_LCR(base), uart->registers.lcr); in mt_uart_restore()
33 mmio_write_32(UART_FCR(base), uart->registers.fcr); in mt_uart_restore()
36 mmio_write_32(UART_HIGHSPEED(base), uart->registers.highspeed); in mt_uart_restore()
37 mmio_write_32(UART_FRACDIV_L(base), uart->registers.fracdiv_l); in mt_uart_restore()
38 mmio_write_32(UART_FRACDIV_M(base), uart->registers.fracdiv_m); in mt_uart_restore()
39 mmio_write_32(UART_LCR(base), in mt_uart_restore()
[all …]
/trusted-firmware-a-3.4.0/drivers/arm/tzc/
Dtzc380.c15 uintptr_t base; member
22 static unsigned int tzc380_read_build_config(uintptr_t base) in tzc380_read_build_config() argument
24 return mmio_read_32(base + TZC380_CONFIGURATION_OFF); in tzc380_read_build_config()
27 static void tzc380_write_action(uintptr_t base, unsigned int action) in tzc380_write_action() argument
29 mmio_write_32(base + ACTION_OFF, action); in tzc380_write_action()
32 static void tzc380_write_region_base_low(uintptr_t base, unsigned int region, in tzc380_write_region_base_low() argument
35 mmio_write_32(base + REGION_SETUP_LOW_OFF(region), val); in tzc380_write_region_base_low()
38 static void tzc380_write_region_base_high(uintptr_t base, unsigned int region, in tzc380_write_region_base_high() argument
41 mmio_write_32(base + REGION_SETUP_HIGH_OFF(region), val); in tzc380_write_region_base_high()
44 static void tzc380_write_region_attributes(uintptr_t base, unsigned int region, in tzc380_write_region_attributes() argument
[all …]
Dtzc400.c34 uintptr_t base; member
42 static inline unsigned int _tzc400_read_build_config(uintptr_t base) in _tzc400_read_build_config() argument
44 return mmio_read_32(base + BUILD_CONFIG_OFF); in _tzc400_read_build_config()
47 static inline unsigned int _tzc400_read_gate_keeper(uintptr_t base) in _tzc400_read_gate_keeper() argument
49 return mmio_read_32(base + GATE_KEEPER_OFF); in _tzc400_read_gate_keeper()
52 static inline void _tzc400_write_gate_keeper(uintptr_t base, unsigned int val) in _tzc400_write_gate_keeper() argument
54 mmio_write_32(base + GATE_KEEPER_OFF, val); in _tzc400_write_gate_keeper()
75 static void _tzc400_clear_it(uintptr_t base, uint32_t filter) in _tzc400_clear_it() argument
77 mmio_write_32(base + INT_CLEAR, BIT_32(filter)); in _tzc400_clear_it()
80 static uint32_t _tzc400_get_int_by_filter(uintptr_t base, uint32_t filter) in _tzc400_get_int_by_filter() argument
[all …]
Dtzc_common_private.h17 uintptr_t base, \
20 mmio_write_32(base + TZC_##macro_name##_ACTION_OFF, \
26 uintptr_t base, \
30 mmio_write_32(base + \
36 mmio_write_32(base + \
46 uintptr_t base, \
50 mmio_write_32(base + \
56 mmio_write_32(base + \
66 uintptr_t base, \
70 mmio_write_32(base + \
[all …]
/trusted-firmware-a-3.4.0/drivers/brcm/
Docotp.c59 uint32_t base; member
64 .base = OTPC_MODE_REG,
69 uint32_t base; member
77 static inline void set_command(uint32_t base, uint32_t command) in set_command() argument
79 mmio_write_32(base + OTPC_COMMAND_OFFSET, command & OTPC_CMD_MASK); in set_command()
82 static inline void set_cpu_address(uint32_t base, uint32_t addr) in set_cpu_address() argument
84 mmio_write_32(base + OTPC_CPUADDR_REG_OFFSET, addr & OTPC_ADDR_MASK); in set_cpu_address()
87 static inline void set_start_bit(uint32_t base) in set_start_bit() argument
89 mmio_write_32(base + OTPC_CMD_START_OFFSET, 1 << OTPC_CMD_START_START); in set_start_bit()
92 static inline void reset_start_bit(uint32_t base) in reset_start_bit() argument
[all …]
/trusted-firmware-a-3.4.0/plat/socionext/uniphier/
Duniphier_console_setup.c49 uintptr_t base, end; in uniphier_console_get_base() local
53 base = uniphier_uart_base[soc]; in uniphier_console_get_base()
54 end = base + UNIPHIER_UART_OFFSET * UNIPHIER_UART_NR_PORTS; in uniphier_console_get_base()
56 while (base < end) { in uniphier_console_get_base()
57 div = mmio_read_32(base + UNIPHIER_UART_DLR); in uniphier_console_get_base()
59 return base; in uniphier_console_get_base()
60 base += UNIPHIER_UART_OFFSET; in uniphier_console_get_base()
66 static void uniphier_console_init(uintptr_t base) in uniphier_console_init() argument
68 mmio_write_32(base + UNIPHIER_UART_FCR, UNIPHIER_UART_FCR_ENABLE_FIFO); in uniphier_console_init()
69 mmio_write_32(base + UNIPHIER_UART_LCR_MCR, in uniphier_console_init()
[all …]
/trusted-firmware-a-3.4.0/plat/imx/common/sci/
Dimx8_mu.c11 void MU_Resume(uint32_t base) in MU_Resume() argument
15 reg = mmio_read_32(base + MU_ACR_OFFSET1); in MU_Resume()
19 mmio_write_32(base + MU_ACR_OFFSET1, reg); in MU_Resume()
23 MU_EnableRxFullInt(base, i); in MU_Resume()
26 void MU_EnableRxFullInt(uint32_t base, uint32_t index) in MU_EnableRxFullInt() argument
28 uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1); in MU_EnableRxFullInt()
32 mmio_write_32(base + MU_ACR_OFFSET1, reg); in MU_EnableRxFullInt()
35 void MU_EnableGeneralInt(uint32_t base, uint32_t index) in MU_EnableGeneralInt() argument
37 uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1); in MU_EnableGeneralInt()
41 mmio_write_32(base + MU_ACR_OFFSET1, reg); in MU_EnableGeneralInt()
[all …]
Dipc.c36 uint32_t base = id; in sc_ipc_open() local
40 if ((ipc == NULL) || (base == 0)) in sc_ipc_open()
46 MU_Init(base); in sc_ipc_open()
50 MU_EnableRxFullInt(base, i); in sc_ipc_open()
61 uint32_t base = ipc; in sc_ipc_close() local
63 if (base != 0) in sc_ipc_close()
64 MU_Init(base); in sc_ipc_close()
69 uint32_t base = ipc; in sc_ipc_read() local
74 if ((base == 0) || (msg == NULL)) in sc_ipc_read()
78 MU_ReceiveMsg(base, 0, (uint32_t *) msg); in sc_ipc_read()
[all …]
/trusted-firmware-a-3.4.0/drivers/marvell/mochi/
Dcp110_setup.c161 static void cp110_errata_wa_init(uintptr_t base) in cp110_errata_wa_init() argument
175 data = mmio_read_32(base + MVEBU_SOC_CFG_REG(MVEBU_SOC_CFG_REG_NUM)); in cp110_errata_wa_init()
177 mmio_write_32(base + MVEBU_SOC_CFG_REG(MVEBU_SOC_CFG_REG_NUM), data); in cp110_errata_wa_init()
180 static void cp110_pcie_clk_cfg(uintptr_t base) in cp110_pcie_clk_cfg() argument
188 reg = mmio_read_32(base + MVEBU_SAMPLE_AT_RESET_REG); in cp110_pcie_clk_cfg()
193 if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A2 || in cp110_pcie_clk_cfg()
194 cp110_device_id_get(base) == MVEBU_CN9130_DEV_ID) { in cp110_pcie_clk_cfg()
199 reg = mmio_read_32(base + MVEBU_PCIE_REF_CLK_BUF_CTRL); in cp110_pcie_clk_cfg()
206 mmio_write_32(base + MVEBU_PCIE_REF_CLK_BUF_CTRL, reg); in cp110_pcie_clk_cfg()
210 if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A1) { in cp110_pcie_clk_cfg()
[all …]
/trusted-firmware-a-3.4.0/plat/marvell/armada/a8k/common/mss/
Dmss_defs.h11 #define MSS_DMA_SRCBR(base) (base + 0xC0) argument
12 #define MSS_DMA_DSTBR(base) (base + 0xC4) argument
13 #define MSS_DMA_CTRLR(base) (base + 0xC8) argument
14 #define MSS_M3_RSTCR(base) (base + 0xFC) argument
/trusted-firmware-a-3.4.0/plat/rpi/rpi4/
Drpi4_pci_svc.c48 uint64_t base; in pci_segment_lib_get_base() local
52 base = PCIE_REG_BASE; in pci_segment_lib_get_base()
65 base += PCIE_EXT_CFG_DATA; in pci_segment_lib_get_base()
87 return base + offset; in pci_segment_lib_get_base()
114 uint64_t base; in pci_read_config() local
117 base = pci_segment_lib_get_base(addr, off); in pci_read_config()
119 if (base == INVALID_PCI_ADDR) { in pci_read_config()
120 *val = base; in pci_read_config()
124 *val = mmio_read_8(base); in pci_read_config()
127 *val = mmio_read_16(base); in pci_read_config()
[all …]
/trusted-firmware-a-3.4.0/drivers/arm/sbsa/
Dsbsa.c13 void sbsa_watchdog_offset_reg_write(uintptr_t base, uint64_t value) in sbsa_watchdog_offset_reg_write() argument
16 mmio_write_32(base + SBSA_WDOG_WOR_LOW_OFFSET, in sbsa_watchdog_offset_reg_write()
18 mmio_write_32(base + SBSA_WDOG_WOR_HIGH_OFFSET, (uint32_t)(value >> 32)); in sbsa_watchdog_offset_reg_write()
26 void sbsa_wdog_start(uintptr_t base, uint64_t ms) in sbsa_wdog_start() argument
34 sbsa_watchdog_offset_reg_write(base, offset_reg_value); in sbsa_wdog_start()
35 mmio_write_32(base + SBSA_WDOG_WCS_OFFSET, SBSA_WDOG_WCS_EN); in sbsa_wdog_start()
39 void sbsa_wdog_stop(uintptr_t base) in sbsa_wdog_stop() argument
41 mmio_write_32(base + SBSA_WDOG_WCS_OFFSET, (0x0)); in sbsa_wdog_stop()
/trusted-firmware-a-3.4.0/drivers/arm/scu/
Dscu.c17 void enable_snoop_ctrl_unit(uintptr_t base) in enable_snoop_ctrl_unit() argument
23 assert(base != 0U); in enable_snoop_ctrl_unit()
24 scu_ctrl = mmio_read_32(base + SCU_CTRL_REG); in enable_snoop_ctrl_unit()
32 mmio_write_32(base + SCU_CTRL_REG, scu_ctrl); in enable_snoop_ctrl_unit()
46 uint32_t read_snoop_ctrl_unit_cfg(uintptr_t base) in read_snoop_ctrl_unit_cfg() argument
48 assert(base != 0U); in read_snoop_ctrl_unit_cfg()
50 return mmio_read_32(base + SCU_CFG_REG); in read_snoop_ctrl_unit_cfg()
/trusted-firmware-a-3.4.0/include/drivers/arm/
Dgic600ae_fmu.h130 uint64_t gic_fmu_read_errfr(uintptr_t base, unsigned int n);
131 uint64_t gic_fmu_read_errctlr(uintptr_t base, unsigned int n);
132 uint64_t gic_fmu_read_errstatus(uintptr_t base, unsigned int n);
133 uint64_t gic_fmu_read_errgsr(uintptr_t base);
134 uint32_t gic_fmu_read_pingctlr(uintptr_t base);
135 uint32_t gic_fmu_read_pingnow(uintptr_t base);
136 uint64_t gic_fmu_read_pingmask(uintptr_t base);
137 uint32_t gic_fmu_read_status(uintptr_t base);
138 uint32_t gic_fmu_read_erridr(uintptr_t base);
139 void gic_fmu_write_errctlr(uintptr_t base, unsigned int n, uint64_t val);
[all …]
/trusted-firmware-a-3.4.0/lib/libc/
Dstrtoul.c48 unsigned long strtoul(const char *nptr, char **endptr, int base) in strtoul() argument
71 if ((base == 0 || base == 16) && in strtoul()
78 base = 16; in strtoul()
80 if (base == 0) in strtoul()
81 base = c == '0' ? 8 : 10; in strtoul()
84 cutoff = ULONG_MAX / base; in strtoul()
85 cutlim = ULONG_MAX % base; in strtoul()
95 if (c >= base) in strtoul()
101 acc *= base; in strtoul()

1234567891011