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Searched refs:addresses (Results 1 – 18 of 18) sorted by relevance

/trusted-firmware-a-3.4.0/common/
Dfdt_fixup.c200 uint32_t addresses[4]; in fdt_add_reserved_memory() local
217 addresses[idx] = cpu_to_fdt32(HIGH_BITS(base)); in fdt_add_reserved_memory()
220 addresses[idx] = cpu_to_fdt32(base & 0xffffffff); in fdt_add_reserved_memory()
223 addresses[idx] = cpu_to_fdt32(HIGH_BITS(size)); in fdt_add_reserved_memory()
226 addresses[idx] = cpu_to_fdt32(size & 0xffffffff); in fdt_add_reserved_memory()
230 fdt_setprop(dtb, offs, "reg", addresses, idx * sizeof(uint32_t)); in fdt_add_reserved_memory()
/trusted-firmware-a-3.4.0/docs/plat/arm/arm_fpga/
Dindex.rst13 configuration: the UART and GIC base addresses are read from there.
70 This will use the default load addresses as described above. When those
71 addresses need to differ for a certain setup, they can be passed on the
87 components at their respective load addresses. In addition to this file
/trusted-firmware-a-3.4.0/tools/marvell/doimage/secure/
Dsec_img_7K.cfg27 # Two register addresses for each connected CP
Dsec_img_8K.cfg27 # Two register addresses for each connected CP
/trusted-firmware-a-3.4.0/docs/plat/
Dintel-agilex.rst57 aarch64-linux-gnu-objcopy -I binary -O ihex --change-addresses 0xffe00000 bl2.bin bl2.hex
Drpi4.rst73 memory. The load addresses have a default, but can also be changed by
75 armstub image file, it will put those two load addresses in memory locations
Dallwinner.rst132 address space. So the virtual addresses used in BL31 match the physical
133 addresses as presented above.
Dintel-stratix10.rst57 aarch64-linux-gnu-objcopy -I binary -O ihex --change-addresses 0xffe00000 bl2.bin bl2.hex
Drpi3.rst62 between them so that the addresses they are loaded to match the ones specified
89 All addresses are Physical Addresses from the point of view of the Arm cores.
139 different mappings than the Arm cores in which the I/O addresses don't overlap
197 The build system concatenates BL1 and the FIP so that the addresses match the
/trusted-firmware-a-3.4.0/plat/allwinner/common/
Darisc_off.S81 # same as above, but with the MMIO addresses matching the H6 SoC
/trusted-firmware-a-3.4.0/plat/nvidia/tegra/scat/
Dbl31.scat74 * security. GOT is a table of addresses so ensure 8-byte alignment.
/trusted-firmware-a-3.4.0/docs/components/
Dxlat-tables-lib-v2-design.rst39 removing all mentions of virtual addresses). Although potential bug fixes will
112 the MPU's translations are limited to specification of valid addresses and
113 access permissions. If the requested virtual and physical addresses mismatch
395 directly maps regions by "base" and "limit" (bottom and top) addresses.
Dsecure-partition-manager.rst575 For the S-EL2 SPMC, base addresses for memory and device region nodes are IPAs
1225 generation of a pointer authentication code for return addresses (pointer
/trusted-firmware-a-3.4.0/docs/getting_started/
Dbuild-options.rst590 - ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the
591 bottom, higher addresses at the top. This build flag can be set to '1' to
592 invert this behavior. Lower addresses will be printed at the top and higher
593 addresses at the bottom.
1066 Using ``-O0`` could cause output images to be larger and base addresses
Dporting-guide.rst54 only for re-mapping peripheral physical addresses and allows platforms with high
55 I/O addresses to reduce their virtual address space. All other addresses
64 an identity mapping for all addresses.
456 used, choose the smallest value needed to map the required virtual addresses
/trusted-firmware-a-3.4.0/docs/design/
Dfirmware-design.rst1552 correspond to particular addresses. TF-A code can refer to these symbols to
1643 How to choose the right base addresses for each bootloader stage image
1648 locations and the base addresses of each image must be chosen carefully such
1650 the base addresses might need adjustments to cope with the new memory layout.
1653 general recipe for choosing the right base addresses for each bootloader image.
/trusted-firmware-a-3.4.0/docs/
Dchange-log.md101 …- allow to access all register addresses if DEBUG=1 ([7e954df](https://review.trustedfirmware.org/…
336 …- update IP addresses for STM32MP13 ([52ac998](https://review.trustedfirmware.org/plugins/gitiles/…
2951 - NV-counter base addresses are now loaded from the device tree when
2959 - DTB and BL33 load addresses have been given sensible default values
2960 - Now reads generic timer counter frequency, GICD and GICR base addresses,
3427 controller, and eMMC controller base addresses configurable
3490 - allwinner: Fix H6 GPIO and CCU memory map addresses and incorrect ARISC code
4600 attempt to access addresses in the higher VA range.
4960 - Imported libfdt v1.4.2 that addresses buffer overflow in fdt_offset_ptr().
5494 - It is now possible to map higher physical addresses using non-flat virtual to
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/trusted-firmware-a-3.4.0/docs/threat_model/
Dthreat_model.rst666 | implemented? | Data received from normal world, such as addresses |