1 /*
2  * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef VERSAL_DEF_H
8 #define VERSAL_DEF_H
9 
10 #include <plat/arm/common/smccc_def.h>
11 #include <plat/common/common_def.h>
12 
13 /* List all consoles */
14 #define VERSAL_CONSOLE_ID_pl011	1
15 #define VERSAL_CONSOLE_ID_pl011_0	1
16 #define VERSAL_CONSOLE_ID_pl011_1	2
17 #define VERSAL_CONSOLE_ID_dcc		3
18 
19 #define VERSAL_CONSOLE_IS(con)	(VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE)
20 
21 /* List all supported platforms */
22 #define VERSAL_PLATFORM_ID_versal_virt	1
23 #define VERSAL_PLATFORM_ID_spp_itr6	2
24 #define VERSAL_PLATFORM_ID_emu_itr6	3
25 #define VERSAL_PLATFORM_ID_silicon	4
26 
27 #define VERSAL_PLATFORM_IS(con)	(VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM)
28 
29 /* Firmware Image Package */
30 #define VERSAL_PRIMARY_CPU	0
31 
32 /*******************************************************************************
33  * memory map related constants
34  ******************************************************************************/
35 #define DEVICE0_BASE		0xFF000000
36 #define DEVICE0_SIZE		0x00E00000
37 #define DEVICE1_BASE		0xF9000000
38 #define DEVICE1_SIZE		0x00800000
39 
40 /* CRL */
41 #define VERSAL_CRL				0xFF5E0000
42 #define VERSAL_CRL_TIMESTAMP_REF_CTRL		(VERSAL_CRL + 0x14C)
43 #define VERSAL_CRL_RST_TIMESTAMP_OFFSET	(VERSAL_CRL + 0x348)
44 
45 #define VERSAL_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT	(1 << 25)
46 
47 /* IOU SCNTRS */
48 #define VERSAL_IOU_SCNTRS			 0xFF140000
49 #define VERSAL_IOU_SCNTRS_COUNTER_CONTROL_REG	(VERSAL_IOU_SCNTRS + 0x0)
50 #define VERSAL_IOU_SCNTRS_BASE_FREQ		(VERSAL_IOU_SCNTRS + 0x20)
51 
52 #define VERSAL_IOU_SCNTRS_CONTROL_EN	1
53 
54 /*******************************************************************************
55  * IRQ constants
56  ******************************************************************************/
57 #define VERSAL_IRQ_SEC_PHY_TIMER		U(29)
58 
59 /*******************************************************************************
60  * CCI-400 related constants
61  ******************************************************************************/
62 #define PLAT_ARM_CCI_BASE		0xFD000000
63 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX	4
64 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX	5
65 
66 /*******************************************************************************
67  * UART related constants
68  ******************************************************************************/
69 #define VERSAL_UART0_BASE		0xFF000000
70 #define VERSAL_UART1_BASE		0xFF010000
71 
72 #if VERSAL_CONSOLE_IS(pl011) || VERSAL_CONSOLE_IS(dcc)
73 # define VERSAL_UART_BASE	VERSAL_UART0_BASE
74 #elif VERSAL_CONSOLE_IS(pl011_1)
75 # define VERSAL_UART_BASE	VERSAL_UART1_BASE
76 #else
77 # error "invalid VERSAL_CONSOLE"
78 #endif
79 
80 #define PLAT_VERSAL_CRASH_UART_BASE		VERSAL_UART_BASE
81 #define PLAT_VERSAL_CRASH_UART_CLK_IN_HZ	VERSAL_UART_CLOCK
82 #define VERSAL_CONSOLE_BAUDRATE			VERSAL_UART_BAUDRATE
83 
84 /*******************************************************************************
85  * Platform related constants
86  ******************************************************************************/
87 #if VERSAL_PLATFORM_IS(versal_virt)
88 # define PLATFORM_NAME		"Versal Virt"
89 # define VERSAL_UART_CLOCK	25000000
90 # define VERSAL_UART_BAUDRATE	115200
91 # define VERSAL_CPU_CLOCK	2720000
92 #elif VERSAL_PLATFORM_IS(silicon)
93 # define PLATFORM_NAME		"Versal Silicon"
94 # define VERSAL_UART_CLOCK	100000000
95 # define VERSAL_UART_BAUDRATE	115200
96 # define VERSAL_CPU_CLOCK	100000000
97 #elif VERSAL_PLATFORM_IS(spp_itr6)
98 # define PLATFORM_NAME          "SPP ITR6"
99 # define VERSAL_UART_CLOCK      25000000
100 # define VERSAL_UART_BAUDRATE   115200
101 # define VERSAL_CPU_CLOCK       2720000
102 #elif VERSAL_PLATFORM_IS(emu_itr6)
103 # define PLATFORM_NAME          "EMU ITR6"
104 # define VERSAL_UART_CLOCK      212000
105 # define VERSAL_UART_BAUDRATE   9600
106 # define VERSAL_CPU_CLOCK       212000
107 #endif
108 
109 /* Access control register defines */
110 #define ACTLR_EL3_L2ACTLR_BIT	(1 << 6)
111 #define ACTLR_EL3_CPUACTLR_BIT	(1 << 0)
112 
113 /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/
114 #define CRF_BASE		0xFD1A0000
115 #define CRF_SIZE		0x00600000
116 
117 /* CRF registers and bitfields */
118 #define CRF_RST_APU	(CRF_BASE + 0X00000300)
119 
120 #define CRF_RST_APU_ACPU_RESET		(1 << 0)
121 #define CRF_RST_APU_ACPU_PWRON_RESET	(1 << 10)
122 
123 #define FPD_MAINCCI_BASE	0xFD000000
124 #define FPD_MAINCCI_SIZE	0x00100000
125 
126 /* APU registers and bitfields */
127 #define FPD_APU_BASE		0xFD5C0000U
128 #define FPD_APU_CONFIG_0	(FPD_APU_BASE + 0x20U)
129 #define FPD_APU_RVBAR_L_0	(FPD_APU_BASE + 0x40U)
130 #define FPD_APU_RVBAR_H_0	(FPD_APU_BASE + 0x44U)
131 #define FPD_APU_PWRCTL		(FPD_APU_BASE + 0x90U)
132 
133 #define FPD_APU_CONFIG_0_VINITHI_SHIFT	8U
134 #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK	1U
135 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK	2U
136 
137 /* PMC registers and bitfields */
138 #define PMC_GLOBAL_BASE			0xF1110000U
139 #define PMC_GLOBAL_GLOB_GEN_STORAGE4	(PMC_GLOBAL_BASE + 0x40U)
140 
141 /* IPI registers and bitfields */
142 #define IPI0_REG_BASE		U(0xFF330000)
143 #define IPI0_TRIG_BIT		(1U << 2U)
144 #define PMC_IPI_TRIG_BIT	(1U << 1U)
145 #define IPI1_REG_BASE		U(0xFF340000)
146 #define IPI1_TRIG_BIT		(1U << 3U)
147 #define IPI2_REG_BASE		U(0xFF350000)
148 #define IPI2_TRIG_BIT		(1U << 4U)
149 #define IPI3_REG_BASE		U(0xFF360000)
150 #define IPI3_TRIG_BIT		(1U << 5U)
151 #define IPI4_REG_BASE		U(0xFF370000)
152 #define IPI4_TRIG_BIT		(1U << 5U)
153 #define IPI5_REG_BASE		U(0xFF380000)
154 #define IPI5_TRIG_BIT		(1U << 6U)
155 
156 #endif /* VERSAL_DEF_H */
157