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Searched refs:TEGRA_FLOWCTRL_BASE (Results 1 – 3 of 3) sorted by relevance

/trusted-firmware-a-3.4.0/plat/nvidia/tegra/drivers/flowctrl/
Dflowctrl.c27 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU0_CSR),
28 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR),
29 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR + 8),
30 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR + 16)
34 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU0_EVENTS),
35 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS),
36 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS + 8),
37 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS + 16)
41 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL),
42 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 4),
[all …]
/trusted-firmware-a-3.4.0/plat/nvidia/tegra/include/drivers/
Dflowctrl.h75 return mmio_read_32(TEGRA_FLOWCTRL_BASE + off); in tegra_fc_read_32()
80 mmio_write_32(TEGRA_FLOWCTRL_BASE + off, val); in tegra_fc_write_32()
/trusted-firmware-a-3.4.0/plat/nvidia/tegra/include/t210/
Dtegra_def.h170 #define TEGRA_FLOWCTRL_BASE U(0x60007000) macro