1 /*
2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef STM32MP1_DEF_H
8 #define STM32MP1_DEF_H
9
10 #include <common/tbbr/tbbr_img_def.h>
11 #include <drivers/st/stm32mp1_rcc.h>
12 #include <dt-bindings/clock/stm32mp1-clks.h>
13 #include <dt-bindings/reset/stm32mp1-resets.h>
14 #include <lib/utils_def.h>
15 #include <lib/xlat_tables/xlat_tables_defs.h>
16
17 #ifndef __ASSEMBLER__
18 #include <drivers/st/bsec.h>
19 #include <drivers/st/stm32mp1_clk.h>
20
21 #include <boot_api.h>
22 #include <stm32mp_auth.h>
23 #include <stm32mp_common.h>
24 #include <stm32mp_dt.h>
25 #include <stm32mp1_dbgmcu.h>
26 #include <stm32mp1_private.h>
27 #include <stm32mp1_shared_resources.h>
28 #endif
29
30 #if !STM32MP_USE_STM32IMAGE
31 #include "stm32mp1_fip_def.h"
32 #else /* STM32MP_USE_STM32IMAGE */
33 #include "stm32mp1_stm32image_def.h"
34 #endif /* STM32MP_USE_STM32IMAGE */
35
36 /*******************************************************************************
37 * CHIP ID
38 ******************************************************************************/
39 #if STM32MP13
40 #define STM32MP1_CHIP_ID U(0x501)
41
42 #define STM32MP135C_PART_NB U(0x05010000)
43 #define STM32MP135A_PART_NB U(0x05010001)
44 #define STM32MP133C_PART_NB U(0x050100C0)
45 #define STM32MP133A_PART_NB U(0x050100C1)
46 #define STM32MP131C_PART_NB U(0x050106C8)
47 #define STM32MP131A_PART_NB U(0x050106C9)
48 #define STM32MP135F_PART_NB U(0x05010800)
49 #define STM32MP135D_PART_NB U(0x05010801)
50 #define STM32MP133F_PART_NB U(0x050108C0)
51 #define STM32MP133D_PART_NB U(0x050108C1)
52 #define STM32MP131F_PART_NB U(0x05010EC8)
53 #define STM32MP131D_PART_NB U(0x05010EC9)
54 #endif
55 #if STM32MP15
56 #define STM32MP1_CHIP_ID U(0x500)
57
58 #define STM32MP157C_PART_NB U(0x05000000)
59 #define STM32MP157A_PART_NB U(0x05000001)
60 #define STM32MP153C_PART_NB U(0x05000024)
61 #define STM32MP153A_PART_NB U(0x05000025)
62 #define STM32MP151C_PART_NB U(0x0500002E)
63 #define STM32MP151A_PART_NB U(0x0500002F)
64 #define STM32MP157F_PART_NB U(0x05000080)
65 #define STM32MP157D_PART_NB U(0x05000081)
66 #define STM32MP153F_PART_NB U(0x050000A4)
67 #define STM32MP153D_PART_NB U(0x050000A5)
68 #define STM32MP151F_PART_NB U(0x050000AE)
69 #define STM32MP151D_PART_NB U(0x050000AF)
70 #endif
71
72 #define STM32MP1_REV_B U(0x2000)
73 #if STM32MP13
74 #define STM32MP1_REV_Z U(0x1001)
75 #endif
76 #if STM32MP15
77 #define STM32MP1_REV_Z U(0x2001)
78 #endif
79
80 /*******************************************************************************
81 * PACKAGE ID
82 ******************************************************************************/
83 #if STM32MP15
84 #define PKG_AA_LFBGA448 U(4)
85 #define PKG_AB_LFBGA354 U(3)
86 #define PKG_AC_TFBGA361 U(2)
87 #define PKG_AD_TFBGA257 U(1)
88 #endif
89
90 /*******************************************************************************
91 * STM32MP1 memory map related constants
92 ******************************************************************************/
93 #define STM32MP_ROM_BASE U(0x00000000)
94 #define STM32MP_ROM_SIZE U(0x00020000)
95 #define STM32MP_ROM_SIZE_2MB_ALIGNED U(0x00200000)
96
97 #if STM32MP13
98 #define STM32MP_SYSRAM_BASE U(0x2FFE0000)
99 #define STM32MP_SYSRAM_SIZE U(0x00020000)
100 #define SRAM1_BASE U(0x30000000)
101 #define SRAM1_SIZE U(0x00004000)
102 #define SRAM2_BASE U(0x30004000)
103 #define SRAM2_SIZE U(0x00002000)
104 #define SRAM3_BASE U(0x30006000)
105 #define SRAM3_SIZE U(0x00002000)
106 #define SRAMS_BASE SRAM1_BASE
107 #define SRAMS_SIZE_2MB_ALIGNED U(0x00200000)
108 #endif /* STM32MP13 */
109 #if STM32MP15
110 #define STM32MP_SYSRAM_BASE U(0x2FFC0000)
111 #define STM32MP_SYSRAM_SIZE U(0x00040000)
112 #endif /* STM32MP15 */
113
114 #define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE
115 #define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \
116 STM32MP_SYSRAM_SIZE - \
117 STM32MP_NS_SYSRAM_SIZE)
118
119 #define STM32MP_SCMI_NS_SHM_BASE STM32MP_NS_SYSRAM_BASE
120 #define STM32MP_SCMI_NS_SHM_SIZE STM32MP_NS_SYSRAM_SIZE
121
122 #define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE
123 #define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \
124 STM32MP_NS_SYSRAM_SIZE)
125
126 /* DDR configuration */
127 #define STM32MP_DDR_BASE U(0xC0000000)
128 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
129
130 /* DDR power initializations */
131 #ifndef __ASSEMBLER__
132 enum ddr_type {
133 STM32MP_DDR3,
134 STM32MP_LPDDR2,
135 STM32MP_LPDDR3
136 };
137 #endif
138
139 /* Section used inside TF binaries */
140 #if STM32MP13
141 /* 512 Octets reserved for header */
142 #define STM32MP_HEADER_RESERVED_SIZE U(0x200)
143
144 #define STM32MP_BINARY_BASE STM32MP_SEC_SYSRAM_BASE
145
146 #define STM32MP_BINARY_SIZE STM32MP_SEC_SYSRAM_SIZE
147 #endif
148 #if STM32MP15
149 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
150 /* 256 Octets reserved for header */
151 #define STM32MP_HEADER_SIZE U(0x00000100)
152 /* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */
153 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000)
154
155 #define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \
156 STM32MP_PARAM_LOAD_SIZE + \
157 STM32MP_HEADER_SIZE)
158
159 #define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
160 (STM32MP_PARAM_LOAD_SIZE + \
161 STM32MP_HEADER_SIZE))
162 #endif
163
164 /* BL2 and BL32/sp_min require finer granularity tables */
165 #if defined(IMAGE_BL2)
166 #define MAX_XLAT_TABLES U(2) /* 8 KB for mapping */
167 #endif
168
169 #if defined(IMAGE_BL32)
170 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
171 #endif
172
173 /*
174 * MAX_MMAP_REGIONS is usually:
175 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
176 */
177 #if defined(IMAGE_BL2)
178 #if STM32MP_USB_PROGRAMMER
179 #define MAX_MMAP_REGIONS 8
180 #else
181 #define MAX_MMAP_REGIONS 7
182 #endif
183 #endif
184
185 #if STM32MP13
186 #define STM32MP_BL33_BASE STM32MP_DDR_BASE
187 #endif
188 #if STM32MP15
189 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
190 #endif
191 #define STM32MP_BL33_MAX_SIZE U(0x400000)
192
193 /* Define maximum page size for NAND devices */
194 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000)
195
196 /*******************************************************************************
197 * STM32MP1 device/io map related constants (used for MMU)
198 ******************************************************************************/
199 #define STM32MP1_DEVICE1_BASE U(0x40000000)
200 #define STM32MP1_DEVICE1_SIZE U(0x40000000)
201
202 #define STM32MP1_DEVICE2_BASE U(0x80000000)
203 #define STM32MP1_DEVICE2_SIZE U(0x40000000)
204
205 /*******************************************************************************
206 * STM32MP1 RCC
207 ******************************************************************************/
208 #define RCC_BASE U(0x50000000)
209
210 /*******************************************************************************
211 * STM32MP1 PWR
212 ******************************************************************************/
213 #define PWR_BASE U(0x50001000)
214
215 /*******************************************************************************
216 * STM32MP1 GPIO
217 ******************************************************************************/
218 #define GPIOA_BASE U(0x50002000)
219 #define GPIOB_BASE U(0x50003000)
220 #define GPIOC_BASE U(0x50004000)
221 #define GPIOD_BASE U(0x50005000)
222 #define GPIOE_BASE U(0x50006000)
223 #define GPIOF_BASE U(0x50007000)
224 #define GPIOG_BASE U(0x50008000)
225 #define GPIOH_BASE U(0x50009000)
226 #define GPIOI_BASE U(0x5000A000)
227 #if STM32MP15
228 #define GPIOJ_BASE U(0x5000B000)
229 #define GPIOK_BASE U(0x5000C000)
230 #define GPIOZ_BASE U(0x54004000)
231 #endif
232 #define GPIO_BANK_OFFSET U(0x1000)
233
234 /* Bank IDs used in GPIO driver API */
235 #define GPIO_BANK_A U(0)
236 #define GPIO_BANK_B U(1)
237 #define GPIO_BANK_C U(2)
238 #define GPIO_BANK_D U(3)
239 #define GPIO_BANK_E U(4)
240 #define GPIO_BANK_F U(5)
241 #define GPIO_BANK_G U(6)
242 #define GPIO_BANK_H U(7)
243 #define GPIO_BANK_I U(8)
244 #if STM32MP15
245 #define GPIO_BANK_J U(9)
246 #define GPIO_BANK_K U(10)
247 #define GPIO_BANK_Z U(25)
248
249 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8
250 #endif
251
252 /*******************************************************************************
253 * STM32MP1 UART
254 ******************************************************************************/
255 #if STM32MP13
256 #define USART1_BASE U(0x4C000000)
257 #define USART2_BASE U(0x4C001000)
258 #endif
259 #if STM32MP15
260 #define USART1_BASE U(0x5C000000)
261 #define USART2_BASE U(0x4000E000)
262 #endif
263 #define USART3_BASE U(0x4000F000)
264 #define UART4_BASE U(0x40010000)
265 #define UART5_BASE U(0x40011000)
266 #define USART6_BASE U(0x44003000)
267 #define UART7_BASE U(0x40018000)
268 #define UART8_BASE U(0x40019000)
269
270 /* For UART crash console */
271 #define STM32MP_DEBUG_USART_BASE UART4_BASE
272 #if STM32MP13
273 /* UART4 on HSI@64MHz, TX on GPIOF12 Alternate 8 (Disco board) */
274 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000
275 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOD_BASE
276 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_S_AHB4ENSETR
277 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_S_AHB4ENSETR_GPIODEN
278 #define DEBUG_UART_TX_GPIO_PORT 6
279 #define DEBUG_UART_TX_GPIO_ALTERNATE 8
280 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART4CKSELR
281 #define DEBUG_UART_TX_CLKSRC RCC_UART4CKSELR_HSI
282 #endif /* STM32MP13 */
283 #if STM32MP15
284 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */
285 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000
286 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE
287 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR
288 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN
289 #define DEBUG_UART_TX_GPIO_PORT 11
290 #define DEBUG_UART_TX_GPIO_ALTERNATE 6
291 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR
292 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI
293 #endif /* STM32MP15 */
294 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR
295 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN
296 #define DEBUG_UART_RST_REG RCC_APB1RSTSETR
297 #define DEBUG_UART_RST_BIT RCC_APB1RSTSETR_UART4RST
298
299 /*******************************************************************************
300 * STM32MP1 ETZPC
301 ******************************************************************************/
302 #define STM32MP1_ETZPC_BASE U(0x5C007000)
303
304 /* ETZPC TZMA IDs */
305 #define STM32MP1_ETZPC_TZMA_ROM U(0)
306 #define STM32MP1_ETZPC_TZMA_SYSRAM U(1)
307
308 #define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0)
309
310 /* ETZPC DECPROT IDs */
311 #define STM32MP1_ETZPC_STGENC_ID 0
312 #define STM32MP1_ETZPC_BKPSRAM_ID 1
313 #define STM32MP1_ETZPC_IWDG1_ID 2
314 #define STM32MP1_ETZPC_USART1_ID 3
315 #define STM32MP1_ETZPC_SPI6_ID 4
316 #define STM32MP1_ETZPC_I2C4_ID 5
317 #define STM32MP1_ETZPC_RNG1_ID 7
318 #define STM32MP1_ETZPC_HASH1_ID 8
319 #define STM32MP1_ETZPC_CRYP1_ID 9
320 #define STM32MP1_ETZPC_DDRCTRL_ID 10
321 #define STM32MP1_ETZPC_DDRPHYC_ID 11
322 #define STM32MP1_ETZPC_I2C6_ID 12
323 #define STM32MP1_ETZPC_SEC_ID_LIMIT 13
324
325 #define STM32MP1_ETZPC_TIM2_ID 16
326 #define STM32MP1_ETZPC_TIM3_ID 17
327 #define STM32MP1_ETZPC_TIM4_ID 18
328 #define STM32MP1_ETZPC_TIM5_ID 19
329 #define STM32MP1_ETZPC_TIM6_ID 20
330 #define STM32MP1_ETZPC_TIM7_ID 21
331 #define STM32MP1_ETZPC_TIM12_ID 22
332 #define STM32MP1_ETZPC_TIM13_ID 23
333 #define STM32MP1_ETZPC_TIM14_ID 24
334 #define STM32MP1_ETZPC_LPTIM1_ID 25
335 #define STM32MP1_ETZPC_WWDG1_ID 26
336 #define STM32MP1_ETZPC_SPI2_ID 27
337 #define STM32MP1_ETZPC_SPI3_ID 28
338 #define STM32MP1_ETZPC_SPDIFRX_ID 29
339 #define STM32MP1_ETZPC_USART2_ID 30
340 #define STM32MP1_ETZPC_USART3_ID 31
341 #define STM32MP1_ETZPC_UART4_ID 32
342 #define STM32MP1_ETZPC_UART5_ID 33
343 #define STM32MP1_ETZPC_I2C1_ID 34
344 #define STM32MP1_ETZPC_I2C2_ID 35
345 #define STM32MP1_ETZPC_I2C3_ID 36
346 #define STM32MP1_ETZPC_I2C5_ID 37
347 #define STM32MP1_ETZPC_CEC_ID 38
348 #define STM32MP1_ETZPC_DAC_ID 39
349 #define STM32MP1_ETZPC_UART7_ID 40
350 #define STM32MP1_ETZPC_UART8_ID 41
351 #define STM32MP1_ETZPC_MDIOS_ID 44
352 #define STM32MP1_ETZPC_TIM1_ID 48
353 #define STM32MP1_ETZPC_TIM8_ID 49
354 #define STM32MP1_ETZPC_USART6_ID 51
355 #define STM32MP1_ETZPC_SPI1_ID 52
356 #define STM32MP1_ETZPC_SPI4_ID 53
357 #define STM32MP1_ETZPC_TIM15_ID 54
358 #define STM32MP1_ETZPC_TIM16_ID 55
359 #define STM32MP1_ETZPC_TIM17_ID 56
360 #define STM32MP1_ETZPC_SPI5_ID 57
361 #define STM32MP1_ETZPC_SAI1_ID 58
362 #define STM32MP1_ETZPC_SAI2_ID 59
363 #define STM32MP1_ETZPC_SAI3_ID 60
364 #define STM32MP1_ETZPC_DFSDM_ID 61
365 #define STM32MP1_ETZPC_TT_FDCAN_ID 62
366 #define STM32MP1_ETZPC_LPTIM2_ID 64
367 #define STM32MP1_ETZPC_LPTIM3_ID 65
368 #define STM32MP1_ETZPC_LPTIM4_ID 66
369 #define STM32MP1_ETZPC_LPTIM5_ID 67
370 #define STM32MP1_ETZPC_SAI4_ID 68
371 #define STM32MP1_ETZPC_VREFBUF_ID 69
372 #define STM32MP1_ETZPC_DCMI_ID 70
373 #define STM32MP1_ETZPC_CRC2_ID 71
374 #define STM32MP1_ETZPC_ADC_ID 72
375 #define STM32MP1_ETZPC_HASH2_ID 73
376 #define STM32MP1_ETZPC_RNG2_ID 74
377 #define STM32MP1_ETZPC_CRYP2_ID 75
378 #define STM32MP1_ETZPC_SRAM1_ID 80
379 #define STM32MP1_ETZPC_SRAM2_ID 81
380 #define STM32MP1_ETZPC_SRAM3_ID 82
381 #define STM32MP1_ETZPC_SRAM4_ID 83
382 #define STM32MP1_ETZPC_RETRAM_ID 84
383 #define STM32MP1_ETZPC_OTG_ID 85
384 #define STM32MP1_ETZPC_SDMMC3_ID 86
385 #define STM32MP1_ETZPC_DLYBSD3_ID 87
386 #define STM32MP1_ETZPC_DMA1_ID 88
387 #define STM32MP1_ETZPC_DMA2_ID 89
388 #define STM32MP1_ETZPC_DMAMUX_ID 90
389 #define STM32MP1_ETZPC_FMC_ID 91
390 #define STM32MP1_ETZPC_QSPI_ID 92
391 #define STM32MP1_ETZPC_DLYBQ_ID 93
392 #define STM32MP1_ETZPC_ETH_ID 94
393 #define STM32MP1_ETZPC_RSV_ID 95
394
395 #define STM32MP_ETZPC_MAX_ID 96
396
397 /*******************************************************************************
398 * STM32MP1 TZC (TZ400)
399 ******************************************************************************/
400 #define STM32MP1_TZC_BASE U(0x5C006000)
401
402 #if STM32MP13
403 #define STM32MP1_FILTER_BIT_ALL TZC_400_REGION_ATTR_FILTER_BIT(0)
404 #endif
405 #if STM32MP15
406 #define STM32MP1_FILTER_BIT_ALL (TZC_400_REGION_ATTR_FILTER_BIT(0) | \
407 TZC_400_REGION_ATTR_FILTER_BIT(1))
408 #endif
409
410 /*******************************************************************************
411 * STM32MP1 SDMMC
412 ******************************************************************************/
413 #define STM32MP_SDMMC1_BASE U(0x58005000)
414 #define STM32MP_SDMMC2_BASE U(0x58007000)
415 #define STM32MP_SDMMC3_BASE U(0x48004000)
416
417 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/
418 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/
419 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/
420 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/
421 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/
422
423 /*******************************************************************************
424 * STM32MP1 BSEC / OTP
425 ******************************************************************************/
426 #define STM32MP1_OTP_MAX_ID 0x5FU
427 #define STM32MP1_UPPER_OTP_START 0x20U
428
429 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U)
430
431 /* OTP labels */
432 #define CFG0_OTP "cfg0_otp"
433 #define PART_NUMBER_OTP "part_number_otp"
434 #if STM32MP15
435 #define PACKAGE_OTP "package_otp"
436 #endif
437 #define HW2_OTP "hw2_otp"
438 #define NAND_OTP "nand_otp"
439 #define MONOTONIC_OTP "monotonic_otp"
440 #define UID_OTP "uid_otp"
441 #define BOARD_ID_OTP "board_id"
442
443 /* OTP mask */
444 /* CFG0 */
445 #if STM32MP13
446 #define CFG0_OTP_MODE_MASK GENMASK_32(9, 0)
447 #define CFG0_OTP_MODE_SHIFT 0
448 #define CFG0_OPEN_DEVICE 0x17U
449 #define CFG0_CLOSED_DEVICE 0x3FU
450 #define CFG0_CLOSED_DEVICE_NO_BOUNDARY_SCAN 0x17FU
451 #define CFG0_CLOSED_DEVICE_NO_JTAG 0x3FFU
452 #endif
453 #if STM32MP15
454 #define CFG0_CLOSED_DEVICE BIT(6)
455 #endif
456
457 /* PART NUMBER */
458 #if STM32MP13
459 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(11, 0)
460 #endif
461 #if STM32MP15
462 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0)
463 #endif
464 #define PART_NUMBER_OTP_PART_SHIFT 0
465
466 /* PACKAGE */
467 #if STM32MP15
468 #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27)
469 #define PACKAGE_OTP_PKG_SHIFT 27
470 #endif
471
472 /* IWDG OTP */
473 #define HW2_OTP_IWDG_HW_POS U(3)
474 #define HW2_OTP_IWDG_FZ_STOP_POS U(5)
475 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7)
476
477 /* HW2 OTP */
478 #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13)
479
480 /* NAND OTP */
481 /* NAND parameter storage flag */
482 #define NAND_PARAM_STORED_IN_OTP BIT(31)
483
484 /* NAND page size in bytes */
485 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29)
486 #define NAND_PAGE_SIZE_SHIFT 29
487 #define NAND_PAGE_SIZE_2K U(0)
488 #define NAND_PAGE_SIZE_4K U(1)
489 #define NAND_PAGE_SIZE_8K U(2)
490
491 /* NAND block size in pages */
492 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27)
493 #define NAND_BLOCK_SIZE_SHIFT 27
494 #define NAND_BLOCK_SIZE_64_PAGES U(0)
495 #define NAND_BLOCK_SIZE_128_PAGES U(1)
496 #define NAND_BLOCK_SIZE_256_PAGES U(2)
497
498 /* NAND number of block (in unit of 256 blocs) */
499 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19)
500 #define NAND_BLOCK_NB_SHIFT 19
501 #define NAND_BLOCK_NB_UNIT U(256)
502
503 /* NAND bus width in bits */
504 #define NAND_WIDTH_MASK BIT(18)
505 #define NAND_WIDTH_SHIFT 18
506
507 /* NAND number of ECC bits per 512 bytes */
508 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15)
509 #define NAND_ECC_BIT_NB_SHIFT 15
510 #define NAND_ECC_BIT_NB_UNSET U(0)
511 #define NAND_ECC_BIT_NB_1_BITS U(1)
512 #define NAND_ECC_BIT_NB_4_BITS U(2)
513 #define NAND_ECC_BIT_NB_8_BITS U(3)
514 #define NAND_ECC_ON_DIE U(4)
515
516 /* NAND number of planes */
517 #define NAND_PLANE_BIT_NB_MASK BIT(14)
518
519 /* MONOTONIC OTP */
520 #define MAX_MONOTONIC_VALUE 32
521
522 /* UID OTP */
523 #define UID_WORD_NB U(3)
524
525 /* FWU configuration (max supported value is 15) */
526 #define FWU_MAX_TRIAL_REBOOT U(3)
527
528 /*******************************************************************************
529 * STM32MP1 TAMP
530 ******************************************************************************/
531 #define TAMP_BASE U(0x5C00A000)
532 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
533
534 #if !(defined(__LINKER__) || defined(__ASSEMBLER__))
tamp_bkpr(uint32_t idx)535 static inline uintptr_t tamp_bkpr(uint32_t idx)
536 {
537 return TAMP_BKP_REGISTER_BASE + (idx << 2);
538 }
539 #endif
540
541 /*******************************************************************************
542 * STM32MP1 USB
543 ******************************************************************************/
544 #define USB_OTG_BASE U(0x49000000)
545
546 /*******************************************************************************
547 * STM32MP1 DDRCTRL
548 ******************************************************************************/
549 #define DDRCTRL_BASE U(0x5A003000)
550
551 /*******************************************************************************
552 * STM32MP1 DDRPHYC
553 ******************************************************************************/
554 #define DDRPHYC_BASE U(0x5A004000)
555
556 /*******************************************************************************
557 * STM32MP1 IWDG
558 ******************************************************************************/
559 #define IWDG_MAX_INSTANCE U(2)
560 #define IWDG1_INST U(0)
561 #define IWDG2_INST U(1)
562
563 #define IWDG1_BASE U(0x5C003000)
564 #define IWDG2_BASE U(0x5A002000)
565
566 /*******************************************************************************
567 * Miscellaneous STM32MP1 peripherals base address
568 ******************************************************************************/
569 #define BSEC_BASE U(0x5C005000)
570 #if STM32MP13
571 #define CRYP_BASE U(0x54002000)
572 #endif
573 #if STM32MP15
574 #define CRYP1_BASE U(0x54001000)
575 #endif
576 #define DBGMCU_BASE U(0x50081000)
577 #if STM32MP13
578 #define HASH_BASE U(0x54003000)
579 #endif
580 #if STM32MP15
581 #define HASH1_BASE U(0x54002000)
582 #endif
583 #if STM32MP13
584 #define I2C3_BASE U(0x4C004000)
585 #define I2C4_BASE U(0x4C005000)
586 #define I2C5_BASE U(0x4C006000)
587 #endif
588 #if STM32MP15
589 #define I2C4_BASE U(0x5C002000)
590 #define I2C6_BASE U(0x5c009000)
591 #endif
592 #if STM32MP13
593 #define RNG_BASE U(0x54004000)
594 #endif
595 #if STM32MP15
596 #define RNG1_BASE U(0x54003000)
597 #endif
598 #define RTC_BASE U(0x5c004000)
599 #if STM32MP13
600 #define SPI4_BASE U(0x4C002000)
601 #define SPI5_BASE U(0x4C003000)
602 #endif
603 #if STM32MP15
604 #define SPI6_BASE U(0x5c001000)
605 #endif
606 #define STGEN_BASE U(0x5c008000)
607 #define SYSCFG_BASE U(0x50020000)
608
609 /*******************************************************************************
610 * STM32MP13 SAES
611 ******************************************************************************/
612 #define SAES_BASE U(0x54005000)
613
614 /*******************************************************************************
615 * STM32MP13 PKA
616 ******************************************************************************/
617 #define PKA_BASE U(0x54006000)
618
619 /*******************************************************************************
620 * REGULATORS
621 ******************************************************************************/
622 /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */
623 #define PLAT_NB_RDEVS U(19)
624 /* 2 FIXED */
625 #define PLAT_NB_FIXED_REGS U(2)
626
627 /*******************************************************************************
628 * Device Tree defines
629 ******************************************************************************/
630 #define DT_BSEC_COMPAT "st,stm32mp15-bsec"
631 #if STM32MP13
632 #define DT_DDR_COMPAT "st,stm32mp13-ddr"
633 #endif
634 #if STM32MP15
635 #define DT_DDR_COMPAT "st,stm32mp1-ddr"
636 #endif
637 #define DT_IWDG_COMPAT "st,stm32mp1-iwdg"
638 #define DT_PWR_COMPAT "st,stm32mp1,pwr-reg"
639 #if STM32MP13
640 #define DT_RCC_CLK_COMPAT "st,stm32mp13-rcc"
641 #define DT_RCC_SEC_CLK_COMPAT "st,stm32mp13-rcc-secure"
642 #endif
643 #if STM32MP15
644 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
645 #define DT_RCC_SEC_CLK_COMPAT "st,stm32mp1-rcc-secure"
646 #endif
647 #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2"
648
649 #endif /* STM32MP1_DEF_H */
650
