1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef GICV2_H 8 #define GICV2_H 9 10 #include <drivers/arm/gic_common.h> 11 #include <platform_def.h> 12 13 /******************************************************************************* 14 * GICv2 miscellaneous definitions 15 ******************************************************************************/ 16 17 /* Interrupt group definitions */ 18 #define GICV2_INTR_GROUP0 U(0) 19 #define GICV2_INTR_GROUP1 U(1) 20 21 /* Interrupt IDs reported by the HPPIR and IAR registers */ 22 #define PENDING_G1_INTID U(1022) 23 24 /* GICv2 can only target up to 8 PEs */ 25 #define GICV2_MAX_TARGET_PE U(8) 26 27 /******************************************************************************* 28 * GICv2 specific Distributor interface register offsets and constants. 29 ******************************************************************************/ 30 #define GICD_ITARGETSR U(0x800) 31 #define GICD_SGIR U(0xF00) 32 #define GICD_CPENDSGIR U(0xF10) 33 #define GICD_SPENDSGIR U(0xF20) 34 35 /* 36 * Some GICv2 implementations violate the specification and have this register 37 * at a different address. Allow overriding it in platform_def.h as workaround. 38 */ 39 #ifndef GICD_PIDR2_GICV2 40 #define GICD_PIDR2_GICV2 U(0xFE8) 41 #endif 42 43 #define ITARGETSR_SHIFT 2 44 #define GIC_TARGET_CPU_MASK U(0xff) 45 46 #define CPENDSGIR_SHIFT 2 47 #define SPENDSGIR_SHIFT CPENDSGIR_SHIFT 48 49 #define SGIR_TGTLSTFLT_SHIFT 24 50 #define SGIR_TGTLSTFLT_MASK U(0x3) 51 #define SGIR_TGTLST_SHIFT 16 52 #define SGIR_TGTLST_MASK U(0xff) 53 #define SGIR_INTID_MASK ULL(0xf) 54 55 #define SGIR_TGT_SPECIFIC U(0) 56 57 #define GICV2_SGIR_VALUE(tgt_lst_flt, tgt, intid) \ 58 ((((tgt_lst_flt) & SGIR_TGTLSTFLT_MASK) << SGIR_TGTLSTFLT_SHIFT) | \ 59 (((tgt) & SGIR_TGTLST_MASK) << SGIR_TGTLST_SHIFT) | \ 60 ((intid) & SGIR_INTID_MASK)) 61 62 /******************************************************************************* 63 * GICv2 specific CPU interface register offsets and constants. 64 ******************************************************************************/ 65 /* Physical CPU Interface registers */ 66 #define GICC_CTLR U(0x0) 67 #define GICC_PMR U(0x4) 68 #define GICC_BPR U(0x8) 69 #define GICC_IAR U(0xC) 70 #define GICC_EOIR U(0x10) 71 #define GICC_RPR U(0x14) 72 #define GICC_HPPIR U(0x18) 73 #define GICC_AHPPIR U(0x28) 74 #define GICC_IIDR U(0xFC) 75 #define GICC_DIR U(0x1000) 76 #define GICC_PRIODROP GICC_EOIR 77 78 /* GICC_CTLR bit definitions */ 79 #define EOI_MODE_NS BIT_32(10) 80 #define EOI_MODE_S BIT_32(9) 81 #define IRQ_BYP_DIS_GRP1 BIT_32(8) 82 #define FIQ_BYP_DIS_GRP1 BIT_32(7) 83 #define IRQ_BYP_DIS_GRP0 BIT_32(6) 84 #define FIQ_BYP_DIS_GRP0 BIT_32(5) 85 #define CBPR BIT_32(4) 86 #define FIQ_EN_SHIFT 3 87 #define FIQ_EN_BIT BIT_32(FIQ_EN_SHIFT) 88 #define ACK_CTL BIT_32(2) 89 90 /* GICC_IIDR bit masks and shifts */ 91 #define GICC_IIDR_PID_SHIFT 20 92 #define GICC_IIDR_ARCH_SHIFT 16 93 #define GICC_IIDR_REV_SHIFT 12 94 #define GICC_IIDR_IMP_SHIFT 0 95 96 #define GICC_IIDR_PID_MASK U(0xfff) 97 #define GICC_IIDR_ARCH_MASK U(0xf) 98 #define GICC_IIDR_REV_MASK U(0xf) 99 #define GICC_IIDR_IMP_MASK U(0xfff) 100 101 /* HYP view virtual CPU Interface registers */ 102 #define GICH_CTL U(0x0) 103 #define GICH_VTR U(0x4) 104 #define GICH_ELRSR0 U(0x30) 105 #define GICH_ELRSR1 U(0x34) 106 #define GICH_APR0 U(0xF0) 107 #define GICH_LR_BASE U(0x100) 108 109 /* Virtual CPU Interface registers */ 110 #define GICV_CTL U(0x0) 111 #define GICV_PRIMASK U(0x4) 112 #define GICV_BP U(0x8) 113 #define GICV_INTACK U(0xC) 114 #define GICV_EOI U(0x10) 115 #define GICV_RUNNINGPRI U(0x14) 116 #define GICV_HIGHESTPEND U(0x18) 117 #define GICV_DEACTIVATE U(0x1000) 118 119 /* GICD_CTLR bit definitions */ 120 #define CTLR_ENABLE_G1_SHIFT 1 121 #define CTLR_ENABLE_G1_MASK U(0x1) 122 #define CTLR_ENABLE_G1_BIT BIT_32(CTLR_ENABLE_G1_SHIFT) 123 124 /* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */ 125 #define INT_ID_MASK U(0x3ff) 126 127 #ifndef __ASSEMBLER__ 128 129 #include <cdefs.h> 130 #include <stdint.h> 131 132 #include <common/interrupt_props.h> 133 134 /******************************************************************************* 135 * This structure describes some of the implementation defined attributes of 136 * the GICv2 IP. It is used by the platform port to specify these attributes 137 * in order to initialize the GICv2 driver. The attributes are described 138 * below. 139 * 140 * The 'gicd_base' field contains the base address of the Distributor interface 141 * programmer's view. 142 * 143 * The 'gicc_base' field contains the base address of the CPU Interface 144 * programmer's view. 145 * 146 * The 'target_masks' is a pointer to an array containing 'target_masks_num' 147 * elements. The GIC driver will populate the array with per-PE target mask to 148 * use to when targeting interrupts. 149 * 150 * The 'interrupt_props' field is a pointer to an array that enumerates secure 151 * interrupts and their properties. If this field is not NULL, both 152 * 'g0_interrupt_array' and 'g1s_interrupt_array' fields are ignored. 153 * 154 * The 'interrupt_props_num' field contains the number of entries in the 155 * 'interrupt_props' array. If this field is non-zero, 'g0_interrupt_num' is 156 * ignored. 157 ******************************************************************************/ 158 typedef struct gicv2_driver_data { 159 uintptr_t gicd_base; 160 uintptr_t gicc_base; 161 unsigned int *target_masks; 162 unsigned int target_masks_num; 163 const interrupt_prop_t *interrupt_props; 164 unsigned int interrupt_props_num; 165 } gicv2_driver_data_t; 166 167 /******************************************************************************* 168 * Function prototypes 169 ******************************************************************************/ 170 void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data); 171 void gicv2_distif_init(void); 172 void gicv2_pcpu_distif_init(void); 173 void gicv2_cpuif_enable(void); 174 void gicv2_cpuif_disable(void); 175 unsigned int gicv2_is_fiq_enabled(void); 176 unsigned int gicv2_get_pending_interrupt_type(void); 177 unsigned int gicv2_get_pending_interrupt_id(void); 178 unsigned int gicv2_acknowledge_interrupt(void); 179 void gicv2_end_of_interrupt(unsigned int id); 180 unsigned int gicv2_get_interrupt_group(unsigned int id); 181 unsigned int gicv2_get_running_priority(void); 182 void gicv2_set_pe_target_mask(unsigned int proc_num); 183 unsigned int gicv2_get_interrupt_active(unsigned int id); 184 void gicv2_enable_interrupt(unsigned int id); 185 void gicv2_disable_interrupt(unsigned int id); 186 void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority); 187 void gicv2_set_interrupt_type(unsigned int id, unsigned int type); 188 void gicv2_raise_sgi(int sgi_num, int proc_num); 189 void gicv2_set_spi_routing(unsigned int id, int proc_num); 190 void gicv2_set_interrupt_pending(unsigned int id); 191 void gicv2_clear_interrupt_pending(unsigned int id); 192 unsigned int gicv2_set_pmr(unsigned int mask); 193 void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg); 194 195 #endif /* __ASSEMBLER__ */ 196 #endif /* GICV2_H */ 197
