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/sof-3.4.0/src/platform/intel/cavs/include/cavs/lib/
Dpm_memory.h68 static inline void cavs_pm_memory_hp_sram_mask_set(uint32_t mask, int segment, in cavs_pm_memory_hp_sram_mask_set() argument
71 uint32_t expected = enabled ? 0 : mask; in cavs_pm_memory_hp_sram_mask_set()
75 io_reg_update_bits(SHIM_HSPGCTL(segment), mask, enabled ? 0 : mask); in cavs_pm_memory_hp_sram_mask_set()
76 io_reg_update_bits(SHIM_HSRMCTL(segment), mask, enabled ? 0 : mask); in cavs_pm_memory_hp_sram_mask_set()
82 while ((io_reg_read(SHIM_HSPGISTS(segment)) & mask) != expected) { in cavs_pm_memory_hp_sram_mask_set()
95 uint32_t mask; in cavs_pm_memory_hp_sram_banks_power_gate() local
103 mask = cavs_pm_memory_hp_sram_mask_get(start_bank_id, in cavs_pm_memory_hp_sram_banks_power_gate()
105 cavs_pm_memory_hp_sram_mask_set(mask, i, enabled); in cavs_pm_memory_hp_sram_banks_power_gate()
134 uint32_t mask = MASK(ending_bank_id, start_bank_id); in cavs_pm_memory_lp_sram_banks_power_gate() local
135 uint32_t expected = enabled ? 0 : mask; in cavs_pm_memory_lp_sram_banks_power_gate()
[all …]
Dasm_memory_management.h55 .macro m_cavs_hpsram_power_change segment_index, mask, ax, ay, az
58 s32i \mask, \ax, 0
63 bne \ax, \mask, 1b
/sof-3.4.0/src/arch/xtensa/xtos/
Dinterrupt-pri.h119 .macro indexmask_int index, mask, intptr, tmp
122 msindex_int \index, \mask // \index = index of msbit set in \mask (\tmp is tmp, \mask clobbered)
125 movi \mask, 0x80000000
127 srl \mask, \mask // \mask = single bit set corresponding to interrupt to be processed...
129 movi \mask, 1
131 sll \mask, \mask // \mask = single bit set corresponding to interrupt to be processed...
136 neg \index, \mask // find lsbit in \mask ...
137 and \mask, \index, \mask // ...
138 …msindex_int_nc \index, \mask, \tmp // \index = index of msbit set in \mask (\tmp is tmp, \mask not…
162 .macro index_int index, mask, intptr, tmp
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/sof-3.4.0/zephyr/include/sof/lib/
Dio.h13 #define io_reg_update_bits16(reg, mask, value) argument
16 #define io_reg_update_bits(reg, mask, value) argument
33 uint8_t mask, in io_reg_update_bits8() argument
36 io_reg_write8(reg, (io_reg_read8(reg) & (~mask)) | (value & mask)); in io_reg_update_bits8()
50 uint16_t mask, in io_reg_update_bits16() argument
53 io_reg_write16(reg, (io_reg_read16(reg) & (~mask)) | (value & mask)); in io_reg_update_bits16()
67 uint32_t mask, in io_reg_update_bits() argument
70 io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask)); in io_reg_update_bits()
/sof-3.4.0/xtos/include/sof/lib/
Dio.h18 static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, in io_reg_update_bits() argument
22 static inline void io_reg_update_bits16(uint32_t reg, uint16_t mask, in io_reg_update_bits16() argument
37 static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, in io_reg_update_bits() argument
40 io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask)); in io_reg_update_bits()
64 static inline void io_reg_update_bits16(uint32_t reg, uint16_t mask, in io_reg_update_bits16() argument
67 io_reg_write16(reg, (io_reg_read16(reg) & (~mask)) | (value & mask)); in io_reg_update_bits16()
80 static inline void io_reg_update_bits8(uint32_t reg, uint8_t mask, in io_reg_update_bits8() argument
83 io_reg_write8(reg, (io_reg_read8(reg) & (~mask)) | (value & mask)); in io_reg_update_bits8()
/sof-3.4.0/src/platform/intel/cavs/
Dplatform.c174 .mux_config = {.bit = 0, .mask = 3, .fn = 1},
177 .mux_config = {.bit = 2, .mask = 3, .fn = 1},
180 .mux_config = {.bit = 4, .mask = 3, .fn = 1},
183 .mux_config = {.bit = 6, .mask = 3, .fn = 1},
186 .mux_config = {.bit = 8, .mask = 3, .fn = 1},
189 .mux_config = {.bit = 10, .mask = 3, .fn = 1},
192 .mux_config = {.bit = 12, .mask = 3, .fn = 1},
195 .mux_config = {.bit = 14, .mask = 3, .fn = 1},
198 .mux_config = {.bit = 16, .mask = 1, .fn = 1},
201 .mux_config = {.bit = 11, .mask = 1, .fn = 1},
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/sof-3.4.0/tools/topology/topology1/m4/
Dbytecontrol.m454 dnl C_CONTROLBYTES(name, index, ops, base, num_regs, mask, max, tlv, priv)
66 ` # default base/num_regs/mask to avoid NULL STR'
69 ` ifelse($7, `', mask STR(XX), mask STR($7)`')'
82 dnl C_CONTROLBYTES_READONLY(name, index, ops, base, num_regs, mask, max, tlv, priv)
94 ` # default base/num_regs/mask to avoid NULL STR'
97 ` ifelse($7, `', mask STR(XX), mask STR($7)`')'
110 dnl C_CONTROLBYTES_VOLATILE_READONLY(name, index, ops, base, num_regs, mask, max, tlv, priv)
124 ` ifelse($7, `', mask STR(XX), mask STR($7)`')'
138 dnl C_CONTROLBYTES_WRITEONLY(name, index, ops, base, num_regs, mask, max, tlv, priv)
152 ` ifelse($7, `', mask STR(XX), mask STR($7)`')'
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/sof-3.4.0/src/arch/xtensa/hal/
Dinterrupts.c451 unsigned xthal_int_enable(unsigned mask) in xthal_int_enable() argument
460 syncmask = (mask & Xthal_tram_pending & Xthal_tram_sync); in xthal_int_enable()
463 mask &= ~syncmask; in xthal_int_enable()
478 Xthal_vpri_enabled |= mask; in xthal_int_enable()
497 unsigned xthal_int_disable(unsigned mask) in xthal_int_disable() argument
504 Xthal_vpri_enabled &= ~mask; in xthal_int_disable()
505 Xthal_tram_enabled &= ~mask; in xthal_int_disable()
559 unsigned mask, maskoff, basepri, prevpri, intlevel, *maskp, i; in xthal_set_int_vpri() local
581 mask = 1L << intnum; in xthal_set_int_vpri()
595 Xthal_vpri_enablemap[0][basepri++] |= mask; in xthal_set_int_vpri()
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/sof-3.4.0/src/drivers/imx/
Dinterrupt-irqsteer.c116 static inline void irqstr_update_bits(uint32_t reg, uint32_t mask, in irqstr_update_bits() argument
119 io_reg_update_bits(IRQSTR_BASE_ADDR + reg, mask, value); in irqstr_update_bits()
165 uint32_t mask; in irqstr_mask_int() local
172 mask = IRQSTR_INT_MASK(irq); in irqstr_mask_int()
173 irqstr_update_bits(IRQSTR_CH_MASK(IRQSTR_INT_REG(irq)), mask, 0); in irqstr_mask_int()
179 uint32_t mask; in irqstr_unmask_int() local
186 mask = IRQSTR_INT_MASK(irq); in irqstr_unmask_int()
187 irqstr_update_bits(IRQSTR_CH_MASK(IRQSTR_INT_REG(irq)), mask, mask); in irqstr_unmask_int()
397 .mask = irq_mask,
460 void platform_interrupt_clear(uint32_t irq, uint32_t mask) in platform_interrupt_clear() argument
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Desai.c53 uint32_t xcr = 0, xccr = 0, mask; in esai_set_config() local
155 mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP | in esai_set_config()
161 dai_update_bits(dai, REG_ESAI_TCCR, mask, xccr); in esai_set_config()
167 dai_update_bits(dai, REG_ESAI_RCCR, mask, xccr); in esai_set_config()
169 mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR | ESAI_xCR_xWA | in esai_set_config()
175 dai_update_bits(dai, REG_ESAI_TCR, mask, xcr); in esai_set_config()
177 mask &= ~ESAI_xCR_PADC; in esai_set_config()
178 dai_update_bits(dai, REG_ESAI_RCR, mask, xcr); in esai_set_config()
/sof-3.4.0/src/arch/xtensa/include/arch/drivers/
Dinterrupt.h33 #define arch_interrupt_enable_mask(mask) \ argument
34 _xtos_ints_on(mask)
37 #define arch_interrupt_disable_mask(mask) \ argument
38 _xtos_ints_off(mask)
/sof-3.4.0/src/drivers/amd/rembrandt/
Dinterrupt.c44 static inline void acp_irq_update_bits(uint32_t reg, uint32_t mask, in acp_irq_update_bits() argument
47 io_reg_update_bits(PU_REGISTER_BASE + reg, mask, value); in acp_irq_update_bits()
69 uint32_t mask; in acp_irq_mask_int() local
75 mask = IRQ_INT_MASK(irq); in acp_irq_mask_int()
77 acp_irq_update_bits(ACP_DSP0_INTR_CNTL1, mask, 0); in acp_irq_mask_int()
79 acp_irq_update_bits(ACP_DSP0_INTR_CNTL, mask, 0); in acp_irq_mask_int()
84 uint32_t mask; in acp_irq_unmask_int() local
90 mask = IRQ_INT_MASK(irq); in acp_irq_unmask_int()
92 acp_irq_update_bits(ACP_DSP0_INTR_CNTL1, mask, mask); in acp_irq_unmask_int()
94 acp_irq_update_bits(ACP_DSP0_INTR_CNTL, mask, mask); in acp_irq_unmask_int()
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/sof-3.4.0/src/arch/xtensa/include/xtensa/
Dxtbsp.h225 extern void xtbsp_uart_int_enable(const xtbsp_uart_int mask);
230 extern void xtbsp_uart_int_disable(const xtbsp_uart_int mask);
239 extern int xtbsp_uart_int_number(const xtbsp_uart_int mask);
Dxtruntime.h155 extern unsigned int _xtos_ints_off( unsigned int mask );
156 extern unsigned int _xtos_ints_on( unsigned int mask );
202 extern void _xtos_clear_ints( unsigned int mask );
/sof-3.4.0/src/drivers/amd/renoir/
Dinterrupt.c45 static inline void acp_irq_update_bits(uint32_t reg, uint32_t mask, in acp_irq_update_bits() argument
48 io_reg_update_bits(PU_REGISTER_BASE + reg, mask, value); in acp_irq_update_bits()
61 uint32_t mask; in acp_irq_mask_int() local
67 mask = IRQ_INT_MASK(irq); in acp_irq_mask_int()
68 acp_irq_update_bits(ACP_DSP0_INTR_CNTL, mask, 0); in acp_irq_mask_int()
73 uint32_t mask; in acp_irq_unmask_int() local
79 mask = IRQ_INT_MASK(irq); in acp_irq_unmask_int()
80 acp_irq_update_bits(ACP_DSP0_INTR_CNTL, mask, mask); in acp_irq_unmask_int()
168 .mask = acp_irq_mask,
223 void platform_interrupt_clear(uint32_t irq, uint32_t mask) in platform_interrupt_clear() argument
/sof-3.4.0/src/lib/
Dwait.c33 int poll_for_register_delay(uint32_t reg, uint32_t mask, in poll_for_register_delay() argument
50 while ((io_reg_read(reg) & mask) != val) { in poll_for_register_delay()
53 reg, mask, val, (uint32_t)us); in poll_for_register_delay()
/sof-3.4.0/src/include/sof/audio/
Dmux.h62 uint8_t mask[PLATFORM_MAX_CHANNELS]; member
197 uint32_t offset, uint8_t mask);
201 uint32_t offset, uint8_t mask);
205 uint32_t offset, uint8_t mask);
/sof-3.4.0/zephyr/
Dwrapper.c117 void platform_interrupt_clear(uint32_t irq, uint32_t mask) in platform_interrupt_clear() argument
162 unsigned int _xtos_ints_off(unsigned int mask) in _xtos_ints_off() argument
286 int poll_for_register_delay(uint32_t reg, uint32_t mask, in poll_for_register_delay() argument
303 while ((io_reg_read(reg) & mask) != val) { in poll_for_register_delay()
306 reg, mask, val, (uint32_t)us); in poll_for_register_delay()
/sof-3.4.0/src/arch/host/include/arch/drivers/
Dinterrupt.h21 static inline uint32_t arch_interrupt_enable_mask(uint32_t mask) {return 0; } in arch_interrupt_enable_mask() argument
22 static inline uint32_t arch_interrupt_disable_mask(uint32_t mask) {return 0; } in arch_interrupt_disable_mask() argument
/sof-3.4.0/xtos/include/rtos/
Dinterrupt.h51 void (*mask)(struct irq_desc *desc, uint32_t irq, member
146 void platform_interrupt_clear(uint32_t irq, uint32_t mask);
168 static inline void interrupt_clear_mask(int irq, uint32_t mask) in interrupt_clear_mask() argument
170 platform_interrupt_clear(irq, mask); in interrupt_clear_mask()
/sof-3.4.0/test/cmocka/src/audio/mux/
Ddemux_copy.c31 uint8_t mask[MUX_MAX_STREAMS][PLATFORM_MAX_CHANNELS]; member
118 mux->streams[i].mask[j] = td->mask[i][j]; in create_demux_comp_ipc()
209 if (td->mask[i][j] & BIT(k)) in test_demux_copy_proc_16()
234 if (td->mask[i][j] & BIT(k)) in test_demux_copy_proc_24()
259 if (td->mask[i][j] & BIT(k)) in test_demux_copy_proc_32()
296 memcpy_s(td->mask, sizeof(td->mask), in main()
Dmux_copy.c31 uint8_t mask[MUX_MAX_STREAMS][PLATFORM_MAX_CHANNELS]; member
136 mux->streams[i].mask[j] = td->mask[i][j]; in create_mux_comp_ipc()
230 if (td->mask[j][k] & BIT(i)) in test_mux_copy_proc_16()
254 if (td->mask[j][k] & BIT(i)) in test_mux_copy_proc_24()
278 if (td->mask[j][k] & BIT(i)) in test_mux_copy_proc_32()
314 memcpy_s(td->mask, sizeof(td->mask), in main()
/sof-3.4.0/zephyr/lib/
Dcpu.c148 int mask = 0; in cpu_enabled_cores() local
152 mask |= BIT(i); in cpu_enabled_cores()
154 return mask; in cpu_enabled_cores()
/sof-3.4.0/src/drivers/mediatek/mt818x/
Dinterrupt.c161 .mask = mtk_irq_mask,
198 void platform_interrupt_clear(uint32_t irq, uint32_t mask) in platform_interrupt_clear() argument
213 if (cascade && cascade->ops->mask) in interrupt_mask()
214 cascade->ops->mask(&cascade->desc, irq - cascade->irq_base, in interrupt_mask()
/sof-3.4.0/src/audio/mux/
Dmux.c76 if (cfg->streams[i].mask[k] & (1 << j)) { in mux_mix_check()
91 if (cfg->streams[k].mask[i] & (1 << j)) { in mux_mix_check()
136 if (popcount(cfg->streams[i].mask[j]) > 1) { in mux_set_values()
151 cd->config.streams[i].mask[j] = cfg->streams[i].mask[j]; in mux_set_values()
177 int mask = 1; in build_config() local
185 memset(cd->config.streams[i].mask, 0, sizeof(cd->config.streams[i].mask)); in build_config()
189 cd->config.streams[0].mask[i] = mask; in build_config()
190 mask <<= 1; in build_config()
194 cd->config.streams[1].mask[i] = mask; in build_config()
195 mask <<= 1; in build_config()

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