/Zephyr-latest/drivers/i2s/ |
D | i2s_litex.h | 37 #define I2S_RX_FIFO_DEPTH DT_PROP(DT_NODELABEL(i2s_rx), fifo_depth) 45 #define I2S_TX_FIFO_DEPTH DT_PROP(DT_NODELABEL(i2s_tx), fifo_depth) 98 uint16_t fifo_depth; member
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D | i2s_litex.c | 369 (cfg->fifo_depth * (i2s_cfg->word_size / 8)) / channel_div; in i2s_litex_configure() 618 .fifo_depth = DT_PROP(DT_NODELABEL(i2s_##dir), fifo_depth), \
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/Zephyr-latest/drivers/i2c/ |
D | i2c_cdns.c | 157 uint32_t fifo_depth; member 453 return (hold_wrkaround && (i2c_bus->curr_recv_count == (i2c_bus->fifo_depth + 1U))); in cdns_is_fifo_hold_quirk() 497 transfer_size = i2c_bus->recv_count - i2c_bus->fifo_depth; in cdns_i2c_master_handle_receive_interrupt() 507 (i2c_bus->curr_recv_count - i2c_bus->fifo_depth)) { in cdns_i2c_master_handle_receive_interrupt() 512 i2c_bus->curr_recv_count = xfer_size + i2c_bus->fifo_depth; in cdns_i2c_master_handle_receive_interrupt() 546 avail_bytes = i2c_bus->fifo_depth - cdns_i2c_readreg(i2c_bus, in cdns_i2c_master_handle_transmit_interrupt() 644 if (i2c_bus->recv_count > i2c_bus->fifo_depth) { in cdns_i2c_mrecv() 664 if ((i2c_bus->bus_hold_flag == 0U) && (i2c_bus->recv_count <= i2c_bus->fifo_depth)) { in cdns_i2c_mrecv() 716 if (i2c_bus->send_count > i2c_bus->fifo_depth) { in cdns_i2c_msend() 726 avail_bytes = i2c_bus->fifo_depth - cdns_i2c_readreg(i2c_bus, CDNS_I2C_XFER_SIZE_OFFSET); in cdns_i2c_msend() [all …]
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D | i2c_andes_atciic100.c | 60 dev_data->fifo_depth = 2; in i2c_atciic100_default_control() 63 dev_data->fifo_depth = 4; in i2c_atciic100_default_control() 66 dev_data->fifo_depth = 8; in i2c_atciic100_default_control() 69 dev_data->fifo_depth = 16; in i2c_atciic100_default_control() 438 if (write_fifo_count >= dev_data->fifo_depth) { in i2c_controller_fifo_write() 439 write_fifo_count = dev_data->fifo_depth; in i2c_controller_fifo_write() 472 if (read_fifo_count >= dev_data->fifo_depth) { in i2c_controller_fifo_read() 473 read_fifo_count = dev_data->fifo_depth; in i2c_controller_fifo_read()
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D | i2c_andes_atciic100.h | 230 uint32_t fifo_depth; member
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D | i2c_dw.c | 89 void i2c_dw_set_fifo_th(const struct device *dev, uint8_t fifo_depth) in i2c_dw_set_fifo_th() argument 93 write_tdlr(fifo_depth, reg_base); in i2c_dw_set_fifo_th() 94 write_rdlr(fifo_depth - 1, reg_base); in i2c_dw_set_fifo_th()
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/Zephyr-latest/drivers/dai/nxp/micfil/ |
D | micfil.c | 129 global_config.fifoWatermark = micfil_cfg->rx_props->fifo_depth - 1; in dai_nxp_micfil_set_config() 194 .fifo_depth = DT_INST_PROP(inst, fifo_depth), \
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/Zephyr-latest/drivers/serial/ |
D | uart_renesas_ra_sci.c | 91 if (IS_ENABLED(CONFIG_UART_RA_SCI_UART_FIFO_ENABLE) && data->sci.fifo_depth > 0 in uart_ra_sci_poll_in() 99 *c = IS_ENABLED(CONFIG_UART_RA_SCI_UART_FIFO_ENABLE) && data->sci.fifo_depth > 0 in uart_ra_sci_poll_in() 112 if (data->sci.fifo_depth > 0) { in uart_ra_sci_poll_out() 132 if (data->sci.fifo_depth > 0) { in uart_ra_sci_err_check() 306 if (data->sci.fifo_depth != 0) { in uart_ra_sci_fifo_fill() 307 while ((size - num_tx > 0) && cfg->regs->FDR_b.T < data->sci.fifo_depth) { in uart_ra_sci_fifo_fill() 331 if (data->sci.fifo_depth != 0) { in uart_ra_sci_fifo_read() 355 if (data->sci.fifo_depth != 0) { in uart_ra_sci_irq_tx_enable() 380 if (data->sci.fifo_depth != 0) { in uart_ra_sci_irq_tx_ready() 405 if (data->sci.fifo_depth != 0) { in uart_ra_sci_irq_rx_enable() [all …]
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D | uart_renesas_ra8_sci_b.c | 261 if (IS_ENABLED(CONFIG_UART_RA_SCI_B_UART_FIFO_ENABLE) && data->sci.fifo_depth > 0) { in uart_ra_sci_b_fifo_fill() 286 if (IS_ENABLED(CONFIG_UART_RA_SCI_B_UART_FIFO_ENABLE) && data->sci.fifo_depth > 0) { in uart_ra_sci_b_fifo_read()
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/Zephyr-latest/drivers/spi/ |
D | spi_dw.c | 96 f_tx = info->fifo_depth - read_txflr(dev) - in push_data() 102 f_tx = info->fifo_depth - read_txflr(dev); in push_data() 175 if (!spi->ctx.rx_len && spi->ctx.tx_len < info->fifo_depth) { in pull_data() 317 uint32_t dw_spi_txftlr_dflt = (info->fifo_depth * 1) / 2; in spi_dw_update_txftlr() 344 uint32_t dw_spi_rxftlr_dflt = (info->fifo_depth * 5) / 8; in transceive() 418 if (spi->ctx.rx_len && spi->ctx.rx_len < info->fifo_depth) { in transceive() 648 .fifo_depth = DT_INST_PROP(inst, fifo_depth), \
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D | spi_pw.c | 214 if (spi->ctx.rx_len && spi->ctx.rx_len < spi->fifo_depth) { in spi_pw_rx_thld_set() 415 fifo_len = spi->fifo_depth - in spi_pw_tx_data() 422 fifo_len = spi->fifo_depth - spi_pw_get_tx_fifo_level(dev); in spi_pw_tx_data() 493 if (!spi->ctx.rx_len && spi->ctx.tx_len < spi->fifo_depth) { in spi_pw_rx_data() 865 .fifo_depth = DT_INST_PROP(n, pw_fifo_depth), \ 887 .fifo_depth = DT_INST_PROP(n, pw_fifo_depth), \
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D | spi_pw.h | 221 uint8_t fifo_depth; member
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D | spi_dw.h | 36 uint8_t fifo_depth; member
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/Zephyr-latest/drivers/dai/intel/alh/ |
D | alh.c | 150 prop->fifo_depth = ALH_GPDMA_BURST_LENGTH; in dai_alh_get_properties() 217 .fifo_depth[DAI_DIR_PLAYBACK] = ALH_GPDMA_BURST_LENGTH, \ 218 .fifo_depth[DAI_DIR_CAPTURE] = ALH_GPDMA_BURST_LENGTH, \
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D | alh.h | 99 uint32_t fifo_depth[2]; member
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/Zephyr-latest/include/zephyr/drivers/ |
D | dai.h | 240 uint32_t fifo_depth; member
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/Zephyr-latest/drivers/dai/nxp/esai/ |
D | esai.c | 718 .fifo_depth = ESAI_FIFO_DEPTH(inst) * 4, \ 724 .fifo_depth = ESAI_FIFO_DEPTH(inst) * 4, \
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D | esai.h | 38 DT_INST_PROP_OR(inst, fifo_depth, _ESAI_FIFO_DEPTH(inst))
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/Zephyr-latest/drivers/dai/nxp/sai/ |
D | sai.c | 951 .fifo_depth = SAI_FIFO_DEPTH(inst) * CONFIG_SAI_FIFO_WORD_SIZE, \ 957 .fifo_depth = SAI_FIFO_DEPTH(inst) * CONFIG_SAI_FIFO_WORD_SIZE, \
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D | sai.h | 119 DT_INST_PROP_OR(inst, fifo_depth, _SAI_FIFO_DEPTH(inst))
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/Zephyr-latest/drivers/dai/intel/dmic/ |
D | dmic.c | 672 prop->fifo_depth = dmic->fifo.depth; in dai_dmic_get_properties()
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/Zephyr-latest/drivers/mspi/ |
D | mspi_dw.c | 1334 #define TX_FIFO_DEPTH(inst) DT_INST_PROP(inst, fifo_depth)
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/Zephyr-latest/doc/releases/ |
D | migration-guide-4.1.rst | 303 * Renamed the device tree property from ``fifo_depth`` to ``fifo-depth``.
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