1 /* SPDX-License-Identifier: BSD-3-Clause
2  *
3  * Copyright(c) 2018 Intel Corporation. All rights reserved.
4  *
5  * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
6  *         Keyon Jie <yang.jie@linux.intel.com>
7  */
8 
9 /**
10  * \file include/ipc/xtensa.h
11  * \brief IPC definitions
12  * \author Liam Girdwood <liam.r.girdwood@linux.intel.com>
13  * \author Keyon Jie <yang.jie@linux.intel.com>
14  */
15 
16 #ifndef __IPC_XTENSA_H__
17 #define __IPC_XTENSA_H__
18 
19 #include <ipc/header.h>
20 #include <stdint.h>
21 
22 /*
23  * Architecture specific debug
24  */
25 
26 #define ARCHITECTURE_ID 0x1
27 
28 /* Xtensa Firmware Oops data */
29 struct sof_ipc_dsp_oops_xtensa {
30 	struct sof_ipc_dsp_oops_arch_hdr arch_hdr;
31 	struct sof_ipc_dsp_oops_plat_hdr plat_hdr;
32 	uint32_t exccause;
33 	uint32_t excvaddr;
34 	uint32_t ps;
35 	uint32_t epc1;
36 	uint32_t epc2;
37 	uint32_t epc3;
38 	uint32_t epc4;
39 	uint32_t epc5;
40 	uint32_t epc6;
41 	uint32_t epc7;
42 	uint32_t eps2;
43 	uint32_t eps3;
44 	uint32_t eps4;
45 	uint32_t eps5;
46 	uint32_t eps6;
47 	uint32_t eps7;
48 	uint32_t depc;
49 	uint32_t intenable;
50 	uint32_t interrupt;
51 	uint32_t sar;
52 	uint32_t debugcause;
53 	uint32_t windowbase;
54 	uint32_t windowstart;
55 	uint32_t excsave1;
56 	uint32_t ar[];
57 } __attribute__((packed, aligned(4)));
58 
59 #endif /* __IPC_XTENSA_H__ */
60