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Searched refs:XTHAL_AR_RWXrwx (Results 1 – 8 of 8) sorted by relevance

/sof-3.4.0/src/platform/mt8195/include/arch/xtensa/config/
Dcore-matmap.h60 #define XCHAL_CA_WRITEBACK (XTHAL_MEM_WRITEBACK | XTHAL_AR_RWXrwx)
62 #define XCHAL_CA_WRITEBACK_NOALLOC (XTHAL_MEM_WRITEBACK_NOALLOC | XTHAL_AR_RWXrwx)
64 #define XCHAL_CA_WRITETHRU (XTHAL_MEM_WRITETHRU | XTHAL_AR_RWXrwx)
67 #define XCHAL_CA_BYPASS (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE)
68 #define XCHAL_CA_BYPASSBUF (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE | XTHAL_MEM_BUFFERABLE)
/sof-3.4.0/src/platform/mt8186/include/arch/xtensa/config/
Dcore-matmap.h60 #define XCHAL_CA_WRITEBACK (XTHAL_MEM_WRITEBACK | XTHAL_AR_RWXrwx)
62 #define XCHAL_CA_WRITEBACK_NOALLOC (XTHAL_MEM_WRITEBACK_NOALLOC| XTHAL_AR_RWXrwx )
64 #define XCHAL_CA_WRITETHRU (XTHAL_MEM_WRITETHRU | XTHAL_AR_RWXrwx)
67 #define XCHAL_CA_BYPASS (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE)
68 #define XCHAL_CA_BYPASSBUF (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE |\
/sof-3.4.0/src/platform/mt8188/include/arch/xtensa/config/
Dcore-matmap.h60 #define XCHAL_CA_WRITEBACK (XTHAL_MEM_WRITEBACK | XTHAL_AR_RWXrwx)
62 #define XCHAL_CA_WRITEBACK_NOALLOC (XTHAL_MEM_WRITEBACK_NOALLOC| XTHAL_AR_RWXrwx )
64 #define XCHAL_CA_WRITETHRU (XTHAL_MEM_WRITETHRU | XTHAL_AR_RWXrwx)
67 #define XCHAL_CA_BYPASS (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE)
68 #define XCHAL_CA_BYPASSBUF (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE |\
/sof-3.4.0/src/platform/mt8188/
Dplatform.c139 XTHAL_MPU_ENTRY(0x00000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_DEVICE), // infra
140 XTHAL_MPU_ENTRY(0x4e100000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_WRITEBACK), // sram
142 XTHAL_MPU_ENTRY(0x60000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_WRITEBACK), // dram
143 XTHAL_MPU_ENTRY(0x60500000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_NON_CACHEABLE), // dram
/sof-3.4.0/src/platform/mt8186/
Dplatform.c139 XTHAL_MPU_ENTRY(0x00000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_DEVICE), // unused
140 XTHAL_MPU_ENTRY(0x4e100000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_WRITEBACK), // sram
142 XTHAL_MPU_ENTRY(0x60000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_WRITEBACK), // dram
143 XTHAL_MPU_ENTRY(0x60500000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_NON_CACHEABLE), // dram
/sof-3.4.0/src/platform/mt8195/
Dplatform.c151 XTHAL_MPU_ENTRY(0x40000000, 1, XTHAL_AR_RWXrwx,
155 XTHAL_MPU_ENTRY(0x60000000, 1, XTHAL_AR_RWXrwx,
/sof-3.4.0/src/arch/xtensa/hal/
Dmpu.c226 case XTHAL_AR_RWXrwx: in is_kernel_readable()
246 case XTHAL_AR_RWXrwx: in is_kernel_writeable()
268 case XTHAL_AR_RWXrwx: in is_kernel_executable()
294 case XTHAL_AR_RWXrwx: in is_user_readable()
315 case XTHAL_AR_RWXrwx: in is_user_writeable()
339 case XTHAL_AR_RWXrwx: in is_user_executable()
681 XTHAL_MPU_ENTRY_SET_ACCESS(fg[ip], XTHAL_AR_RWXrwx); in safe_region()
/sof-3.4.0/src/arch/xtensa/include/xtensa/
Dhal.h1038 #define XTHAL_AR_RWXrwx 15 /* Kernel read/write/execute, macro