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Searched refs:XSHAL_TRAPNULL_CACHEATTR_WRITETHRU (Results 1 – 9 of 9) sorted by relevance

/sof-3.4.0/src/platform/mt8195/include/arch/xtensa/config/
Dsystem.h168 #define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2211112F /* enable caches in write-through mode */ macro
179 #define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
/sof-3.4.0/src/platform/mt8186/include/arch/xtensa/config/
Dsystem.h168 #define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2211111F /* enable caches in write-through mode */ macro
179 #define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
/sof-3.4.0/src/platform/mt8188/include/arch/xtensa/config/
Dsystem.h168 #define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2211111F /* enable caches in write-through mode */ macro
179 #define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
/sof-3.4.0/src/platform/imx8ulp/include/arch/xtensa/config/
Dsystem.h185 #define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x22222211 /* enable caches in write-through mode */ macro
196 #define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
/sof-3.4.0/src/platform/amd/renoir/include/arch/xtensa/config/
Dsystem.h182 #define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2222111F /* enable caches in write-through mode */ macro
193 #define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
/sof-3.4.0/src/platform/imx8/include/arch/xtensa/config/
Dsystem.h185 #define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2221212F /* enable caches in write-through mode */ macro
196 #define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
/sof-3.4.0/src/platform/imx8m/include/arch/xtensa/config/
Dsystem.h185 #define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2222221F /* enable caches in write-through mode */ macro
196 #define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
/sof-3.4.0/src/platform/amd/rembrandt/include/arch/xtensa/config/
Dsystem.h174 #define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x1222112F /* enable caches in write-through mode */ macro
185 #define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
/sof-3.4.0/src/platform/tigerlake/include/arch/xtensa/config/
Dsystem.h189 #define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2211222F /* enable caches in write-through mode */ macro
200 #define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU