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Searched refs:XCHAL_INT18_LEVEL (Results 1 – 9 of 9) sorted by relevance

/sof-3.4.0/src/platform/tigerlake/include/arch/xtensa/config/
Dcore-isa.h403 #define XCHAL_INT18_LEVEL 5 macro
/sof-3.4.0/src/platform/imx8/include/arch/xtensa/config/
Dcore-isa.h368 #define XCHAL_INT18_LEVEL 2 macro
/sof-3.4.0/src/platform/imx8m/include/arch/xtensa/config/
Dcore-isa.h366 #define XCHAL_INT18_LEVEL 2 macro
/sof-3.4.0/src/platform/mt8195/include/arch/xtensa/config/
Dcore-isa.h442 #define XCHAL_INT18_LEVEL 3 macro
/sof-3.4.0/src/platform/imx8ulp/include/arch/xtensa/config/
Dcore-isa.h395 #define XCHAL_INT18_LEVEL 2 macro
/sof-3.4.0/src/platform/mt8186/include/arch/xtensa/config/
Dcore-isa.h489 #define XCHAL_INT18_LEVEL 3 macro
/sof-3.4.0/src/platform/mt8188/include/arch/xtensa/config/
Dcore-isa.h489 #define XCHAL_INT18_LEVEL 3 macro
/sof-3.4.0/src/arch/xtensa/hal/
Dinterrupts.c346 DEFAULT_INTVPRI( XCHAL_INT18_LEVEL ),
/sof-3.4.0/src/arch/xtensa/include/xtensa/config/
Dcore.h262 XCHAL_SEP XCHAL_INT18_LEVEL \
412 # define XCHAL_INT18_LEVEL 0 macro