1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2018 Intel Corporation. All rights reserved. 4 * 5 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 6 * Keyon Jie <yang.jie@linux.intel.com> 7 */ 8 9 /** 10 * \file include/ipc/topology.h 11 * \brief IPC definitions 12 * \author Liam Girdwood <liam.r.girdwood@linux.intel.com> 13 * \author Keyon Jie <yang.jie@linux.intel.com> 14 */ 15 16 #ifndef __IPC_TOPOLOGY_H__ 17 #define __IPC_TOPOLOGY_H__ 18 19 #include <ipc/header.h> 20 #include <stdint.h> 21 22 /* 23 * Component 24 */ 25 26 /* types of component */ 27 enum sof_comp_type { 28 SOF_COMP_NONE = 0, 29 SOF_COMP_HOST, 30 SOF_COMP_DAI, 31 SOF_COMP_SG_HOST, /**< scatter gather variant */ 32 SOF_COMP_SG_DAI, /**< scatter gather variant */ 33 SOF_COMP_VOLUME, 34 SOF_COMP_MIXER, 35 SOF_COMP_MUX, 36 SOF_COMP_SRC, 37 SOF_COMP_SPLITTER, 38 SOF_COMP_TONE, 39 SOF_COMP_SWITCH, 40 SOF_COMP_BUFFER, 41 SOF_COMP_EQ_IIR, 42 SOF_COMP_EQ_FIR, 43 SOF_COMP_KEYWORD_DETECT, 44 SOF_COMP_KPB, /* A key phrase buffer component */ 45 SOF_COMP_SELECTOR, /**< channel selector component */ 46 SOF_COMP_DEMUX, 47 SOF_COMP_ASRC, /**< Asynchronous sample rate converter */ 48 SOF_COMP_DCBLOCK, 49 SOF_COMP_SMART_AMP, /**< smart amplifier component */ 50 SOF_COMP_MODULE_ADAPTER, /**< module adapter */ 51 /* keep FILEREAD/FILEWRITE as the last ones */ 52 SOF_COMP_FILEREAD = 10000, /**< host test based file IO */ 53 SOF_COMP_FILEWRITE = 10001, /**< host test based file IO */ 54 }; 55 56 /* XRUN action for component */ 57 #define SOF_XRUN_STOP 1 /**< stop stream */ 58 #define SOF_XRUN_UNDER_ZERO 2 /**< send 0s to sink */ 59 #define SOF_XRUN_OVER_NULL 4 /**< send data to NULL */ 60 61 /* create new generic component - SOF_IPC_TPLG_COMP_NEW */ 62 struct sof_ipc_comp { 63 struct sof_ipc_cmd_hdr hdr; 64 uint32_t id; 65 enum sof_comp_type type; 66 uint32_t pipeline_id; 67 uint32_t core; 68 69 /** extended data length, 0 if no extended data (ABI3.17) */ 70 uint32_t ext_data_length; 71 } __attribute__((packed, aligned(4))); 72 73 /* 74 * Component Buffers 75 */ 76 77 /* 78 * SOF memory capabilities, add new ones at the end 79 */ 80 #define SOF_MEM_CAPS_RAM BIT(0) 81 #define SOF_MEM_CAPS_ROM BIT(1) 82 #define SOF_MEM_CAPS_EXT BIT(2) /**< external */ 83 #define SOF_MEM_CAPS_LP BIT(3) /**< low power */ 84 #define SOF_MEM_CAPS_HP BIT(4) /**< high performance */ 85 #define SOF_MEM_CAPS_DMA BIT(5) /**< DMA'able */ 86 #define SOF_MEM_CAPS_CACHE BIT(6) /**< cacheable */ 87 #define SOF_MEM_CAPS_EXEC BIT(7) /**< executable */ 88 #define SOF_MEM_CAPS_L3 BIT(8) /**< L3 memory */ 89 90 /* 91 * overrun will cause ring buffer overwrite, instead of XRUN. 92 */ 93 #define SOF_BUF_OVERRUN_PERMITTED BIT(0) 94 95 /* 96 * underrun will cause readback of 0s, instead of XRUN. 97 */ 98 #define SOF_BUF_UNDERRUN_PERMITTED BIT(1) 99 100 /* the UUID size in bytes, shared between FW and host */ 101 #define SOF_UUID_SIZE 16 102 103 /* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */ 104 struct sof_ipc_buffer { 105 struct sof_ipc_comp comp; 106 uint32_t size; /**< buffer size in bytes */ 107 uint32_t caps; /**< SOF_MEM_CAPS_ */ 108 uint32_t flags; /**< SOF_BUF_ flags defined above */ 109 uint32_t reserved; /**< reserved for future use */ 110 } __attribute__((packed, aligned(4))); 111 112 /* generic component config data - must always be after struct sof_ipc_comp */ 113 struct sof_ipc_comp_config { 114 struct sof_ipc_cmd_hdr hdr; 115 uint32_t periods_sink; /**< 0 means variable */ 116 uint32_t periods_source;/**< 0 means variable */ 117 uint32_t reserved1; /**< reserved */ 118 uint32_t frame_fmt; /**< SOF_IPC_FRAME_ */ 119 uint32_t xrun_action; 120 121 /* reserved for future use */ 122 uint32_t reserved[2]; 123 } __attribute__((packed, aligned(4))); 124 125 /* generic host component */ 126 struct sof_ipc_comp_host { 127 struct sof_ipc_comp comp; 128 struct sof_ipc_comp_config config; 129 uint32_t direction; /**< SOF_IPC_STREAM_ */ 130 uint32_t no_irq; /**< don't send periodic IRQ to host/DSP */ 131 uint32_t dmac_config; /**< DMA engine specific */ 132 } __attribute__((packed, aligned(4))); 133 134 /* generic DAI component */ 135 struct sof_ipc_comp_dai { 136 struct sof_ipc_comp comp; 137 struct sof_ipc_comp_config config; 138 uint32_t direction; /**< SOF_IPC_STREAM_ */ 139 uint32_t dai_index; /**< index of this type dai */ 140 uint32_t type; /**< DAI type - SOF_DAI_ */ 141 uint32_t reserved; /**< reserved */ 142 } __attribute__((packed, aligned(4))); 143 144 /* generic mixer component */ 145 struct sof_ipc_comp_mixer { 146 struct sof_ipc_comp comp; 147 struct sof_ipc_comp_config config; 148 } __attribute__((packed, aligned(4))); 149 150 /* volume ramping types */ 151 enum sof_volume_ramp { 152 SOF_VOLUME_LINEAR = 0, 153 SOF_VOLUME_LOG, 154 SOF_VOLUME_LINEAR_ZC, 155 SOF_VOLUME_LOG_ZC, 156 SOF_VOLUME_WINDOWS_FADE, 157 SOF_VOLUME_WINDOWS_NO_FADE, 158 }; 159 160 /* generic volume component */ 161 struct sof_ipc_comp_volume { 162 struct sof_ipc_comp comp; 163 struct sof_ipc_comp_config config; 164 uint32_t channels; 165 uint32_t min_value; 166 uint32_t max_value; 167 uint32_t ramp; /**< SOF_VOLUME_ */ 168 uint32_t initial_ramp; /**< ramp space in ms */ 169 } __attribute__((packed, aligned(4))); 170 171 /* generic SRC component */ 172 struct sof_ipc_comp_src { 173 struct sof_ipc_comp comp; 174 struct sof_ipc_comp_config config; 175 /* either source or sink rate must be non zero */ 176 uint32_t source_rate; /**< source rate or 0 for variable */ 177 uint32_t sink_rate; /**< sink rate or 0 for variable */ 178 uint32_t rate_mask; /**< SOF_RATE_ supported rates */ 179 } __attribute__((packed, aligned(4))); 180 181 /* generic ASRC component */ 182 struct sof_ipc_comp_asrc { 183 struct sof_ipc_comp comp; 184 struct sof_ipc_comp_config config; 185 /* either source or sink rate must be non zero */ 186 uint32_t source_rate; /**< Define fixed source rate or */ 187 /**< use 0 to indicate need to get */ 188 /**< the rate from stream */ 189 uint32_t sink_rate; /**< Define fixed sink rate or */ 190 /**< use 0 to indicate need to get */ 191 /**< the rate from stream */ 192 uint32_t asynchronous_mode; /**< synchronous 0, asynchronous 1 */ 193 /**< When 1 the ASRC tracks and */ 194 /**< compensates for drift. */ 195 uint32_t operation_mode; /**< push 0, pull 1, In push mode the */ 196 /**< ASRC consumes a defined number */ 197 /**< of frames at input, with varying */ 198 /**< number of frames at output. */ 199 /**< In pull mode the ASRC outputs */ 200 /**< a defined number of frames while */ 201 /**< number of input frames varies. */ 202 203 /* reserved for future use */ 204 uint32_t reserved[4]; 205 } __attribute__((packed, aligned(4))); 206 207 /* generic MUX component */ 208 struct sof_ipc_comp_mux { 209 struct sof_ipc_comp comp; 210 struct sof_ipc_comp_config config; 211 } __attribute__((packed, aligned(4))); 212 213 /* generic tone generator component */ 214 struct sof_ipc_comp_tone { 215 struct sof_ipc_comp comp; 216 struct sof_ipc_comp_config config; 217 int32_t sample_rate; 218 int32_t frequency; 219 int32_t amplitude; 220 int32_t freq_mult; 221 int32_t ampl_mult; 222 int32_t length; 223 int32_t period; 224 int32_t repeats; 225 int32_t ramp_step; 226 } __attribute__((packed, aligned(4))); 227 228 /* generic "effect", "codec" or proprietary processing component */ 229 struct sof_ipc_comp_process { 230 struct sof_ipc_comp comp; 231 struct sof_ipc_comp_config config; 232 uint32_t size; /**< size of bespoke data section in bytes */ 233 uint32_t type; /**< sof_ipc_process_type */ 234 235 /* reserved for future use */ 236 uint32_t reserved[7]; 237 238 unsigned char data[]; 239 } __attribute__((packed, aligned(4))); 240 241 /* IPC file component used by testbench only */ 242 struct sof_ipc_comp_file { 243 struct sof_ipc_comp comp; 244 struct sof_ipc_comp_config config; 245 uint32_t rate; 246 uint32_t channels; 247 char *fn; 248 uint32_t mode; 249 uint32_t frame_fmt; 250 uint32_t direction; /**< SOF_IPC_STREAM_ */ 251 } __attribute__((packed, aligned(4))); 252 253 /* frees components, buffers and pipelines 254 * SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_FREE, SOF_IPC_TPLG_BUFFER_FREE 255 */ 256 struct sof_ipc_free { 257 struct sof_ipc_cmd_hdr hdr; 258 uint32_t id; 259 } __attribute__((packed, aligned(4))); 260 261 struct sof_ipc_comp_reply { 262 struct sof_ipc_reply rhdr; 263 uint32_t id; 264 uint32_t offset; 265 } __attribute__((packed, aligned(4))); 266 267 /* 268 * Pipeline 269 */ 270 271 /** \brief Types of pipeline scheduling time domains */ 272 enum sof_ipc_pipe_sched_time_domain { 273 SOF_TIME_DOMAIN_DMA = 0, /**< DMA interrupt */ 274 SOF_TIME_DOMAIN_TIMER, /**< Timer interrupt */ 275 }; 276 277 /* new pipeline - SOF_IPC_TPLG_PIPE_NEW */ 278 struct sof_ipc_pipe_new { 279 struct sof_ipc_cmd_hdr hdr; 280 uint32_t comp_id; /**< component id for pipeline */ 281 uint32_t pipeline_id; /**< pipeline id */ 282 uint32_t sched_id; /**< Scheduling component id */ 283 uint32_t core; /**< core we run on */ 284 uint32_t period; /**< execution period in us*/ 285 uint32_t priority; /**< priority level 0 (low) to 10 (max) */ 286 uint32_t period_mips; /**< worst case instruction count per period */ 287 uint32_t frames_per_sched;/**< output frames of pipeline, 0 is variable */ 288 uint32_t xrun_limit_usecs; /**< report xruns greater than limit */ 289 uint32_t time_domain; /**< scheduling time domain */ 290 } __attribute__((packed, aligned(4))); 291 292 /* pipeline construction complete - SOF_IPC_TPLG_PIPE_COMPLETE */ 293 struct sof_ipc_pipe_ready { 294 struct sof_ipc_cmd_hdr hdr; 295 uint32_t comp_id; 296 } __attribute__((packed, aligned(4))); 297 298 struct sof_ipc_pipe_free { 299 struct sof_ipc_cmd_hdr hdr; 300 uint32_t comp_id; 301 } __attribute__((packed, aligned(4))); 302 303 /* connect two components in pipeline - SOF_IPC_TPLG_COMP_CONNECT */ 304 struct sof_ipc_pipe_comp_connect { 305 struct sof_ipc_cmd_hdr hdr; 306 uint32_t source_id; 307 uint32_t sink_id; 308 } __attribute__((packed, aligned(4))); 309 310 /* extended data struct for UUID components */ 311 struct sof_ipc_comp_ext { 312 uint8_t uuid[SOF_UUID_SIZE]; 313 } __attribute__((packed, aligned(4))); 314 315 #endif /* __IPC_TOPOLOGY_H__ */ 316
