1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2017 Intel Corporation. All rights reserved. 4 * 5 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 6 * Keyon Jie <yang.jie@linux.intel.com> 7 * Rander Wang <rander.wang@intel.com> 8 */ 9 10 #ifdef __SOF_LIB_SHIM_H__ 11 12 #ifndef __PLATFORM_LIB_SHIM_H__ 13 #define __PLATFORM_LIB_SHIM_H__ 14 15 #include <cavs/drivers/sideband-ipc.h> 16 #include <cavs/lib/shim.h> 17 #include <rtos/bit.h> 18 #include <sof/lib/memory.h> 19 20 /* DSP IPC for Host Registers */ 21 #define IPC_DIPCTDR 0x00 22 #define IPC_DIPCTDA 0x04 23 #define IPC_DIPCTDD 0x08 24 #define IPC_DIPCIDR 0x10 25 #define IPC_DIPCIDA 0x14 26 #define IPC_DIPCIDD 0x18 27 #define IPC_DIPCCTL 0x28 28 29 #define IPC_DSP_OFFSET 0x10 30 31 /* DSP IPC for intra DSP communication */ 32 #define IPC_IDCTFC(x) (0x0 + x * IPC_DSP_OFFSET) 33 #define IPC_IDCTEFC(x) (0x4 + x * IPC_DSP_OFFSET) 34 #define IPC_IDCITC(x) (0x8 + x * IPC_DSP_OFFSET) 35 #define IPC_IDCIETC(x) (0xc + x * IPC_DSP_OFFSET) 36 #define IPC_IDCCTL 0x50 37 38 /* IDCTFC */ 39 #define IPC_IDCTFC_BUSY BIT(31) 40 #define IPC_IDCTFC_MSG_MASK 0x7FFFFFFF 41 42 /* IDCTEFC */ 43 #define IPC_IDCTEFC_MSG_MASK 0x3FFFFFFF 44 45 /* IDCITC */ 46 #define IPC_IDCITC_BUSY BIT(31) 47 #define IPC_IDCITC_MSG_MASK 0x7FFFFFFF 48 49 /* IDCIETC */ 50 #define IPC_IDCIETC_DONE BIT(30) 51 #define IPC_IDCIETC_MSG_MASK 0x3FFFFFFF 52 53 /* IDCCTL */ 54 #define IPC_IDCCTL_IDCIDIE(x) (0x100 << (x)) 55 #define IPC_IDCCTL_IDCTBIE(x) BIT(x) 56 57 #define IRQ_CPU_OFFSET 0x40 58 59 #define REG_IRQ_IL2MSD(xcpu) (0x0 + (xcpu * IRQ_CPU_OFFSET)) 60 #define REG_IRQ_IL2MCD(xcpu) (0x4 + (xcpu * IRQ_CPU_OFFSET)) 61 #define REG_IRQ_IL2MD(xcpu) (0x8 + (xcpu * IRQ_CPU_OFFSET)) 62 #define REG_IRQ_IL2SD(xcpu) (0xc + (xcpu * IRQ_CPU_OFFSET)) 63 64 /* all mask valid bits */ 65 #define REG_IRQ_IL2MD_ALL 0x03F181F0 66 67 #define REG_IRQ_IL3MSD(xcpu) (0x10 + (xcpu * IRQ_CPU_OFFSET)) 68 #define REG_IRQ_IL3MCD(xcpu) (0x14 + (xcpu * IRQ_CPU_OFFSET)) 69 #define REG_IRQ_IL3MD(xcpu) (0x18 + (xcpu * IRQ_CPU_OFFSET)) 70 #define REG_IRQ_IL3SD(xcpu) (0x1c + (xcpu * IRQ_CPU_OFFSET)) 71 72 /* all mask valid bits */ 73 #define REG_IRQ_IL3MD_ALL 0x807F81FF 74 75 #define REG_IRQ_IL4MSD(xcpu) (0x20 + (xcpu * IRQ_CPU_OFFSET)) 76 #define REG_IRQ_IL4MCD(xcpu) (0x24 + (xcpu * IRQ_CPU_OFFSET)) 77 #define REG_IRQ_IL4MD(xcpu) (0x28 + (xcpu * IRQ_CPU_OFFSET)) 78 #define REG_IRQ_IL4SD(xcpu) (0x2c + (xcpu * IRQ_CPU_OFFSET)) 79 80 /* all mask valid bits */ 81 #define REG_IRQ_IL4MD_ALL 0x807F81FF 82 83 #define REG_IRQ_IL5MSD(xcpu) (0x30 + (xcpu * IRQ_CPU_OFFSET)) 84 #define REG_IRQ_IL5MCD(xcpu) (0x34 + (xcpu * IRQ_CPU_OFFSET)) 85 #define REG_IRQ_IL5MD(xcpu) (0x38 + (xcpu * IRQ_CPU_OFFSET)) 86 #define REG_IRQ_IL5SD(xcpu) (0x3c + (xcpu * IRQ_CPU_OFFSET)) 87 88 /* all mask valid bits */ 89 #define REG_IRQ_IL5MD_ALL 0xFFFFC0CF 90 91 #define REG_IRQ_IL2RSD 0x100 92 #define REG_IRQ_IL3RSD 0x104 93 #define REG_IRQ_IL4RSD 0x108 94 #define REG_IRQ_IL5RSD 0x10c 95 96 #define REG_IRQ_LVL5_LP_GPDMA0_MASK (0xff << 16) 97 #define REG_IRQ_LVL5_LP_GPDMA1_MASK (0xff << 24) 98 99 /* DSP Shim Registers */ 100 #define SHIM_DSPWC 0x20 /* DSP Wall Clock */ 101 #define SHIM_DSPWCL 0x20 /* DSP Wall Clock Low */ 102 #define SHIM_DSPWCH 0x24 /* DSP Wall Clock High */ 103 #define SHIM_DSPWCTCS 0x28 /* DSP Wall Clock Timer Control & Status */ 104 #define SHIM_DSPWCT0C 0x30 /* DSP Wall Clock Timer 0 Compare */ 105 #define SHIM_DSPWCT1C 0x38 /* DSP Wall Clock Timer 1 Compare */ 106 107 #define SHIM_DSPWCTCS_T1T BIT(5) /* Timer 1 triggered */ 108 #define SHIM_DSPWCTCS_T0T BIT(4) /* Timer 0 triggered */ 109 #define SHIM_DSPWCTCS_T1A BIT(1) /* Timer 1 armed */ 110 #define SHIM_DSPWCTCS_T0A BIT(0) /* Timer 0 armed */ 111 112 /** \brief Clock control */ 113 #define SHIM_CLKCTL 0x78 114 115 /** \brief Request HP RING Oscillator Clock */ 116 #define SHIM_CLKCTL_RHROSCC BIT(31) 117 118 /** \brief Request WOVCRO Clock */ 119 #define SHIM_CLKCTL_WOV_CRO_REQUEST BIT(4) 120 121 /** \brief Request XTAL Oscillator Clock */ 122 #define SHIM_CLKCTL_RXOSCC BIT(30) 123 124 /** \brief Request LP RING Oscillator Clock */ 125 #define SHIM_CLKCTL_RLROSCC BIT(29) 126 127 /** \brief Tensilica Core Prevent Local Clock Gating */ 128 #define SHIM_CLKCTL_TCPLCG_EN(x) BIT(16 + (x)) 129 #define SHIM_CLKCTL_TCPLCG_DIS(x) 0 130 #define SHIM_CLKCTL_TCPLCG_DIS_ALL (SHIM_CLKCTL_TCPLCG_DIS(0) | \ 131 SHIM_CLKCTL_TCPLCG_DIS(1) | \ 132 SHIM_CLKCTL_TCPLCG_DIS(2) | \ 133 SHIM_CLKCTL_TCPLCG_DIS(3)) 134 135 /** \brief Oscillator Clock Select*/ 136 #define SHIM_CLKCTL_OCS_HP_RING BIT(2) 137 #define SHIM_CLKCTL_OCS_LP_RING 0 138 #define SHIM_CLKCTL_WOVCROSC BIT(3) 139 140 /** \brief LP Memory Clock Select */ 141 #define SHIM_CLKCTL_LMCS_DIV2 0 142 #define SHIM_CLKCTL_LMCS_DIV4 BIT(1) 143 144 /** \brief HP Memory Clock Select */ 145 #define SHIM_CLKCTL_HMCS_DIV2 0 146 #define SHIM_CLKCTL_HMCS_DIV4 BIT(0) 147 148 /* Core clock PLL divisor */ 149 #define SHIM_CLKCTL_DPCS_MASK(x) BIT(2) 150 151 /* Prevent Audio PLL Shutdown */ 152 #define SHIM_CLKCTL_TCPAPLLS BIT(7) 153 154 /* 0--from PLL, 1--from oscillator */ 155 #define SHIM_CLKCTL_HDCS BIT(4) 156 157 /* Oscillator select */ 158 #define SHIM_CLKCTL_HDOCS BIT(2) 159 160 /* HP memory clock PLL divisor */ 161 #define SHIM_CLKCTL_HPMPCS BIT(0) 162 163 /** \brief Mask for requesting clock 164 */ 165 #define SHIM_CLKCTL_OSC_REQUEST_MASK \ 166 (SHIM_CLKCTL_RHROSCC | SHIM_CLKCTL_RXOSCC | \ 167 SHIM_CLKCTL_RLROSCC) 168 169 /** \brief Mask for setting previously requested clock 170 */ 171 #define SHIM_CLKCTL_OSC_SOURCE_MASK \ 172 (SHIM_CLKCTL_OCS_HP_RING | SHIM_CLKCTL_LMCS_DIV4 | \ 173 SHIM_CLKCTL_HMCS_DIV4) 174 175 /** \brief Clock status */ 176 #define SHIM_CLKSTS 0x7C 177 178 /** \brief HP RING Oscillator Clock Status */ 179 #define SHIM_CLKSTS_HROSCCS BIT(31) 180 181 /** \brief WOVCRO Clock Status */ 182 #define SHIM_CLKSTS_WOV_CRO BIT(4) 183 184 /** \brief XTAL Oscillator Clock Status */ 185 #define SHIM_CLKSTS_XOSCCS BIT(30) 186 187 /** \brief LP RING Oscillator Clock Status */ 188 #define SHIM_CLKSTS_LROSCCS BIT(29) 189 190 #define SHIM_PWRCTL 0x90 191 #define SHIM_PWRCTL_TCPDSPPG(x) BIT(x) 192 #define SHIM_PWRCTL_TCPCTLPG BIT(4) 193 194 #define SHIM_PWRSTS 0x92 195 196 #define SHIM_LPSCTL 0x94 197 #define SHIM_LPSCTL_BID BIT(7) 198 #define SHIM_LPSCTL_FDSPRUN BIT(9) 199 #define SHIM_LPSCTL_BATTR_0 BIT(12) 200 201 /** \brief GPDMA shim registers Control */ 202 #define SHIM_GPDMA_BASE_OFFSET 0x6500 203 #define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x100) 204 205 /** \brief GPDMA Clock Control */ 206 #define SHIM_GPDMA_CLKCTL(x) (SHIM_GPDMA_BASE(x) + 0x4) 207 /* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */ 208 #define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0) 209 210 /** \brief GPDMA Channel Linear Link Position Control */ 211 #define SHIM_GPDMA_CHLLPC(x, y) (SHIM_GPDMA_BASE(x) + 0x10 + (y) * 0x10) 212 #define SHIM_GPDMA_CHLLPC_EN BIT(7) 213 #define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x) 214 215 #define SHIM_GPDMA_CHLLPL(x, y) (SHIM_GPDMA_BASE(x) + 0x18 + (y) * 0x10) 216 #define SHIM_GPDMA_CHLLPU(x, y) (SHIM_GPDMA_BASE(x) + 0x1c + (y) * 0x10) 217 218 /* I2S SHIM Registers */ 219 #define I2SLCTL 0x71C04 220 221 /* SPA register should be set for each I2S port and DSP should 222 * wait for CPA to be set 223 */ 224 #define I2SLCTL_SPA(x) BIT(0 + x) 225 #define I2SLCTL_CPA(x) BIT(8 + x) 226 227 #define L2LMCAP 0x71D00 228 #define L2MPAT 0x71D04 229 230 #define HSPGCTL0 0x71D10 231 #define HSRMCTL0 0x71D14 232 #define HSPGISTS0 0x71D18 233 234 #define SHIM_HSPGCTL(x) (HSPGCTL0 + 0x10 * (x)) 235 #define SHIM_HSRMCTL(x) (HSRMCTL0 + 0x10 * (x)) 236 #define SHIM_HSPGISTS(x) (HSPGISTS0 + 0x10 * (x)) 237 238 #define HSPGCTL1 0x71D20 239 #define HSRMCTL1 0x71D24 240 #define HSPGISTS1 0x71D28 241 242 #define LSPGCTL 0x71D50 243 #define LSRMCTL 0x71D54 244 #define LSPGISTS 0x71D58 245 246 #define SHIM_L2_MECS (SHIM_BASE + 0xd0) 247 248 /** \brief LDO Control */ 249 #define SHIM_LDOCTL 0xA4 250 #define SHIM_LDOCTL_HPSRAM_MASK (3 << 0 | 3 << 16) 251 #define SHIM_LDOCTL_LPSRAM_MASK (3 << 2) 252 #define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0 | 3 << 16) 253 #define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2) 254 #define SHIM_LDOCTL_HPSRAM_LDO_BYPASS (BIT(0) | BIT(16)) 255 #define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2) 256 #define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0) 257 #define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2) 258 259 #define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x)) 260 #define LPGPDMA_CTLOSEL_FLAG BIT(15) 261 #define LPGPDMA_CHOSEL_FLAG 0xFF 262 263 #define DSP_INIT_IOPO 0x71A68 264 #define IOPO_DMIC_FLAG BIT(0) 265 #define IOPO_I2S_FLAG MASK(DAI_NUM_SSP_BASE + DAI_NUM_SSP_EXT + 7, 8) 266 267 #define DSP_INIT_GENO 0x71A6C 268 #define GENO_MDIVOSEL BIT(1) 269 #define GENO_DIOPTOSEL BIT(2) 270 271 #define DSP_INIT_ALHO 0x71A70 272 #define ALHO_ASO_FLAG BIT(0) 273 #define ALHO_CSO_FLAG BIT(1) 274 #define ALHO_CFO_FLAG BIT(2) 275 276 #define SHIM_SVCFG 0xF4 277 #define SHIM_SVCFG_FORCE_L1_EXIT BIT(1) 278 279 /* host windows */ 280 #define DMWBA(x) (HOST_WIN_BASE(x) + 0x0) 281 #define DMWLO(x) (HOST_WIN_BASE(x) + 0x4) 282 283 #define DMWBA_ENABLE BIT(0) 284 #define DMWBA_READONLY BIT(1) 285 286 /* DMIC power ON bit */ 287 #define DMICLCTL_SPA ((uint32_t) BIT(0)) 288 289 /* DMIC disable clock gating */ 290 #define DMIC_DCGD ((uint32_t) BIT(30)) 291 292 #endif /* __PLATFORM_LIB_SHIM_H__ */ 293 294 #else 295 296 #error "This file shouldn't be included from outside of sof/lib/shim.h" 297 298 #endif /* __SOF_LIB_SHIM_H__ */ 299
