Home
last modified time | relevance | path

Searched refs:INTENABLE (Results 1 – 15 of 15) sorted by relevance

/sof-3.4.0/src/arch/xtensa/debug/gdb/
Dutilities.c86 sregs[INTENABLE] &= ~GDB_DISABLE_LOWER_INTERRUPTS_MASK; in arch_gdb_single_step()
89 arch_gdb_write_sr(INTENABLE, sregs); in arch_gdb_single_step()
Ddebugexception.S176 LOAD INTENABLE
/sof-3.4.0/src/arch/xtensa/include/arch/debug/gdb/
Dxtensa-defs.h28 #define DEBUG_INTENABLE INTENABLE
/sof-3.4.0/src/platform/mt8195/include/arch/xtensa/config/
Dspecreg.h70 #define INTENABLE 228 macro
/sof-3.4.0/src/platform/imx8/include/arch/xtensa/config/
Dspecreg.h71 #define INTENABLE 228 macro
/sof-3.4.0/src/platform/imx8m/include/arch/xtensa/config/
Dspecreg.h71 #define INTENABLE 228 macro
/sof-3.4.0/src/platform/amd/rembrandt/include/arch/xtensa/config/
Dspecreg.h78 #define INTENABLE 228 macro
/sof-3.4.0/src/arch/xtensa/xtos/xea2/
Dintlevel-restore.S84 wsr a5, INTENABLE
/sof-3.4.0/src/platform/mt8186/include/arch/xtensa/config/
Dspecreg.h76 #define INTENABLE 228 macro
/sof-3.4.0/src/platform/mt8188/include/arch/xtensa/config/
Dspecreg.h76 #define INTENABLE 228 macro
/sof-3.4.0/src/platform/imx8ulp/include/arch/xtensa/config/
Dspecreg.h78 #define INTENABLE 228 macro
/sof-3.4.0/src/platform/tigerlake/include/arch/xtensa/config/
Dspecreg.h86 #define INTENABLE 228 macro
/sof-3.4.0/src/platform/amd/renoir/include/arch/xtensa/config/
Dspecreg.h82 #define INTENABLE 228 macro
/sof-3.4.0/src/arch/xtensa/include/xtensa/
Dspecreg.h95 #define INTENABLE 228 macro
/sof-3.4.0/src/platform/intel/cavs/
Dalternate_reset_vector.S115 wsr a2, INTENABLE
184 wsr a2, INTENABLE