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Searched refs:EXCSAVE (Results 1 – 13 of 13) sorted by relevance

/sof-3.4.0/src/arch/xtensa/include/arch/debug/gdb/
Dxtensa-defs.h22 #define DEBUG_EXCSAVE (EXCSAVE + XCHAL_DEBUGLEVEL)
/sof-3.4.0/src/arch/xtensa/xtos/
Dreset-unneeded.S120 wsr a0, EXCSAVE+1
128 wsr a0, EXCSAVE + \num
/sof-3.4.0/src/platform/mt8195/include/arch/xtensa/config/
Dspecreg.h95 #define EXCSAVE 208 macro
/sof-3.4.0/src/platform/imx8/include/arch/xtensa/config/
Dspecreg.h92 #define EXCSAVE 208 macro
/sof-3.4.0/src/platform/imx8m/include/arch/xtensa/config/
Dspecreg.h92 #define EXCSAVE 208 macro
/sof-3.4.0/src/platform/amd/rembrandt/include/arch/xtensa/config/
Dspecreg.h99 #define EXCSAVE 208 macro
/sof-3.4.0/src/platform/mt8186/include/arch/xtensa/config/
Dspecreg.h101 #define EXCSAVE 208 macro
/sof-3.4.0/src/platform/mt8188/include/arch/xtensa/config/
Dspecreg.h101 #define EXCSAVE 208 macro
/sof-3.4.0/src/platform/imx8ulp/include/arch/xtensa/config/
Dspecreg.h100 #define EXCSAVE 208 macro
/sof-3.4.0/src/platform/tigerlake/include/arch/xtensa/config/
Dspecreg.h106 #define EXCSAVE 208 macro
/sof-3.4.0/src/platform/amd/renoir/include/arch/xtensa/config/
Dspecreg.h104 #define EXCSAVE 208 macro
/sof-3.4.0/src/arch/xtensa/include/xtensa/
Dspecreg.h120 #define EXCSAVE 208 macro
/sof-3.4.0/src/platform/intel/cavs/
Dlps_pic_restore_vector.S25 wsr a4, EXCSAVE+\level