XSHAL_ALLVALID_CACHEATTR_DEFAULT (reference) in projects: sof-2.7.6

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Searched refs:XSHAL_ALLVALID_CACHEATTR_DEFAULT (Results 1 – 11 of 11) sorted by relevance

/sof-2.7.6/src/platform/imx8ulp/include/arch/xtensa/config/
D	system.h	`171 #define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to e… macro`
/sof-2.7.6/src/platform/amd/renoir/include/arch/xtensa/config/
D	system.h	`168 #define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to e… macro`
/sof-2.7.6/src/platform/haswell/include/arch/xtensa/config/
D	system.h	`169 #define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to e… macro`
/sof-2.7.6/src/platform/imx8m/include/arch/xtensa/config/
D	system.h	`171 #define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to e… macro`
/sof-2.7.6/src/platform/imx8/include/arch/xtensa/config/
D	system.h	`171 #define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to e… macro`
/sof-2.7.6/src/platform/baytrail/include/arch/xtensa/config/
D	system.h	`169 #define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to e… macro`
/sof-2.7.6/src/platform/tigerlake/include/arch/xtensa/config/
D	system.h	`175 #define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to e… macro`
/sof-2.7.6/src/platform/suecreek/include/arch/xtensa/config/
D	system.h	`175 #define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to e… macro`
/sof-2.7.6/src/platform/cannonlake/include/arch/xtensa/config/
D	system.h	`175 #define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to e… macro`
/sof-2.7.6/src/platform/icelake/include/arch/xtensa/config/
D	system.h	`175 #define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to e… macro`
/sof-2.7.6/src/platform/apollolake/include/arch/xtensa/config/
D	system.h	`175 #define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to e… macro`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
acpica-3.6.0
acpica-3.7.0
babblesim_base-3.4.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
babblesim_ext_2G4_modem_BLE_simple-3.4.0
babblesim_ext_2G4_modem_BLE_simple-3.6.0-3.5.0
babblesim_ext_2G4_modem_BLE_simple-3.7.0
babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_modem_magic-3.7.0
babblesim_ext_2G4_phy_v1-3.4.0
babblesim_ext_2G4_phy_v1-3.6.0-3.5.0
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