1 /* SPDX-License-Identifier: BSD-3-Clause
2 *
3 * Copyright(c) 2016 Intel Corporation. All rights reserved.
4 *
5 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
6 */
7
8 #ifndef __SOF_DRIVERS_SSP_H__
9 #define __SOF_DRIVERS_SSP_H__
10
11 #include <sof/bit.h>
12 #include <sof/lib/clk.h>
13 #include <sof/lib/dai.h>
14 #include <sof/lib/wait.h>
15 #include <sof/trace/trace.h>
16 #include <ipc/dai.h>
17 #include <ipc/dai-intel.h>
18 #include <user/trace.h>
19
20 #include <stdint.h>
21
22 #define SSP_CLOCK_XTAL_OSCILLATOR 0x0
23 #define SSP_CLOCK_AUDIO_CARDINAL 0x1
24 #define SSP_CLOCK_PLL_FIXED 0x2
25
26 extern const struct freq_table *ssp_freq;
27 extern const uint32_t *ssp_freq_sources;
28
29 /* SSP register offsets */
30 #define SSCR0 0x00
31 #define SSCR1 0x04
32 #define SSSR 0x08
33 #define SSITR 0x0C
34 #define SSDR 0x10
35 #define SSTO 0x28
36 #define SSPSP 0x2C
37 #define SSTSA 0x30
38 #define SSRSA 0x34
39 #define SSTSS 0x38
40 #define SSCR2 0x40
41
42 #if CONFIG_BAYTRAIL || CONFIG_CHERRYTRAIL || CONFIG_BROADWELL || CONFIG_HASWELL
43 #define SFIFOL 0x68
44 #define SFIFOTT 0x6C
45 #define SSCR3 0x70
46 #define SSCR4 0x74
47 #define SSCR5 0x78
48 #endif
49
50 extern const struct dai_driver ssp_driver;
51
52 /* SSCR0 bits */
53 #define SSCR0_DSIZE(x) SET_BITS(3, 0, (x) - 1)
54 #define SSCR0_DSIZE_GET(x) (((x) & MASK(3, 0)) + 1)
55 #define SSCR0_FRF MASK(5, 4)
56 #define SSCR0_MOT SET_BITS(5, 4, 0)
57 #define SSCR0_TI SET_BITS(5, 4, 1)
58 #define SSCR0_NAT SET_BITS(5, 4, 2)
59 #define SSCR0_PSP SET_BITS(5, 4, 3)
60 #define SSCR0_ECS BIT(6)
61 #define SSCR0_SSE BIT(7)
62 #define SSCR0_SCR_MASK MASK(19, 8)
63 #define SSCR0_SCR(x) SET_BITS(19, 8, x)
64 #define SSCR0_EDSS BIT(20)
65 #define SSCR0_NCS BIT(21)
66 #define SSCR0_RIM BIT(22)
67 #define SSCR0_TIM BIT(23)
68 #define SSCR0_FRDC(x) SET_BITS(26, 24, (x) - 1)
69 #define SSCR0_FRDC_GET(x) ((((x) & MASK(26, 24)) >> 24) + 1)
70 #define SSCR0_ACS BIT(30)
71 #define SSCR0_MOD BIT(31)
72
73 /* SSCR1 bits */
74 #define SSCR1_RIE BIT(0)
75 #define SSCR1_TIE BIT(1)
76 #define SSCR1_LBM BIT(2)
77 #define SSCR1_SPO BIT(3)
78 #define SSCR1_SPH BIT(4)
79 #define SSCR1_MWDS BIT(5)
80 #define SSCR1_TFT_MASK MASK(9, 6)
81 #define SSCR1_TFT(x) SET_BITS(9, 6, (x) - 1)
82 #define SSCR1_RFT_MASK MASK(13, 10)
83 #define SSCR1_RFT(x) SET_BITS(13, 10, (x) - 1)
84 #define SSCR1_EFWR BIT(14)
85 #define SSCR1_STRF BIT(15)
86 #define SSCR1_IFS BIT(16)
87 #define SSCR1_PINTE BIT(18)
88 #define SSCR1_TINTE BIT(19)
89 #define SSCR1_RSRE BIT(20)
90 #define SSCR1_TSRE BIT(21)
91 #define SSCR1_TRAIL BIT(22)
92 #define SSCR1_RWOT BIT(23)
93 #define SSCR1_SFRMDIR BIT(24)
94 #define SSCR1_SCLKDIR BIT(25)
95 #define SSCR1_ECRB BIT(26)
96 #define SSCR1_ECRA BIT(27)
97 #define SSCR1_SCFR BIT(28)
98 #define SSCR1_EBCEI BIT(29)
99 #define SSCR1_TTE BIT(30)
100 #define SSCR1_TTELP BIT(31)
101
102 #if CONFIG_BAYTRAIL || CONFIG_CHERRYTRAIL
103 /* SSCR2 bits */
104 #define SSCR2_URUN_FIX0 BIT(0)
105 #define SSCR2_URUN_FIX1 BIT(1)
106 #define SSCR2_SLV_EXT_CLK_RUN_EN BIT(2)
107 #define SSCR2_CLK_DEL_EN BIT(3)
108 #define SSCR2_UNDRN_FIX_EN BIT(6)
109 #define SSCR2_FIFO_EMPTY_FIX_EN BIT(7)
110 #define SSCR2_ASRC_CNTR_EN BIT(8)
111 #define SSCR2_ASRC_CNTR_CLR BIT(9)
112 #define SSCR2_ASRC_FRM_CNRT_EN BIT(10)
113 #define SSCR2_ASRC_INTR_MASK BIT(11)
114 #elif CONFIG_CAVS || CONFIG_HASWELL || CONFIG_BROADWELL
115 #define SSCR2_TURM1 BIT(1)
116 #define SSCR2_PSPSRWFDFD BIT(3)
117 #define SSCR2_PSPSTWFDFD BIT(4)
118 #define SSCR2_SDFD BIT(14)
119 #define SSCR2_SDPM BIT(16)
120 #define SSCR2_LJDFD BIT(17)
121 #define SSCR2_MMRATF BIT(18)
122 #define SSCR2_SMTATF BIT(19)
123 #endif
124
125 /* SSR bits */
126 #define SSSR_TNF BIT(2)
127 #define SSSR_RNE BIT(3)
128 #define SSSR_BSY BIT(4)
129 #define SSSR_TFS BIT(5)
130 #define SSSR_RFS BIT(6)
131 #define SSSR_ROR BIT(7)
132 #define SSSR_TUR BIT(21)
133
134 /* SSPSP bits */
135 #define SSPSP_SCMODE(x) SET_BITS(1, 0, x)
136 #define SSPSP_SFRMP(x) SET_BIT(2, x)
137 #define SSPSP_ETDS BIT(3)
138 #define SSPSP_STRTDLY(x) SET_BITS(6, 4, x)
139 #define SSPSP_DMYSTRT(x) SET_BITS(8, 7, x)
140 #define SSPSP_SFRMDLY(x) SET_BITS(15, 9, x)
141 #define SSPSP_SFRMWDTH(x) SET_BITS(21, 16, x)
142 #define SSPSP_DMYSTOP(x) SET_BITS(24, 23, x)
143 #define SSPSP_DMYSTOP_BITS 2
144 #define SSPSP_DMYSTOP_MASK MASK(SSPSP_DMYSTOP_BITS - 1, 0)
145 #define SSPSP_FSRT BIT(25)
146 #define SSPSP_EDMYSTOP(x) SET_BITS(28, 26, x)
147
148 #define SSPSP2 0x44
149 #define SSPSP2_FEP_MASK 0xff
150
151 #if CONFIG_CAVS
152 #define SSCR3 0x48
153 #define SSIOC 0x4C
154
155 #define SSP_REG_MAX SSIOC
156 #endif
157
158 /* SSTSA bits */
159 #define SSTSA_SSTSA(x) SET_BITS(7, 0, x)
160 #define SSTSA_GET(x) ((x) & MASK(7, 0))
161 #define SSTSA_TXEN BIT(8)
162
163 /* SSRSA bits */
164 #define SSRSA_SSRSA(x) SET_BITS(7, 0, x)
165 #define SSRSA_GET(x) ((x) & MASK(7, 0))
166 #define SSRSA_RXEN BIT(8)
167
168 /* SSCR3 bits */
169 #define SSCR3_FRM_MST_EN BIT(0)
170 #define SSCR3_I2S_MODE_EN BIT(1)
171 #define SSCR3_I2S_FRM_POL(x) SET_BIT(2, x)
172 #define SSCR3_I2S_TX_SS_FIX_EN BIT(3)
173 #define SSCR3_I2S_RX_SS_FIX_EN BIT(4)
174 #define SSCR3_I2S_TX_EN BIT(9)
175 #define SSCR3_I2S_RX_EN BIT(10)
176 #define SSCR3_CLK_EDGE_SEL BIT(12)
177 #define SSCR3_STRETCH_TX BIT(14)
178 #define SSCR3_STRETCH_RX BIT(15)
179 #define SSCR3_MST_CLK_EN BIT(16)
180 #define SSCR3_SYN_FIX_EN BIT(17)
181
182 /* SSCR4 bits */
183 #define SSCR4_TOT_FRM_PRD(x) ((x) << 7)
184
185 /* SSCR5 bits */
186 #define SSCR5_FRM_ASRT_CLOCKS(x) (((x) - 1) << 1)
187 #define SSCR5_FRM_POLARITY(x) SET_BIT(0, x)
188
189 /* SFIFOTT bits */
190 #define SFIFOTT_TX(x) ((x) - 1)
191 #define SFIFOTT_RX(x) (((x) - 1) << 16)
192
193 /* SFIFOL bits */
194 #define SFIFOL_TFL(x) ((x) & 0xFFFF)
195 #define SFIFOL_RFL(x) ((x) >> 16)
196
197 #if CONFIG_CAVS || CONFIG_HASWELL || CONFIG_BROADWELL
198 #define SSTSA_TSEN BIT(8)
199 #define SSRSA_RSEN BIT(8)
200
201 #define SSCR3_TFL_MASK MASK(5, 0)
202 #define SSCR3_RFL_MASK MASK(13, 8)
203 #define SSCR3_TFL_VAL(scr3_val) (((scr3_val) >> 0) & MASK(5, 0))
204 #define SSCR3_RFL_VAL(scr3_val) (((scr3_val) >> 8) & MASK(5, 0))
205 #define SSCR3_TX(x) SET_BITS(21, 16, (x) - 1)
206 #define SSCR3_RX(x) SET_BITS(29, 24, (x) - 1)
207
208 #define SSIOC_TXDPDEB BIT(1)
209 #define SSIOC_SFCR BIT(4)
210 #define SSIOC_SCOE BIT(5)
211 #endif
212
213 #if CONFIG_CAVS
214
215 #include <sof/lib/clk.h>
216
217 /* max possible index in ssp_freq array */
218 #define MAX_SSP_FREQ_INDEX (NUM_SSP_FREQ - 1)
219
220 #endif
221
222 /* For 8000 Hz rate one sample is transmitted within 125us */
223 #define SSP_MAX_SEND_TIME_PER_SAMPLE 125
224
225 /* SSP flush retry counts maximum */
226 #define SSP_RX_FLUSH_RETRY_MAX 16
227
228 #define ssp_irq(ssp) \
229 ssp->plat_data.irq
230
231 #define SSP_CLK_MCLK_ES_REQ BIT(0)
232 #define SSP_CLK_MCLK_ACTIVE BIT(1)
233 #define SSP_CLK_BCLK_ES_REQ BIT(2)
234 #define SSP_CLK_BCLK_ACTIVE BIT(3)
235
236 /* SSP private data */
237 struct ssp_pdata {
238 uint32_t sscr0;
239 uint32_t sscr1;
240 uint32_t psp;
241 uint32_t state[2]; /* SSP_STATE_ for each direction */
242 uint32_t clk_active;
243 struct sof_ipc_dai_config config;
244 struct sof_ipc_dai_ssp_params params;
245 };
246
ssp_write(struct dai * dai,uint32_t reg,uint32_t value)247 static inline void ssp_write(struct dai *dai, uint32_t reg, uint32_t value)
248 {
249 dai_write(dai, reg, value);
250 }
251
ssp_read(struct dai * dai,uint32_t reg)252 static inline uint32_t ssp_read(struct dai *dai, uint32_t reg)
253 {
254 return dai_read(dai, reg);
255 }
256
ssp_update_bits(struct dai * dai,uint32_t reg,uint32_t mask,uint32_t value)257 static inline void ssp_update_bits(struct dai *dai, uint32_t reg, uint32_t mask,
258 uint32_t value)
259 {
260 dai_update_bits(dai, reg, mask, value);
261 }
262
263 #endif /* __SOF_DRIVERS_SSP_H__ */
264
