1 /* 2 * Copyright(c) 2022 AMD 3 * SPDX-License-Identifier: Apache-2.0 4 * 5 * Author: Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com> 6 * DineshKumar Kalva <dineshkumar.kalva@amd.com> 7 */ 8 #ifndef ZEPHYR_SOC_AMD_ADSP_MEMORY_H_ 9 #define ZEPHYR_SOC_AMD_ADSP_MEMORY_H_ 10 11 #define PLATFORM_CORE_COUNT 1 12 #define PLATFORM_PRIMARY_CORE_ID 0 13 14 #define IRAM_BASE 0x7F000000 15 #define IRAM_SIZE 0x60000 16 17 #define IRAM_RESERVE_HEADER_SPACE 0x400 18 19 #define MEM_RESET_TEXT_SIZE 0x400 20 #define MEM_RESET_LIT_SIZE 0x8 21 #define XCHAL_RESET_VECTOR_PADDR_IRAM 0x7F000000 22 #define XCHAL_WINDOW_VECTORS_PADDR_IRAM 0x7F000400 23 24 #define XCHAL_VECBASE_RESET_PADDR_IRAM (IRAM_BASE + IRAM_RESERVE_HEADER_SPACE) 25 26 #define MEM_VECBASE_LIT_SIZE 0x178 27 #define MEM_WIN_TEXT_SIZE 0x178 28 29 /* Vector and literal sizes - not in core-isa.h */ 30 #define MEM_VECT_LIT_SIZE 0x7 31 #define MEM_VECT_TEXT_SIZE 0x37 32 33 #define XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x180) 34 35 #define XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1C0) 36 37 #define XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x200) 38 39 #define XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x240) 40 41 #define XCHAL_INTLEVEL6_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x280) 42 43 #define XCHAL_INTLEVEL7_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x2C0) 44 45 #define XCHAL_KERNEL_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x300) 46 47 #define XCHAL_USER_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x340) 48 49 #define XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x3C0) 50 51 /* Location for the intList section which is later used to construct the 52 * Interrupt Descriptor Table (IDT). This is a bogus address as this 53 * section will be stripped off in the final image. 54 */ 55 #define IDT_BASE (IRAM_BASE + IRAM_SIZE) 56 /* size of the Interrupt Descriptor Table (IDT) */ 57 #define IDT_SIZE 0x2000 58 /* physical DSP addresses */ 59 #define IRAM_BASE 0x7F000000 60 #define IRAM_SIZE 0x60000 /* 384K */ 61 #define SRAM0_BASE 0x9FF00000 /* Scratch mem */ 62 #define SRAM1_BASE 0x60006000 63 #define SRAM1_SIZE 0x80000 /* 256K Data Mem */ 64 #define DRAM0_BASE 0xE0000000 65 #define DRAM0_SIZE 0x20000 /* 128K ,to use for heap mem */ 66 #define DMA0_BASE PU_REGISTER_BASE 67 #define DMA0_SIZE 0x4 68 #define PU_REGISTER_BASE (0x9FD00000 - 0x01240000) 69 #define ACP_I2S_RX_RINGBUFADDR 0x1242000 70 /* DAI DMA register base address */ 71 #define DAI_BASE (PU_REGISTER_BASE + ACP_I2S_RX_RINGBUFADDR) 72 #define DAI_BASE_REM (PU_REGISTER_BASE + ACP_P1_I2S_RX_RINGBUFADDR) 73 #define DAI_SIZE 0x4 74 #define BT_TX_FIFO_OFFST (ACP_P1_BT_TX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR) 75 #define BT_RX_FIFO_OFFST (ACP_P1_BT_RX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR) 76 #define HS_TX_FIFO_OFFST (ACP_P1_HS_TX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR) 77 #define HS_RX_FIFO_OFFST (ACP_P1_HS_TX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR) 78 #define UUID_ENTRY_ELF_BASE 0x1FFFA000 79 #define UUID_ENTRY_ELF_SIZE \ 80 0x6000 /* Log buffer base need to be updated properly, these are used in linker scripts \ 81 */ 82 #define LOG_ENTRY_ELF_BASE 0x20000000 83 #define LOG_ENTRY_ELF_SIZE 0x2000000 84 #define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE) 85 #define EXT_MANIFEST_ELF_SIZE 0x2000000 /* Stack configuration */ 86 #define SOF_STACK_SIZE 0x1000 87 #define SOF_STACK_TOTAL_SIZE SOF_STACK_SIZE 88 #define SOF_STACK_END (DRAM0_BASE + DRAM0_SIZE) 89 #define SOF_STACK_BASE (SOF_STACK_END + SOF_STACK_SIZE) /* Mailbox configuration */ 90 #define SRAM_OUTBOX_BASE SRAM0_BASE 91 #define SRAM_OUTBOX_SIZE 0x400 92 #define SRAM_OUTBOX_OFFSET 0 93 #define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE) 94 #define SRAM_INBOX_SIZE 0x400 95 #define SRAM_INBOX_OFFSET SRAM_OUTBOX_SIZE 96 #define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) 97 #define SRAM_DEBUG_SIZE 0x400 98 #define SRAM_DEBUG_OFFSET (SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE) 99 #define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) 100 #define SRAM_EXCEPT_SIZE 0x400 101 #define SRAM_EXCEPT_OFFSET (SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE) 102 #define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) 103 #define SRAM_STREAM_SIZE 0x400 104 #define SRAM_STREAM_OFFSET (SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE) 105 #define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) 106 #define SRAM_TRACE_SIZE 0x400 107 #define SRAM_TRACE_OFFSET (SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE) 108 #define SOF_MAILBOX_SIZE \ 109 (SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE + SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE + \ 110 SRAM_STREAM_SIZE + SRAM_TRACE_SIZE) 111 /* Heap section sizes for module pool */ 112 #define HEAP_RT_COUNT8 0 113 #define HEAP_RT_COUNT16 48 114 #define HEAP_RT_COUNT32 48 115 #define HEAP_RT_COUNT64 32 116 #define HEAP_RT_COUNT128 60 117 #define HEAP_RT_COUNT256 32 118 #define HEAP_RT_COUNT512 4 119 #define HEAP_RT_COUNT1024 12 120 #define HEAP_RT_COUNT2048 12 121 /* Heap section sizes for system runtime heap */ 122 #define HEAP_SYS_RT_COUNT64 64 123 #define HEAP_SYS_RT_COUNT512 20 /*rembrandt-arch*/ 124 #define HEAP_SYS_RT_COUNT1024 6 125 /* Heap configuration */ 126 #define HEAP_SYSTEM_BASE DRAM0_BASE /* SRAM1_BASE */ 127 #define HEAP_SYSTEM_SIZE 0xE000 128 #define HEAP_SYSTEM_0_BASE HEAP_SYSTEM_BASE 129 #define HEAP_SYS_RUNTIME_BASE (HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE) 130 #define HEAP_SYS_RUNTIME_SIZE \ 131 (HEAP_SYS_RT_COUNT64 * 64 + HEAP_SYS_RT_COUNT512 * 512 + HEAP_SYS_RT_COUNT1024 * 1024) 132 #define HEAP_RUNTIME_BASE (HEAP_SYS_RUNTIME_BASE + HEAP_SYS_RUNTIME_SIZE) 133 #define HEAP_RUNTIME_SIZE \ 134 (HEAP_RT_COUNT8 * 8 + HEAP_RT_COUNT16 * 16 + HEAP_RT_COUNT32 * 32 + HEAP_RT_COUNT64 * 64 + \ 135 HEAP_RT_COUNT128 * 128 + HEAP_RT_COUNT256 * 256 + HEAP_RT_COUNT512 * 512 + \ 136 HEAP_RT_COUNT1024 * 1024 + HEAP_RT_COUNT2048 * 2048) 137 #define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE) 138 #define HEAP_BUFFER_SIZE (0xF000) 139 #define HEAP_BUFFER_BLOCK_SIZE 0x180 140 #define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE) 141 #define PLATFORM_HEAP_SYSTEM 1 142 #define PLATFORM_HEAP_SYSTEM_RUNTIME 1 143 #define PLATFORM_HEAP_RUNTIME 1 144 #define PLATFORM_HEAP_BUFFER 1 145 /* Vector and literal sizes - not in core-isa.h */ 146 #define SOF_MEM_VECT_LIT_SIZE 0x7 147 #define SOF_MEM_VECT_TEXT_SIZE 0x37 148 #define SOF_MEM_VECT_SIZE (SOF_MEM_VECT_TEXT_SIZE + SOF_MEM_VECT_LIT_SIZE) 149 #define SOF_MEM_RESET_TEXT_SIZE 0x400 150 #define SOF_MEM_RESET_LIT_SIZE 0x8 151 #define SOF_MEM_VECBASE_LIT_SIZE 0x178 152 #define SOF_MEM_WIN_TEXT_SIZE 0x178 153 #define SOF_MEM_RO_SIZE 0x8 154 #define uncache_to_cache(address) address 155 #define cache_to_uncache(address) address 156 #define is_uncached(address) 0 157 #define HEAP_BUF_ALIGNMENT PLATFORM_DCACHE_ALIGN 158 /* brief EDF task's default stack size in bytes */ 159 #define PLATFORM_TASK_DEFAULT_STACK_SIZE 3072 160 #endif /* ZEPHYR_SOC_AMD_ADSP_MEMORY_H_ */ 161
