1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2016 Intel Corporation. All rights reserved. 4 * 5 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 6 * Keyon Jie <yang.jie@linux.intel.com> 7 */ 8 9 #ifdef __SOF_LIB_SHIM_H__ 10 11 #ifndef __PLATFORM_LIB_SHIM_H__ 12 #define __PLATFORM_LIB_SHIM_H__ 13 14 #include <cavs/lib/shim.h> 15 #include <sof/bit.h> 16 #include <sof/lib/memory.h> 17 18 /* DSP IPC for Host Registers */ 19 #define IPC_DIPCT 0x00 20 #define IPC_DIPCTE 0x04 21 #define IPC_DIPCI 0x08 22 #define IPC_DIPCIE 0x0c 23 #define IPC_DIPCCTL 0x10 24 25 /* DIPCT */ 26 #define IPC_DIPCT_BUSY BIT(31) 27 #define IPC_DIPCT_MSG_MASK 0x7FFFFFFF 28 29 /* DIPCTE */ 30 #define IPC_DIPCTE_MSG_MASK 0x3FFFFFFF 31 32 /* DIPCI */ 33 #define IPC_DIPCI_BUSY BIT(31) 34 #define IPC_DIPCI_MSG_MASK 0x7FFFFFFF 35 36 /* DIPCIE */ 37 #define IPC_DIPCIE_DONE BIT(30) 38 #define IPC_DIPCIE_MSG_MASK 0x3FFFFFFF 39 40 /* DIPCCTL */ 41 #define IPC_DIPCCTL_IPCIDIE BIT(1) 42 #define IPC_DIPCCTL_IPCTBIE BIT(0) 43 44 #define IPC_DSP_OFFSET 0x10 45 46 /* DSP IPC for intra DSP communication */ 47 #define IPC_IDCTFC(x) (0x0 + x * IPC_DSP_OFFSET) 48 #define IPC_IDCTEFC(x) (0x4 + x * IPC_DSP_OFFSET) 49 #define IPC_IDCITC(x) (0x8 + x * IPC_DSP_OFFSET) 50 #define IPC_IDCIETC(x) (0xc + x * IPC_DSP_OFFSET) 51 #define IPC_IDCCTL 0x50 52 53 /* IDCTFC */ 54 #define IPC_IDCTFC_BUSY BIT(31) 55 #define IPC_IDCTFC_MSG_MASK 0x7FFFFFFF 56 57 /* IDCTEFC */ 58 #define IPC_IDCTEFC_MSG_MASK 0x3FFFFFFF 59 60 /* IDCITC */ 61 #define IPC_IDCITC_BUSY BIT(31) 62 #define IPC_IDCITC_MSG_MASK 0x7FFFFFFF 63 64 /* IDCIETC */ 65 #define IPC_IDCIETC_DONE BIT(30) 66 #define IPC_IDCIETC_MSG_MASK 0x3FFFFFFF 67 68 /* IDCCTL */ 69 #define IPC_IDCCTL_IDCIDIE(x) (0x100 << (x)) 70 #define IPC_IDCCTL_IDCTBIE(x) BIT(x) 71 72 #define IRQ_CPU_OFFSET 0x40 73 74 #define REG_IRQ_IL2MSD(xcpu) (0x0 + (xcpu * IRQ_CPU_OFFSET)) 75 #define REG_IRQ_IL2MCD(xcpu) (0x4 + (xcpu * IRQ_CPU_OFFSET)) 76 #define REG_IRQ_IL2MD(xcpu) (0x8 + (xcpu * IRQ_CPU_OFFSET)) 77 #define REG_IRQ_IL2SD(xcpu) (0xc + (xcpu * IRQ_CPU_OFFSET)) 78 79 /* all mask valid bits */ 80 #define REG_IRQ_IL2MD_ALL 0x03F181F0 81 82 #define REG_IRQ_IL3MSD(xcpu) (0x10 + (xcpu * IRQ_CPU_OFFSET)) 83 #define REG_IRQ_IL3MCD(xcpu) (0x14 + (xcpu * IRQ_CPU_OFFSET)) 84 #define REG_IRQ_IL3MD(xcpu) (0x18 + (xcpu * IRQ_CPU_OFFSET)) 85 #define REG_IRQ_IL3SD(xcpu) (0x1c + (xcpu * IRQ_CPU_OFFSET)) 86 87 /* all mask valid bits */ 88 #define REG_IRQ_IL3MD_ALL 0x807F81FF 89 90 #define REG_IRQ_IL4MSD(xcpu) (0x20 + (xcpu * IRQ_CPU_OFFSET)) 91 #define REG_IRQ_IL4MCD(xcpu) (0x24 + (xcpu * IRQ_CPU_OFFSET)) 92 #define REG_IRQ_IL4MD(xcpu) (0x28 + (xcpu * IRQ_CPU_OFFSET)) 93 #define REG_IRQ_IL4SD(xcpu) (0x2c + (xcpu * IRQ_CPU_OFFSET)) 94 95 /* all mask valid bits */ 96 #define REG_IRQ_IL4MD_ALL 0x807F81FF 97 98 #define REG_IRQ_IL5MSD(xcpu) (0x30 + (xcpu * IRQ_CPU_OFFSET)) 99 #define REG_IRQ_IL5MCD(xcpu) (0x34 + (xcpu * IRQ_CPU_OFFSET)) 100 #define REG_IRQ_IL5MD(xcpu) (0x38 + (xcpu * IRQ_CPU_OFFSET)) 101 #define REG_IRQ_IL5SD(xcpu) (0x3c + (xcpu * IRQ_CPU_OFFSET)) 102 103 /* all mask valid bits */ 104 #define REG_IRQ_IL5MD_ALL 0xFFFFC0CF 105 106 #define REG_IRQ_IL2RSD 0x100 107 #define REG_IRQ_IL3RSD 0x104 108 #define REG_IRQ_IL4RSD 0x108 109 #define REG_IRQ_IL5RSD 0x10c 110 111 #define REG_IRQ_LVL5_LP_GPDMA0_MASK (0xff << 16) 112 #define REG_IRQ_LVL5_LP_GPDMA1_MASK (0xff << 24) 113 114 /* DSP Shim Registers */ 115 #define SHIM_DSPWC 0x20 /* DSP Wall Clock */ 116 #define SHIM_DSPWCL 0x20 /* DSP Wall Clock Low */ 117 #define SHIM_DSPWCH 0x24 /* DSP Wall Clock High */ 118 #define SHIM_DSPWCTCS 0x28 /* DSP Wall Clock Timer Control & Status */ 119 #define SHIM_DSPWCT0C 0x30 /* DSP Wall Clock Timer 0 Compare */ 120 #define SHIM_DSPWCT1C 0x38 /* DSP Wall Clock Timer 1 Compare */ 121 122 #define SHIM_DSPWCTCS_T1T BIT(5) /* Timer 1 triggered */ 123 #define SHIM_DSPWCTCS_T0T BIT(4) /* Timer 0 triggered */ 124 #define SHIM_DSPWCTCS_T1A BIT(1) /* Timer 1 armed */ 125 #define SHIM_DSPWCTCS_T0A BIT(0) /* Timer 0 armed */ 126 127 /** \brief Clock control */ 128 #define SHIM_CLKCTL 0x78 129 130 /** \brief Clock status */ 131 #define SHIM_CLKSTS 0x7C 132 133 /** \brief Request Audio PLL Clock */ 134 #define SHIM_CLKCTL_RAPLLC BIT(31) 135 136 /** \brief Request XTAL Oscillator Clock */ 137 #define SHIM_CLKCTL_RXOSCC BIT(30) 138 139 /** \brief Request Fast RING Oscillator Clock */ 140 #define SHIM_CLKCTL_RFROSCC BIT(29) 141 142 /** \brief LP GPDMA Force Dynamic Clock Gating bits, 0: enable */ 143 #define SHIM_CLKCTL_LPGPDMAFDCGB(x) BIT(26 + x) 144 145 /** \brief DMIC Force Dynamic Clock Gating */ 146 #define SHIM_CLKCTL_DMICFDCGB BIT(24) 147 148 /** \brief I2S Force Dynamic Clock Gating */ 149 #define SHIM_CLKCTL_I2SFDCGB(x) BIT(20 + x) 150 151 /** \brief I2S Extension Force Dynamic Clock Gating */ 152 #define SHIM_CLKCTL_I2SEFDCGB(x) BIT(18 + x) 153 154 /** \brief Tensilica Core Prevent Local Clock Gating */ 155 #define SHIM_CLKCTL_TCPLCG_EN(x) BIT(16 + (x)) 156 #define SHIM_CLKCTL_TCPLCG_DIS(x) 0 157 158 /** \brief Core clock PLL divisor */ 159 #define SHIM_CLKCTL_DPCS_MASK(x) (0x3 << (8 + x * 2)) 160 #define SHIM_CLKCTL_DPCS_DIV1(x) (0x0 << (8 + x * 2)) 161 #define SHIM_CLKCTL_DPCS_DIV2(x) (0x1 << (8 + x * 2)) 162 #define SHIM_CLKCTL_DPCS_DIV4(x) (0x3 << (8 + x * 2)) 163 164 /** \brief Tensilica Core Prevent Audio PLL Shutdown */ 165 #define SHIM_CLKCTL_TCPAPLLS_EN BIT(7) 166 #define SHIM_CLKCTL_TCPAPLLS_DIS 0 167 168 /** \brief LP domain clock select, 0: PLL, 1: oscillator */ 169 #define SHIM_CLKCTL_LDCS_XTAL BIT(5) 170 #define SHIM_CLKCTL_LDCS_PLL 0 171 172 /** \brief HP domain clock select */ 173 #define SHIM_CLKCTL_HDCS BIT(4) 174 #define SHIM_CLKCTL_HDCS_XTAL BIT(4) 175 #define SHIM_CLKCTL_HDCS_PLL 0 176 177 /** \brief LP domain oscillator clock select select, 0: XTAL, 1: Fast RING */ 178 #define SHIM_CLKCTL_LDOCS BIT(3) 179 180 /** \brief HP domain oscillator clock select select, 0: XTAL, 1: Fast RING */ 181 #define SHIM_CLKCTL_HDOCS BIT(2) 182 183 /** \brief LP memory clock PLL divisor, 0: div by 2, 1: div by 4 */ 184 #define SHIM_CLKCTL_LPMPCS_DIV4 BIT(1) 185 #define SHIM_CLKCTL_LPMPCS_DIV2 0 186 187 /** \brief HP memory clock PLL divisor, 0: div by 2, 1: div by 4 */ 188 #define SHIM_CLKCTL_HPMPCS_DIV4 BIT(0) 189 #define SHIM_CLKCTL_HPMPCS_DIV2 0 190 191 #define SHIM_PWRCTL 0x90 192 #define SHIM_PWRSTS 0x92 193 #define SHIM_LPSCTL 0x94 194 195 /* HP & LP SRAM Power Gating */ 196 #define SHIM_HSPGCTL 0x80 197 #define SHIM_LSPGCTL 0x84 198 #define SHIM_SPSREQ 0xa0 199 #define LSPGCTL (SHIM_BASE + SHIM_LSPGCTL) 200 201 #define SHIM_SPSREQ_RVNNP BIT(0) 202 203 /** \brief GPDMA shim registers Control */ 204 #define SHIM_GPDMA_BASE_OFFSET 0xC00 205 #define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x80) 206 207 /** \brief GPDMA Channel Linear Link Position Control */ 208 #define SHIM_GPDMA_CHLLPC(x, y) (SHIM_GPDMA_BASE(x) + (y) * 0x10) 209 #define SHIM_GPDMA_CHLLPC_EN BIT(5) 210 #define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(4, 0, x) 211 212 /** \brief LDO Control */ 213 #define SHIM_LDOCTL 0xA4 214 #define SHIM_LDOCTL_HPSRAM_MASK (3 << 0) 215 #define SHIM_LDOCTL_LPSRAM_MASK (3 << 2) 216 #define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0) 217 #define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2) 218 #define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0) 219 #define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2) 220 #define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0) 221 #define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2) 222 223 #define SHIM_HSPGISTS 0xb0 224 #define SHIM_LSPGISTS 0xb4 225 #define LSPGISTS (SHIM_BASE + SHIM_LSPGISTS) 226 227 #define SHIM_LPSCTL_FDSPRUN BIT(9) 228 #define SHIM_LPSCTL_FDMARUN BIT(8) 229 230 #define SHIM_L2_MECS (SHIM_BASE + 0xd0) 231 232 #define SHIM_LPGPDMAC(x) (0x1110 + (2 * x)) 233 #define SHIM_LPGPDMAC_CTLOSEL BIT(15) 234 #define SHIM_LPGPDMAC_CHOSEL 0xFF 235 236 #define SHIM_DSPIOPO 0x1118 237 #define SHIM_DSPIOPO_DMICOSEL BIT(0) 238 #define SHIM_DSPIOPO_I2SOSEL (0x3F << 8) 239 240 #define SHIM_GENO 0x111C 241 #define SHIM_GENO_SHIMOSEL BIT(0) 242 #define SHIM_GENO_MDIVOSEL BIT(1) 243 #define SHIM_GENO_DIOPTOSEL BIT(2) 244 245 #define SHIM_L2_CACHE_CTRL (SHIM_BASE + 0x500) 246 #define SHIM_L2_PREF_CFG (SHIM_BASE + 0x508) 247 #define SHIM_L2_CACHE_PREF (SHIM_BASE + 0x510) 248 249 #define SHIM_SVCFG 0xF4 250 #define SHIM_SVCFG_FORCE_L1_EXIT BIT(1) 251 252 /* host windows */ 253 #define DMWBA(x) (HOST_WIN_BASE(x) + 0x0) 254 #define DMWLO(x) (HOST_WIN_BASE(x) + 0x4) 255 256 #define DMWBA_ENABLE BIT(0) 257 #define DMWBA_READONLY BIT(1) 258 259 #endif /* __PLATFORM_LIB_SHIM_H__ */ 260 261 #else 262 263 #error "This file shouldn't be included from outside of sof/lib/shim.h" 264 265 #endif /* __SOF_LIB_SHIM_H__ */ 266
