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Searched refs:MASK (Results 1 – 22 of 22) sorted by relevance

/sof-2.7.6/src/include/sof/drivers/
Desai.h77 #define ESAI_xFCR_xWA_MASK MASK(18, 16)
81 #define ESAI_xFCR_xFWM_MASK MASK(15, 8)
86 #define ESAI_xFCR_TE_MASK MASK(7, 2)
87 #define ESAI_xFCR_RE_MASK MASK(5, 2)
89 #define ESAI_xFCR_TE(x) SET_BITS(7, 2, MASK((x) - 1, 0))
90 #define ESAI_xFCR_RE(x) SET_BITS(5, 2, MASK((x) - 1, 0))
99 #define ESAI_xFSR_NTFO_MASK MASK(14, 12)
100 #define ESAI_xFSR_NTFI_MASK MASK(10, 8)
101 #define ESAI_xFSR_NRFO_MASK MASK(9, 8)
102 #define ESAI_xFSR_NRFI_MASK MASK(13, 12)
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Dsai.h111 #define REG_SAI_CSR_XF_MASK MASK(REG_SAI_CSR_XF_SHIFT + 4, \
113 #define REG_SAI_CSR_XF_W_MASK MASK(REG_SAI_CSR_XF_W_SHIFT + 2,\
121 #define REG_SAI_CSR_XIE_MASK MASK(REG_SAI_CSR_XIE_SHIFT + 4,\
140 #define REG_SAI_CR2_SYNC_MASK MASK(31, 30)
141 #define REG_SAI_CR2_MSEL_MASK MASK(27, 26)
153 #define REG_SAI_CR3_TRCE_MASK MASK(23, 16)
163 #define REG_SAI_CR4_FCOMB_MASK MASK(27, 26)
167 #define REG_SAI_CR4_FRSZ_MASK MASK(20, 16)
169 #define REG_SAI_CR4_SYWD_MASK MASK(12, 8)
179 #define REG_SAI_CR5_WNW_MASK MASK(28, 24)
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Dssp.h54 #define SSCR0_DSIZE_GET(x) (((x) & MASK(3, 0)) + 1)
55 #define SSCR0_FRF MASK(5, 4)
62 #define SSCR0_SCR_MASK MASK(19, 8)
69 #define SSCR0_FRDC_GET(x) ((((x) & MASK(26, 24)) >> 24) + 1)
80 #define SSCR1_TFT_MASK MASK(9, 6)
82 #define SSCR1_RFT_MASK MASK(13, 10)
144 #define SSPSP_DMYSTOP_MASK MASK(SSPSP_DMYSTOP_BITS - 1, 0)
160 #define SSTSA_GET(x) ((x) & MASK(7, 0))
165 #define SSRSA_GET(x) ((x) & MASK(7, 0))
201 #define SSCR3_TFL_MASK MASK(5, 0)
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Dsdma.h42 #define SDMA_CONFIG_CSM_MSK MASK(1, 0)
94 #define SDMA_BD_COUNT_MASK MASK(15, 0)
118 #define SDMA_BD_CMD_MASK MASK(31, 24)
Ddw-dma.h65 #define DW_CHAN_WRITE_EN_ALL MASK(2 * DW_MAX_CHAN - 1, DW_MAX_CHAN)
67 #define DW_CHAN_ALL MASK(DW_MAX_CHAN - 1, 0)
103 #define DW_CTLL_SRC_WIDTH_MASK MASK(6, 4)
105 #define DW_CTLL_DST_WIDTH_MASK MASK(3, 1)
Dedma.h81 #define EDMA_HS_GET_IRQ(hs) (((hs) & MASK(8, 0)) >> 0)
83 #define EDMA_HS_GET_CHAN(hs) (((hs) & MASK(13, 9)) >> 9)
Ddmic.h274 #define OUTSTAT0_FL_MASK MASK(6, 0)
281 #define OUTSTAT1_FL_MASK MASK(6, 0)
313 #define CIC_CONFIG_CIC_SHIFT_MASK MASK(27, 24)
314 #define CIC_CONFIG_COMB_COUNT_MASK MASK(15, 8)
329 #define MIC_CONTROL_PDM_CLKDIV_MASK MASK(15, 8)
/sof-2.7.6/src/platform/intel/cavs/include/cavs/drivers/
Dsideband-ipc.h22 #define IPC_DIPCTDR_MSG_MASK MASK(30, 0)
26 #define IPC_DIPCTDA_MSG_MASK MASK(30, 0)
29 #define IPC_DIPCTDD_MSG_MASK MASK(30, 0)
33 #define IPC_DIPCIDA_MSG_MASK MASK(30, 0)
37 #define IPC_DIPCIDR_MSG_MASK MASK(30, 0)
40 #define IPC_DIPCIDD_MSG_MASK MASK(31, 0)
Ddw-dma.h36 #define DW_CTLH_BLOCK_TS_MASK MASK(16, 0)
/sof-2.7.6/src/include/ipc/
Dprobe.h74 #define PROBE_MASK_FMT_TYPE MASK(31, 31)
75 #define PROBE_MASK_STANDARD_TYPE MASK(30, 27)
76 #define PROBE_MASK_AUDIO_FMT MASK(26, 23)
77 #define PROBE_MASK_SAMPLE_RATE MASK(22, 19)
78 #define PROBE_MASK_NB_CHANNELS MASK(18, 14)
79 #define PROBE_MASK_SAMPLE_SIZE MASK(13, 12)
80 #define PROBE_MASK_CONTAINER_SIZE MASK(11, 10)
81 #define PROBE_MASK_SAMPLE_FMT MASK(9, 9)
82 #define PROBE_MASK_SAMPLE_END MASK(8, 8)
83 #define PROBE_MASK_INTERLEAVING_ST MASK(7, 7)
Dheader-intel-cavs.h39 #define CAVS_IPC_TYPE_MASK MASK(28, 24)
45 #define CAVS_IPC_MOD_INSTANCE_ID_MASK MASK(23, 16)
48 #define CAVS_IPC_MOD_ID_MASK MASK(15, 0)
79 #define CAVS_IPC_MOD_SETD0IX_BIT_MASK MASK(7, 0)
/sof-2.7.6/src/include/sof/
Dbit.h22 #define MASK(b_hi, b_lo) \ macro
30 (((x) & MASK(b_hi, b_lo)) >> (b_lo))
/sof-2.7.6/src/platform/intel/cavs/include/cavs/lib/
Dpm_memory.h60 return MASK(end_bank - first_in_segment, start_bank - first_in_segment); in cavs_pm_memory_hp_sram_mask_get()
132 uint32_t mask = MASK(ending_bank_id, start_bank_id); in cavs_pm_memory_lp_sram_banks_power_gate()
173 uint32_t mask = MASK(start_bank_id, ending_bank_id); in cavs_pm_memory_l1_dram_banks_power_gate()
Dpm_runtime.h23 #define PWRD_MASK MASK(31, 30)
/sof-2.7.6/src/platform/haswell/include/platform/drivers/
Ddw-dma.h30 #define DW_CTLH_BLOCK_TS_MASK MASK(11, 0)
/sof-2.7.6/src/platform/baytrail/include/platform/drivers/
Ddw-dma.h37 #define DW_CTLH_BLOCK_TS_MASK MASK(16, 0)
/sof-2.7.6/src/platform/icelake/include/platform/lib/
Dshim.h246 #define IOPO_I2S_FLAG MASK(DAI_NUM_SSP_BASE + DAI_NUM_SSP_EXT + 7, 8)
/sof-2.7.6/src/platform/tigerlake/include/platform/lib/
Dshim.h262 #define IOPO_I2S_FLAG MASK(DAI_NUM_SSP_BASE + DAI_NUM_SSP_EXT + 7, 8)
/sof-2.7.6/src/audio/pcm_converter/
Dpcm_converter_generic.c214 mantissa = BIT(23) | (MASK(22, 0) & src); /* mantisa + 1.0 [Q9.22] */ in _pcm_convert_f_to_i()
253 mantissa = _pcm_shift(mantissa, 23 - 31 + abs_clz) & MASK(22, 0); in _pcm_convert_i_to_f()
/sof-2.7.6/test/cmocka/src/audio/pcm_converter/
Dpcm_float.c269 mask_array(MASK(24, 0), source_buf, N); in test_pcm_convert_s24_to_f()
/sof-2.7.6/src/drivers/imx/
Dsdma.c174 dma_reg_write(dma, SDMA_INTR, MASK(31, 0)); in sdma_register_init()
/sof-2.7.6/src/ipc/ipc3/
Dhandler.c653 if (pm_core_config.enable_mask > MASK(CONFIG_CORE_COUNT - 1, 0)) { in ipc_pm_core_enable()