1 /* SPDX-License-Identifier: BSD-3-Clause
2 *
3 * Copyright(c) 2017 Intel Corporation. All rights reserved.
4 *
5 * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
6 */
7
8 #ifndef __SOF_DRIVERS_DMIC_H__
9 #define __SOF_DRIVERS_DMIC_H__
10
11 #if CONFIG_INTEL_DMIC
12
13 /* Let find up to 50 mode candidates to choose from */
14 #define DMIC_MAX_MODES 50
15
16 /* Minimum OSR is always applied for 48 kHz and less sample rates */
17 #define DMIC_MIN_OSR 50
18
19 /* These are used as guideline for configuring > 48 kHz sample rates. The
20 * minimum OSR can be relaxed down to 40 (use 3.84 MHz clock for 96 kHz).
21 */
22 #define DMIC_HIGH_RATE_MIN_FS 64000
23 #define DMIC_HIGH_RATE_OSR_MIN 40
24
25 /* HW FIR pipeline needs 5 additional cycles per channel for internal
26 * operations. This is used in MAX filter length check.
27 */
28 #define DMIC_FIR_PIPELINE_OVERHEAD 5
29
30 /* The microphones create a low frequecy thump sound when clock is enabled.
31 * The unmute linear gain ramp chacteristic is defined here.
32 * NOTE: Do not set any of these to 0.
33 */
34 #define DMIC_UNMUTE_RAMP_US 1000 /* 1 ms (in microseconds) */
35 #define DMIC_UNMUTE_CIC 1 /* Unmute CIC at 1 ms */
36 #define DMIC_UNMUTE_FIR 2 /* Unmute FIR at 2 ms */
37
38 #if CONFIG_APOLLOLAKE
39 #define DMIC_HW_VERSION 1
40 #define DMIC_HW_CONTROLLERS 2
41 #define DMIC_HW_IOCLK 19200000
42 #define DMIC_HW_FIFOS 2
43 #endif
44
45 #if CONFIG_CANNONLAKE
46 #define DMIC_HW_VERSION 1
47 #define DMIC_HW_CONTROLLERS 2
48 #define DMIC_HW_IOCLK 24000000
49 #define DMIC_HW_FIFOS 2
50 #endif
51
52 #if CONFIG_SUECREEK
53 #define DMIC_HW_VERSION 2
54 #define DMIC_HW_CONTROLLERS 4
55 #define DMIC_HW_IOCLK 19200000
56 #define DMIC_HW_FIFOS 2
57 #endif
58
59 #if CONFIG_ICELAKE || CONFIG_TIGERLAKE
60 #define DMIC_HW_VERSION 1
61 #define DMIC_HW_CONTROLLERS 2
62 #define DMIC_HW_IOCLK 38400000
63 #define DMIC_HW_FIFOS 2
64 #endif
65
66 /* For NHLT DMIC configuration parsing */
67 #define DMIC_HW_CONTROLLERS_MAX 4
68 #define DMIC_HW_FIFOS_MAX 2
69
70 #endif
71
72 #if DMIC_HW_VERSION
73
74 #include <ipc/dai-intel.h>
75 #include <sof/audio/format.h>
76 #include <sof/bit.h>
77 #include <sof/lib/dai.h>
78 #include <sof/lib/wait.h>
79 #include <sof/schedule/task.h>
80 #include <stdint.h>
81
82 /* Parameters used in modes computation */
83 #define DMIC_HW_BITS_CIC 26
84 #define DMIC_HW_BITS_FIR_COEF 20
85 #define DMIC_HW_BITS_FIR_GAIN 20
86 #define DMIC_HW_BITS_FIR_INPUT 22
87 #define DMIC_HW_BITS_FIR_OUTPUT 24
88 #define DMIC_HW_BITS_FIR_INTERNAL 26
89 #define DMIC_HW_BITS_GAIN_OUTPUT 22
90 #define DMIC_HW_FIR_LENGTH_MAX 250
91 #define DMIC_HW_CIC_SHIFT_MIN -8
92 #define DMIC_HW_CIC_SHIFT_MAX 4
93 #define DMIC_HW_FIR_SHIFT_MIN 0
94 #define DMIC_HW_FIR_SHIFT_MAX 8
95 #define DMIC_HW_CIC_DECIM_MIN 5
96 #define DMIC_HW_CIC_DECIM_MAX 31 /* Note: Limited by BITS_CIC */
97 #define DMIC_HW_FIR_DECIM_MIN 2
98 #define DMIC_HW_FIR_DECIM_MAX 20 /* Note: Practical upper limit */
99 #define DMIC_HW_SENS_Q28 Q_CONVERT_FLOAT(1.0, 28) /* Q1.28 */
100 #define DMIC_HW_PDM_CLK_MIN 100000 /* Note: Practical min value */
101 #define DMIC_HW_DUTY_MIN 20 /* Note: Practical min value */
102 #define DMIC_HW_DUTY_MAX 80 /* Note: Practical max value */
103
104 /* DMIC register offsets */
105
106 /* Global registers */
107 #define OUTCONTROL0 0x0000
108 #define OUTSTAT0 0x0004
109 #define OUTDATA0 0x0008
110 #define OUTCONTROL1 0x0100
111 #define OUTSTAT1 0x0104
112 #define OUTDATA1 0x0108
113 #define PDM0 0x1000
114 #define PDM0_COEFFICIENT_A 0x1400
115 #define PDM0_COEFFICIENT_B 0x1800
116 #define PDM1 0x2000
117 #define PDM1_COEFFICIENT_A 0x2400
118 #define PDM1_COEFFICIENT_B 0x2800
119 #define PDM2 0x3000
120 #define PDM2_COEFFICIENT_A 0x3400
121 #define PDM2_COEFFICIENT_B 0x3800
122 #define PDM3 0x4000
123 #define PDM3_COEFFICIENT_A 0x4400
124 #define PDM3_COEFFICIENT_B 0x4800
125 #define PDM_COEF_RAM_A_LENGTH 0x0400
126 #define PDM_COEF_RAM_B_LENGTH 0x0400
127
128 /* Local registers in each PDMx */
129 #define CIC_CONTROL 0x000
130 #define CIC_CONFIG 0x004
131 #define MIC_CONTROL 0x00c
132 #define FIR_CONTROL_A 0x020
133 #define FIR_CONFIG_A 0x024
134 #define DC_OFFSET_LEFT_A 0x028
135 #define DC_OFFSET_RIGHT_A 0x02c
136 #define OUT_GAIN_LEFT_A 0x030
137 #define OUT_GAIN_RIGHT_A 0x034
138 #define FIR_CONTROL_B 0x040
139 #define FIR_CONFIG_B 0x044
140 #define DC_OFFSET_LEFT_B 0x048
141 #define DC_OFFSET_RIGHT_B 0x04c
142 #define OUT_GAIN_LEFT_B 0x050
143 #define OUT_GAIN_RIGHT_B 0x054
144
145 /* Register bits */
146
147 /* OUTCONTROLx IPM bit fields style */
148 #if DMIC_HW_VERSION == 1 || (DMIC_HW_VERSION == 2 && DMIC_HW_CONTROLLERS <= 2)
149 #define DMIC_IPM_VER1
150 #elif DMIC_HW_VERSION == 2 && DMIC_HW_CONTROLLERS > 2
151 #define DMIC_IPM_VER2
152 #else
153 #error Not supported HW version
154 #endif
155
156 #if defined DMIC_IPM_VER1
157 /* OUTCONTROL0 bits */
158 #define OUTCONTROL0_TIE_BIT BIT(27)
159 #define OUTCONTROL0_SIP_BIT BIT(26)
160 #define OUTCONTROL0_FINIT_BIT BIT(25)
161 #define OUTCONTROL0_FCI_BIT BIT(24)
162 #define OUTCONTROL0_TIE(x) SET_BIT(27, x)
163 #define OUTCONTROL0_SIP(x) SET_BIT(26, x)
164 #define OUTCONTROL0_FINIT(x) SET_BIT(25, x)
165 #define OUTCONTROL0_FCI(x) SET_BIT(24, x)
166 #define OUTCONTROL0_BFTH(x) SET_BITS(23, 20, x)
167 #define OUTCONTROL0_OF(x) SET_BITS(19, 18, x)
168 #define OUTCONTROL0_IPM(x) SET_BITS(17, 16, x)
169 #define OUTCONTROL0_TH(x) SET_BITS(5, 0, x)
170
171 #define OUTCONTROL0_TIE_GET(x) GET_BIT(27, x)
172 #define OUTCONTROL0_SIP_GET(x) GET_BIT(26, x)
173 #define OUTCONTROL0_FINIT_GET(x) GET_BIT(25, x)
174 #define OUTCONTROL0_FCI_GET(x) GET_BIT(24, x)
175 #define OUTCONTROL0_BFTH_GET(x) GET_BITS(23, 20, x)
176 #define OUTCONTROL0_OF_GET(x) GET_BITS(19, 18, x)
177 #define OUTCONTROL0_IPM_GET(x) GET_BITS(17, 16, x)
178 #define OUTCONTROL0_TH_GET(x) GET_BITS(5, 0, x)
179
180 /* OUTCONTROL1 bits */
181 #define OUTCONTROL1_TIE_BIT BIT(27)
182 #define OUTCONTROL1_SIP_BIT BIT(26)
183 #define OUTCONTROL1_FINIT_BIT BIT(25)
184 #define OUTCONTROL1_FCI_BIT BIT(24)
185 #define OUTCONTROL1_TIE(x) SET_BIT(27, x)
186 #define OUTCONTROL1_SIP(x) SET_BIT(26, x)
187 #define OUTCONTROL1_FINIT(x) SET_BIT(25, x)
188 #define OUTCONTROL1_FCI(x) SET_BIT(24, x)
189 #define OUTCONTROL1_BFTH(x) SET_BITS(23, 20, x)
190 #define OUTCONTROL1_OF(x) SET_BITS(19, 18, x)
191 #define OUTCONTROL1_IPM(x) SET_BITS(17, 16, x)
192 #define OUTCONTROL1_TH(x) SET_BITS(5, 0, x)
193
194 #define OUTCONTROL1_TIE_GET(x) GET_BIT(27, x)
195 #define OUTCONTROL1_SIP_GET(x) GET_BIT(26, x)
196 #define OUTCONTROL1_FINIT_GET(x) GET_BIT(25, x)
197 #define OUTCONTROL1_FCI_GET(x) GET_BIT(24, x)
198 #define OUTCONTROL1_BFTH_GET(x) GET_BITS(23, 20, x)
199 #define OUTCONTROL1_OF_GET(x) GET_BITS(19, 18, x)
200 #define OUTCONTROL1_IPM_GET(x) GET_BITS(17, 16, x)
201 #define OUTCONTROL1_TH_GET(x) GET_BITS(5, 0, x)
202 #endif
203
204 #if defined DMIC_IPM_VER2
205 /* OUTCONTROL0 bits */
206 #define OUTCONTROL0_TIE_BIT BIT(27)
207 #define OUTCONTROL0_SIP_BIT BIT(26)
208 #define OUTCONTROL0_FINIT_BIT BIT(25)
209 #define OUTCONTROL0_FCI_BIT BIT(24)
210 #define OUTCONTROL0_TIE(x) SET_BIT(27, x)
211 #define OUTCONTROL0_SIP(x) SET_BIT(26, x)
212 #define OUTCONTROL0_FINIT(x) SET_BIT(25, x)
213 #define OUTCONTROL0_FCI(x) SET_BIT(24, x)
214 #define OUTCONTROL0_BFTH(x) SET_BITS(23, 20, x)
215 #define OUTCONTROL0_OF(x) SET_BITS(19, 18, x)
216 #define OUTCONTROL0_IPM(x) SET_BITS(17, 15, x)
217 #define OUTCONTROL0_IPM_SOURCE_1(x) SET_BITS(14, 13, x)
218 #define OUTCONTROL0_IPM_SOURCE_2(x) SET_BITS(12, 11, x)
219 #define OUTCONTROL0_IPM_SOURCE_3(x) SET_BITS(10, 9, x)
220 #define OUTCONTROL0_IPM_SOURCE_4(x) SET_BITS(8, 7, x)
221 #define OUTCONTROL0_TH(x) SET_BITS(5, 0, x)
222 #define OUTCONTROL0_TIE_GET(x) GET_BIT(27, x)
223 #define OUTCONTROL0_SIP_GET(x) GET_BIT(26, x)
224 #define OUTCONTROL0_FINIT_GET(x) GET_BIT(25, x)
225 #define OUTCONTROL0_FCI_GET(x) GET_BIT(24, x)
226 #define OUTCONTROL0_BFTH_GET(x) GET_BITS(23, 20, x)
227 #define OUTCONTROL0_OF_GET(x) GET_BITS(19, 18, x)
228 #define OUTCONTROL0_IPM_GET(x) GET_BITS(17, 15, x)
229 #define OUTCONTROL0_IPM_SOURCE_1_GET(x) GET_BITS(14, 13, x)
230 #define OUTCONTROL0_IPM_SOURCE_2_GET(x) GET_BITS(12, 11, x)
231 #define OUTCONTROL0_IPM_SOURCE_3_GET(x) GET_BITS(10, 9, x)
232 #define OUTCONTROL0_IPM_SOURCE_4_GET(x) GET_BITS(8, 7, x)
233 #define OUTCONTROL0_TH_GET(x) GET_BITS(5, 0, x)
234
235 /* OUTCONTROL1 bits */
236 #define OUTCONTROL1_TIE_BIT BIT(27)
237 #define OUTCONTROL1_SIP_BIT BIT(26)
238 #define OUTCONTROL1_FINIT_BIT BIT(25)
239 #define OUTCONTROL1_FCI_BIT BIT(24)
240 #define OUTCONTROL1_TIE(x) SET_BIT(27, x)
241 #define OUTCONTROL1_SIP(x) SET_BIT(26, x)
242 #define OUTCONTROL1_FINIT(x) SET_BIT(25, x)
243 #define OUTCONTROL1_FCI(x) SET_BIT(24, x)
244 #define OUTCONTROL1_BFTH(x) SET_BITS(23, 20, x)
245 #define OUTCONTROL1_OF(x) SET_BITS(19, 18, x)
246 #define OUTCONTROL1_IPM(x) SET_BITS(17, 15, x)
247 #define OUTCONTROL1_IPM_SOURCE_1(x) SET_BITS(14, 13, x)
248 #define OUTCONTROL1_IPM_SOURCE_2(x) SET_BITS(12, 11, x)
249 #define OUTCONTROL1_IPM_SOURCE_3(x) SET_BITS(10, 9, x)
250 #define OUTCONTROL1_IPM_SOURCE_4(x) SET_BITS(8, 7, x)
251 #define OUTCONTROL1_TH(x) SET_BITS(5, 0, x)
252 #define OUTCONTROL1_TIE_GET(x) GET_BIT(27, x)
253 #define OUTCONTROL1_SIP_GET(x) GET_BIT(26, x)
254 #define OUTCONTROL1_FINIT_GET(x) GET_BIT(25, x)
255 #define OUTCONTROL1_FCI_GET(x) GET_BIT(24, x)
256 #define OUTCONTROL1_BFTH_GET(x) GET_BITS(23, 20, x)
257 #define OUTCONTROL1_OF_GET(x) GET_BITS(19, 18, x)
258 #define OUTCONTROL1_IPM_GET(x) GET_BITS(17, 15, x)
259 #define OUTCONTROL1_IPM_SOURCE_1_GET(x) GET_BITS(14, 13, x)
260 #define OUTCONTROL1_IPM_SOURCE_2_GET(x) GET_BITS(12, 11, x)
261 #define OUTCONTROL1_IPM_SOURCE_3_GET(x) GET_BITS(10, 9, x)
262 #define OUTCONTROL1_IPM_SOURCE_4_GET(x) GET_BITS(8, 7, x)
263 #define OUTCONTROL1_TH_GET(x) GET_BITS(5, 0, x)
264
265 #define OUTCONTROLX_IPM_NUMSOURCES 4
266
267 #endif
268
269 /* OUTSTAT0 bits */
270 #define OUTSTAT0_AFE_BIT BIT(31)
271 #define OUTSTAT0_ASNE_BIT BIT(29)
272 #define OUTSTAT0_RFS_BIT BIT(28)
273 #define OUTSTAT0_ROR_BIT BIT(27)
274 #define OUTSTAT0_FL_MASK MASK(6, 0)
275
276 /* OUTSTAT1 bits */
277 #define OUTSTAT1_AFE_BIT BIT(31)
278 #define OUTSTAT1_ASNE_BIT BIT(29)
279 #define OUTSTAT1_RFS_BIT BIT(28)
280 #define OUTSTAT1_ROR_BIT BIT(27)
281 #define OUTSTAT1_FL_MASK MASK(6, 0)
282
283 /* CIC_CONTROL bits */
284 #define CIC_CONTROL_SOFT_RESET_BIT BIT(16)
285 #define CIC_CONTROL_CIC_START_B_BIT BIT(15)
286 #define CIC_CONTROL_CIC_START_A_BIT BIT(14)
287 #define CIC_CONTROL_MIC_B_POLARITY_BIT BIT(3)
288 #define CIC_CONTROL_MIC_A_POLARITY_BIT BIT(2)
289 #define CIC_CONTROL_MIC_MUTE_BIT BIT(1)
290 #define CIC_CONTROL_STEREO_MODE_BIT BIT(0)
291
292 #define CIC_CONTROL_SOFT_RESET(x) SET_BIT(16, x)
293 #define CIC_CONTROL_CIC_START_B(x) SET_BIT(15, x)
294 #define CIC_CONTROL_CIC_START_A(x) SET_BIT(14, x)
295 #define CIC_CONTROL_MIC_B_POLARITY(x) SET_BIT(3, x)
296 #define CIC_CONTROL_MIC_A_POLARITY(x) SET_BIT(2, x)
297 #define CIC_CONTROL_MIC_MUTE(x) SET_BIT(1, x)
298 #define CIC_CONTROL_STEREO_MODE(x) SET_BIT(0, x)
299
300 #define CIC_CONTROL_SOFT_RESET_GET(x) GET_BIT(16, x)
301 #define CIC_CONTROL_CIC_START_B_GET(x) GET_BIT(15, x)
302 #define CIC_CONTROL_CIC_START_A_GET(x) GET_BIT(14, x)
303 #define CIC_CONTROL_MIC_B_POLARITY_GET(x) GET_BIT(3, x)
304 #define CIC_CONTROL_MIC_A_POLARITY_GET(x) GET_BIT(2, x)
305 #define CIC_CONTROL_MIC_MUTE_GET(x) GET_BIT(1, x)
306 #define CIC_CONTROL_STEREO_MODE_GET(x) GET_BIT(0, x)
307
308 /* CIC_CONFIG bits */
309 #define CIC_CONFIG_CIC_SHIFT(x) SET_BITS(27, 24, x)
310 #define CIC_CONFIG_COMB_COUNT(x) SET_BITS(15, 8, x)
311
312 /* CIC_CONFIG masks */
313 #define CIC_CONFIG_CIC_SHIFT_MASK MASK(27, 24)
314 #define CIC_CONFIG_COMB_COUNT_MASK MASK(15, 8)
315
316 #define CIC_CONFIG_CIC_SHIFT_GET(x) GET_BITS(27, 24, x)
317 #define CIC_CONFIG_COMB_COUNT_GET(x) GET_BITS(15, 8, x)
318
319 /* MIC_CONTROL bits */
320 #define MIC_CONTROL_PDM_EN_B_BIT BIT(1)
321 #define MIC_CONTROL_PDM_EN_A_BIT BIT(0)
322 #define MIC_CONTROL_PDM_CLKDIV(x) SET_BITS(15, 8, x)
323 #define MIC_CONTROL_PDM_SKEW(x) SET_BITS(7, 4, x)
324 #define MIC_CONTROL_CLK_EDGE(x) SET_BIT(3, x)
325 #define MIC_CONTROL_PDM_EN_B(x) SET_BIT(1, x)
326 #define MIC_CONTROL_PDM_EN_A(x) SET_BIT(0, x)
327
328 /* MIC_CONTROL masks */
329 #define MIC_CONTROL_PDM_CLKDIV_MASK MASK(15, 8)
330
331 #define MIC_CONTROL_PDM_CLKDIV_GET(x) GET_BITS(15, 8, x)
332 #define MIC_CONTROL_PDM_SKEW_GET(x) GET_BITS(7, 4, x)
333 #define MIC_CONTROL_PDM_CLK_EDGE_GET(x) GET_BIT(3, x)
334 #define MIC_CONTROL_PDM_EN_B_GET(x) GET_BIT(1, x)
335 #define MIC_CONTROL_PDM_EN_A_GET(x) GET_BIT(0, x)
336
337 /* FIR_CONTROL_A bits */
338 #define FIR_CONTROL_A_START_BIT BIT(7)
339 #define FIR_CONTROL_A_ARRAY_START_EN_BIT BIT(6)
340 #define FIR_CONTROL_A_MUTE_BIT BIT(1)
341 #define FIR_CONTROL_A_START(x) SET_BIT(7, x)
342 #define FIR_CONTROL_A_ARRAY_START_EN(x) SET_BIT(6, x)
343 #define FIR_CONTROL_A_DCCOMP(x) SET_BIT(4, x)
344 #define FIR_CONTROL_A_MUTE(x) SET_BIT(1, x)
345 #define FIR_CONTROL_A_STEREO(x) SET_BIT(0, x)
346
347 #define FIR_CONTROL_A_START_GET(x) GET_BIT(7, x)
348 #define FIR_CONTROL_A_ARRAY_START_EN_GET(x) GET_BIT(6, x)
349 #define FIR_CONTROL_A_DCCOMP_GET(x) GET_BIT(4, x)
350 #define FIR_CONTROL_A_MUTE_GET(x) GET_BIT(1, x)
351 #define FIR_CONTROL_A_STEREO_GET(x) GET_BIT(0, x)
352
353 /* FIR_CONFIG_A bits */
354 #define FIR_CONFIG_A_FIR_DECIMATION(x) SET_BITS(20, 16, x)
355 #define FIR_CONFIG_A_FIR_SHIFT(x) SET_BITS(11, 8, x)
356 #define FIR_CONFIG_A_FIR_LENGTH(x) SET_BITS(7, 0, x)
357
358 #define FIR_CONFIG_A_FIR_DECIMATION_GET(x) GET_BITS(20, 16, x)
359 #define FIR_CONFIG_A_FIR_SHIFT_GET(x) GET_BITS(11, 8, x)
360 #define FIR_CONFIG_A_FIR_LENGTH_GET(x) GET_BITS(7, 0, x)
361
362 /* DC offset compensation time constants */
363 #define DCCOMP_TC0 0
364 #define DCCOMP_TC1 1
365 #define DCCOMP_TC2 2
366 #define DCCOMP_TC3 3
367 #define DCCOMP_TC4 4
368 #define DCCOMP_TC5 5
369 #define DCCOMP_TC6 6
370 #define DCCOMP_TC7 7
371
372 /* DC_OFFSET_LEFT_A bits */
373 #define DC_OFFSET_LEFT_A_DC_OFFS(x) SET_BITS(21, 0, x)
374
375 /* DC_OFFSET_RIGHT_A bits */
376 #define DC_OFFSET_RIGHT_A_DC_OFFS(x) SET_BITS(21, 0, x)
377
378 /* OUT_GAIN_LEFT_A bits */
379 #define OUT_GAIN_LEFT_A_GAIN(x) SET_BITS(19, 0, x)
380
381 /* OUT_GAIN_RIGHT_A bits */
382 #define OUT_GAIN_RIGHT_A_GAIN(x) SET_BITS(19, 0, x)
383
384 /* FIR_CONTROL_B bits */
385 #define FIR_CONTROL_B_START_BIT BIT(7)
386 #define FIR_CONTROL_B_ARRAY_START_EN_BIT BIT(6)
387 #define FIR_CONTROL_B_MUTE_BIT BIT(1)
388 #define FIR_CONTROL_B_START(x) SET_BIT(7, x)
389 #define FIR_CONTROL_B_ARRAY_START_EN(x) SET_BIT(6, x)
390 #define FIR_CONTROL_B_DCCOMP(x) SET_BIT(4, x)
391 #define FIR_CONTROL_B_MUTE(x) SET_BIT(1, x)
392 #define FIR_CONTROL_B_STEREO(x) SET_BIT(0, x)
393
394 #define FIR_CONTROL_B_START_GET(x) GET_BIT(7, x)
395 #define FIR_CONTROL_B_ARRAY_START_EN_GET(x) GET_BIT(6, x)
396 #define FIR_CONTROL_B_DCCOMP_GET(x) GET_BIT(4, x)
397 #define FIR_CONTROL_B_MUTE_GET(x) GET_BIT(1, x)
398 #define FIR_CONTROL_B_STEREO_GET(x) GET_BIT(0, x)
399
400 /* FIR_CONFIG_B bits */
401 #define FIR_CONFIG_B_FIR_DECIMATION(x) SET_BITS(20, 16, x)
402 #define FIR_CONFIG_B_FIR_SHIFT(x) SET_BITS(11, 8, x)
403 #define FIR_CONFIG_B_FIR_LENGTH(x) SET_BITS(7, 0, x)
404
405 #define FIR_CONFIG_B_FIR_DECIMATION_GET(x) GET_BITS(20, 16, x)
406 #define FIR_CONFIG_B_FIR_SHIFT_GET(x) GET_BITS(11, 8, x)
407 #define FIR_CONFIG_B_FIR_LENGTH_GET(x) GET_BITS(7, 0, x)
408
409 /* DC_OFFSET_LEFT_B bits */
410 #define DC_OFFSET_LEFT_B_DC_OFFS(x) SET_BITS(21, 0, x)
411
412 /* DC_OFFSET_RIGHT_B bits */
413 #define DC_OFFSET_RIGHT_B_DC_OFFS(x) SET_BITS(21, 0, x)
414
415 /* OUT_GAIN_LEFT_B bits */
416 #define OUT_GAIN_LEFT_B_GAIN(x) SET_BITS(19, 0, x)
417
418 /* OUT_GAIN_RIGHT_B bits */
419 #define OUT_GAIN_RIGHT_B_GAIN(x) SET_BITS(19, 0, x)
420
421 /* FIR coefficients */
422 #define FIR_COEF_A(x) SET_BITS(19, 0, x)
423 #define FIR_COEF_B(x) SET_BITS(19, 0, x)
424
425 /* Used for scaling FIR coefficients for HW */
426 #define DMIC_HW_FIR_COEF_MAX ((1 << (DMIC_HW_BITS_FIR_COEF - 1)) - 1)
427 #define DMIC_HW_FIR_COEF_Q (DMIC_HW_BITS_FIR_COEF - 1)
428
429 /* Internal precision in gains computation, e.g. Q4.28 in int32_t */
430 #define DMIC_FIR_SCALE_Q 28
431
432 /* Used in unmute ramp values calculation */
433 #define DMIC_HW_FIR_GAIN_MAX ((1 << (DMIC_HW_BITS_FIR_GAIN - 1)) - 1)
434
435 /* Hardwired log ramp parameters. The first value is the initial gain in
436 * decibels. The default ramp time is provided by 1st order equation
437 * ramp time = coef * samplerate + offset. The default ramp is 200 ms for
438 * 48 kHz and 400 ms for 16 kHz.
439 */
440 #define LOGRAMP_START_DB Q_CONVERT_FLOAT(-90, DB2LIN_FIXED_INPUT_QY)
441 #define LOGRAMP_TIME_COEF_Q15 -205 /* dy/dx (16000,400) (48000,200) */
442 #define LOGRAMP_TIME_OFFS_Q0 500 /* Offset for line slope */
443
444 /* Limits for ramp time from topology */
445 #define LOGRAMP_TIME_MIN_MS 10 /* Min. 10 ms */
446 #define LOGRAMP_TIME_MAX_MS 1000 /* Max. 1s */
447
448 /* Simplify log ramp step calculation equation with this constant term */
449 #define LOGRAMP_CONST_TERM ((int32_t) \
450 ((int64_t)-LOGRAMP_START_DB * DMIC_UNMUTE_RAMP_US / 1000))
451
452 /* Fractional shift for gain update. Gain format is Q2.30. */
453 #define Q_SHIFT_GAIN_X_GAIN_COEF \
454 (Q_SHIFT_BITS_32(30, DB2LIN_FIXED_OUTPUT_QY, 30))
455
456 #define dmic_irq(dmic) dmic->plat_data.irq
457 #define dmic_irq_name(dmic) dmic->plat_data.irq_name
458
459 /* Common data for all DMIC DAI instances */
460 struct dmic_global_shared {
461 struct sof_ipc_dai_dmic_params prm[DMIC_HW_FIFOS]; /* Configuration requests */
462 uint32_t active_fifos_mask; /* Bits (dai->index) are set to indicate active FIFO */
463 uint32_t pause_mask; /* Bits (dai->index) are set to indicate driver pause */
464 };
465
466 /* DMIC private data */
467 struct dmic_pdata {
468 struct dmic_global_shared *global; /* Common data for all DMIC DAI instances */
469 struct task dmicwork; /* HW gain ramp update task */
470 uint16_t enable[DMIC_HW_CONTROLLERS]; /* Mic 0 and 1 enable bits array for PDMx */
471 uint32_t state; /* Driver component state */
472 int32_t startcount; /* Counter in dmicwork that controls HW unmute */
473 int32_t gain_coef; /* Gain update constant */
474 int32_t gain; /* Gain value to be applied to HW */
475 int irq; /* Interrupt number used */
476 enum sof_ipc_frame dai_format; /* PCM format s32_le etc. */
477 int dai_channels; /* Channels count */
478 int dai_rate; /* Sample rate in Hz */
479 };
480
481 struct decim_modes {
482 int16_t clkdiv[DMIC_MAX_MODES];
483 int16_t mcic[DMIC_MAX_MODES];
484 int16_t mfir[DMIC_MAX_MODES];
485 int num_of_modes;
486 };
487
488 struct matched_modes {
489 int16_t clkdiv[DMIC_MAX_MODES];
490 int16_t mcic[DMIC_MAX_MODES];
491 int16_t mfir_a[DMIC_MAX_MODES];
492 int16_t mfir_b[DMIC_MAX_MODES];
493 int num_of_modes;
494 };
495
496 struct dmic_configuration {
497 struct pdm_decim *fir_a;
498 struct pdm_decim *fir_b;
499 int clkdiv;
500 int mcic;
501 int mfir_a;
502 int mfir_b;
503 int cic_shift;
504 int fir_a_shift;
505 int fir_b_shift;
506 int fir_a_length;
507 int fir_b_length;
508 int32_t fir_a_scale;
509 int32_t fir_b_scale;
510 };
511
512 struct nhlt_dmic_gateway_attributes {
513 uint32_t dw;
514 };
515
516 struct nhlt_dmic_ts_group {
517 uint32_t ts_group[4];
518 };
519
520 struct nhlt_dmic_clock_on_delay {
521 uint32_t clock_on_delay;
522 };
523
524 struct nhlt_dmic_channel_ctrl_mask {
525 uint32_t channel_ctrl_mask;
526 };
527
528 struct nhlt_pdm_ctrl_mask {
529 uint32_t pdm_ctrl_mask;
530 };
531
532 struct nhlt_pdm_ctrl_cfg {
533 uint32_t cic_control;
534 uint32_t cic_config;
535 uint32_t reserved0;
536 uint32_t mic_control;
537 uint32_t pdm_sdw_map;
538 uint32_t reuse_fir_from_pdm;
539 uint32_t reserved1[2];
540 };
541
542 struct nhlt_pdm_ctrl_fir_cfg {
543 uint32_t fir_control;
544 uint32_t fir_config;
545 int32_t dc_offset_left;
546 int32_t dc_offset_right;
547 int32_t out_gain_left;
548 int32_t out_gain_right;
549 uint32_t reserved[2];
550 };
551
552 struct nhlt_pdm_fir_coeffs {
553 int32_t fir_coeffs[0];
554 };
555
556 int dmic_set_config_computed(struct dai *dai);
557 int dmic_get_hw_params_computed(struct dai *dai, struct sof_ipc_stream_params *params, int dir);
558 int dmic_set_config_nhlt(struct dai *dai, void *spec_config);
559 int dmic_get_hw_params_nhlt(struct dai *dai, struct sof_ipc_stream_params *params, int dir);
560
561 extern const struct dai_driver dmic_driver;
562
dmic_get_unmute_ramp_from_samplerate(int rate)563 static inline int dmic_get_unmute_ramp_from_samplerate(int rate)
564 {
565 int time_ms;
566
567 time_ms = Q_MULTSR_32X32((int32_t)rate, LOGRAMP_TIME_COEF_Q15, 0, 15, 0) +
568 LOGRAMP_TIME_OFFS_Q0;
569 if (time_ms > LOGRAMP_TIME_MAX_MS)
570 return LOGRAMP_TIME_MAX_MS;
571
572 if (time_ms < LOGRAMP_TIME_MIN_MS)
573 return LOGRAMP_TIME_MIN_MS;
574
575 return time_ms;
576 }
577
578 #endif /* DMIC_HW_VERSION */
579 #endif /* __SOF_DRIVERS_DMIC_H__ */
580
