Searched refs:ldp (Results 1 – 7 of 7) sorted by relevance
| /Zephyr-latest/arch/arm64/core/ |
| D | fpu.S | 43 ldp q0, q1, [x0, #(16 * 0)]
44 ldp q2, q3, [x0, #(16 * 2)]
45 ldp q4, q5, [x0, #(16 * 4)]
46 ldp q6, q7, [x0, #(16 * 6)]
47 ldp q8, q9, [x0, #(16 * 8)]
48 ldp q10, q11, [x0, #(16 * 10)]
49 ldp q12, q13, [x0, #(16 * 12)]
50 ldp q14, q15, [x0, #(16 * 14)]
51 ldp q16, q17, [x0, #(16 * 16)]
52 ldp q18, q19, [x0, #(16 * 18)]
[all …]
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| D | vector_table.S | 274 ldp x16, x17, [x18, -(___esf_t_SIZEOF - ___esf_t_x16_x17_OFFSET)]
276 ldp x16, x17, [x18, -(___esf_t_SIZEOF - ___esf_t_x18_lr_OFFSET)]
311 ldp x0, x1, [sp, ___esf_t_spsr_elr_OFFSET]
331 ldp x0, x1, [sp, ___esf_t_x0_x1_OFFSET]
332 ldp x2, x3, [sp, ___esf_t_x2_x3_OFFSET]
333 ldp x4, x5, [sp, ___esf_t_x4_x5_OFFSET]
334 ldp x6, x7, [sp, ___esf_t_x6_x7_OFFSET]
335 ldp x8, x9, [sp, ___esf_t_x8_x9_OFFSET]
336 ldp x10, x11, [sp, ___esf_t_x10_x11_OFFSET]
337 ldp x12, x13, [sp, ___esf_t_x12_x13_OFFSET]
[all …]
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| D | switch.S | 74 ldp x0, x1, [sp], #16
93 ldp x19, x20, [x0, #_thread_offset_to_callee_saved_x19_x20]
94 ldp x21, x22, [x0, #_thread_offset_to_callee_saved_x21_x22]
95 ldp x23, x24, [x0, #_thread_offset_to_callee_saved_x23_x24]
96 ldp x25, x26, [x0, #_thread_offset_to_callee_saved_x25_x26]
97 ldp x27, x28, [x0, #_thread_offset_to_callee_saved_x27_x28]
99 ldp x29, x4, [x0, #_thread_offset_to_callee_saved_x29_sp_el0]
108 ldp x4, lr, [x0, #_thread_offset_to_callee_saved_sp_elx_lr]
180 ldp x1, x0, [sp, ___esf_t_x0_x1_OFFSET]
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| D | userspace.S | 96 ldp x0, x1, [sp, ___esf_t_x0_x1_OFFSET]
97 ldp x2, x3, [sp, ___esf_t_x2_x3_OFFSET]
98 ldp x4, x5, [sp, ___esf_t_x4_x5_OFFSET]
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| D | isr_wrapper.S | 90 ldp x0, x3, [x1] /* arg in x0, ISR in x3 */
101 ldp x0, xzr, [sp], #16
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| D | cpu_idle.S | 36 ldp x0, lr, [sp], #16
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| D | CMakeLists.txt | 51 # GCC may generate ldp/stp instructions with the Advanced SIMD Qn registers for
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