1 /*
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright © 2019 Keith Packard
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * 3. Neither the name of the copyright holder nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
26 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
31 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
33 * OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36 #include "../../crt0.h"
37
38 #if __ARM_ARCH_PROFILE == 'M'
39
40 /*
41 * Cortex-mM includes an NVIC and starts with SP initialized, so start
42 * is a C function
43 */
44
45 extern const void *__interrupt_vector[];
46
47 #define CPACR ((volatile uint32_t *) (0xE000ED88))
48
49 #ifdef __clang__
50 const void *__interrupt_reference = __interrupt_vector;
51 #endif
52
53 void
_start(void)54 _start(void)
55 {
56 /* Generate a reference to __interrupt_vector so we get one loaded */
57 __asm__(".equ __my_interrupt_vector, __interrupt_vector");
58 /* Access to the coprocessor has to be enabled in CPACR, if either FPU or
59 * MVE is used. This is described in "Arm v8-M Architecture Reference
60 * Manual". */
61 #if defined __ARM_FP || defined __ARM_FEATURE_MVE
62 /* Enable FPU */
63 *CPACR |= 0xf << 20;
64 /*
65 * Wait for the write enabling FPU to reach memory before
66 * executing the instruction accessing the status register
67 */
68 __asm__("dsb");
69 __asm__("isb");
70
71 /* Clear FPU status register. 0x40000 will initialize FPSCR.LTPSIZE to
72 * a valid value for 8.1-m low overhead loops. */
73 #if __ARM_ARCH >= 8 && __ARM_ARCH_PROFILE == 'M'
74 #define INIT_FPSCR 0x40000
75 #else
76 #define INIT_FPSCR 0x0
77 #endif
78 __asm__("vmsr fpscr, %0" : : "r" (INIT_FPSCR));
79 #endif
80 __start();
81 }
82
83 #else
84
85 /*
86 * Regular ARM has an 8-entry exception vector and starts without SP
87 * initialized, so start is a naked function
88 */
89
90 static void __attribute__((used)) __section(".init")
_cstart(void)91 _cstart(void)
92 {
93 __start();
94 }
95
96 extern char __stack[];
97
98 void __attribute__((naked)) __section(".init") __attribute__((used))
_start(void)99 _start(void)
100 {
101 /* Generate a reference to __vector_table so we get one loaded */
102 __asm__(".equ __my_vector_table, __vector_table");
103
104 /* Initialize stack pointer */
105 __asm__("mov sp, %0" : : "r" (__stack));
106
107 #ifdef __thumb2__
108 /* Make exceptions run in Thumb mode */
109 uint32_t sctlr;
110 __asm__("mrc p15, 0, %0, c1, c0, 0" : "=r" (sctlr));
111 sctlr |= (1 << 30);
112 __asm__("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
113 #endif
114 #if defined __ARM_FP || defined __ARM_FEATURE_MVE
115 #if __ARM_ARCH > 6
116 /* Set CPACR for access to CP10 and 11 */
117 __asm__("mcr p15, 0, %0, c1, c0, 2" : : "r" (0xf << 20));
118 #endif
119 /* Enable FPU */
120 __asm__("vmsr fpexc, %0" : : "r" (0x40000000));
121 #endif
122
123 /* Branch to C code */
124 __asm__("b _cstart");
125 }
126
127 #endif
128
129 #ifdef CRT0_SEMIHOST
130
131 /*
132 * Trap faults, print message and exit when running under semihost
133 */
134
135 #include <semihost.h>
136 #include <unistd.h>
137 #include <stdio.h>
138
139 #define _REASON(r) #r
140 #define REASON(r) _REASON(r)
141
142 #if __ARM_ARCH_PROFILE == 'M'
143
144 #define GET_SP struct fault *sp; __asm__ ("mov %0, sp" : "=r" (sp))
145
146 struct fault {
147 unsigned int r0;
148 unsigned int r1;
149 unsigned int r2;
150 unsigned int r3;
151 unsigned int r12;
152 unsigned int lr;
153 unsigned int pc;
154 unsigned int xpsr;
155 };
156
157 static const char *const reasons[] = {
158 "hardfault",
159 "memmanage",
160 "busfault",
161 "usagefault"
162 };
163
164 #define REASON_HARDFAULT 0
165 #define REASON_MEMMANAGE 1
166 #define REASON_BUSFAULT 2
167 #define REASON_USAGE 3
168
169 static void __attribute__((used))
arm_fault(struct fault * f,int reason)170 arm_fault(struct fault *f, int reason)
171 {
172 printf("ARM fault: %s\n", reasons[reason]);
173 printf("\tR0: 0x%08x\n", f->r0);
174 printf("\tR1: 0x%08x\n", f->r1);
175 printf("\tR2: 0x%08x\n", f->r2);
176 printf("\tR3: 0x%08x\n", f->r3);
177 printf("\tR12: 0x%08x\n", f->r12);
178 printf("\tLR: 0x%08x\n", f->lr);
179 printf("\tPC: 0x%08x\n", f->pc);
180 printf("\tXPSR: 0x%08x\n", f->xpsr);
181 _exit(1);
182 }
183
184 void __attribute__((naked))
arm_hardfault_isr(void)185 arm_hardfault_isr(void)
186 {
187 __asm__("mov r0, sp");
188 __asm__("movs r1, #" REASON(REASON_HARDFAULT));
189 __asm__("bl arm_fault");
190 }
191
192 void __attribute__((naked))
arm_memmange_isr(void)193 arm_memmange_isr(void)
194 {
195 __asm__("mov r0, sp");
196 __asm__("movs r1, #" REASON(REASON_MEMMANAGE));
197 __asm__("bl arm_fault");
198 }
199
200 void __attribute__((naked))
arm_busfault_isr(void)201 arm_busfault_isr(void)
202 {
203 __asm__("mov r0, sp");
204 __asm__("movs r1, #" REASON(REASON_BUSFAULT));
205 __asm__("bl arm_fault");
206 }
207
208 void __attribute__((naked))
arm_usagefault_isr(void)209 arm_usagefault_isr(void)
210 {
211 __asm__("mov r0, sp");
212 __asm__("movs r1, #" REASON(REASON_USAGE));
213 __asm__("bl arm_fault");
214 }
215
216 #else
217
218 struct fault {
219 unsigned int r[7];
220 unsigned int pc;
221 };
222
223 static const char *const reasons[] = {
224 "undef",
225 "svc",
226 "prefetch_abort",
227 "data_abort"
228 };
229
230 #define REASON_UNDEF 0
231 #define REASON_SVC 1
232 #define REASON_PREFETCH_ABORT 2
233 #define REASON_DATA_ABORT 3
234
235 static void __attribute__((used))
arm_fault(struct fault * f,int reason)236 arm_fault(struct fault *f, int reason)
237 {
238 int r;
239 printf("ARM fault: %s\n", reasons[reason]);
240 for (r = 0; r <= 6; r++)
241 printf("\tR%d: 0x%08x\n", r, f->r[r]);
242 printf("\tPC: 0x%08x\n", f->pc);
243 _exit(1);
244 }
245
246 #define VECTOR_COMMON \
247 __asm__("mov r7, %0" : : "r" (__stack)); \
248 __asm__("mov sp, r7"); \
249 __asm__("push {lr}"); \
250 __asm__("push {r0-r6}"); \
251 __asm__("mov r0, sp")
252
253 void __attribute__((naked)) __section(".init")
arm_undef_vector(void)254 arm_undef_vector(void)
255 {
256 VECTOR_COMMON;
257 __asm__("mov r1, #" REASON(REASON_UNDEF));
258 __asm__("bl arm_fault");
259 }
260
261 void __attribute__((naked)) __section(".init")
arm_prefetch_abort_vector(void)262 arm_prefetch_abort_vector(void)
263 {
264 VECTOR_COMMON;
265 __asm__("mov r1, #" REASON(REASON_UNDEF));
266 __asm__("bl arm_fault");
267 }
268
269 void __attribute__((naked)) __section(".init")
arm_data_abort_vector(void)270 arm_data_abort_vector(void)
271 {
272 VECTOR_COMMON;
273 __asm__("mov r1, #" REASON(REASON_UNDEF));
274 __asm__("bl arm_fault");
275 }
276
277 #endif
278
279 #endif
280
281
